FEATURES
■
100% Tested Low Voltage Noise: 2.7nV/√Hz Typ
4.2nV/√Hz Max
■
Slew Rate: 4.5V/µs Typ
■
Gain Bandwidth Product: 12.5MHz Typ
■
Offset Voltage, Prime Grade: 70µV Max
Low Grade: 100µV Max
■
High Voltage Gain: 5 Million Min
■
Supply Current Per Amplifier: 2.75mA Max
■
Common Mode Rejection: 112dB Min
■
Power Supply Rejection: 116dB Min
■
Available in 8-Pin SO Package
U
APPLICATIO S
■
Two and Three Op Amp Instrumentation Amplifiers
■
Low Noise Signal Processing
■
Active Filters
■
Microvolt Accuracy Threshold Detection
■
Strain Gauge Amplifiers
■
Direct Coupled Audio Gain Stages
■
Tape Head Preamplifiers
■
Infrared Detectors
, LTC and LT are registered trademarks of Linear Technology Corporation.
Protected by U.S. patents 4,775,884 and 4,837,496.
LT1124/LT1125
Dual/Quad Low Noise,
High Speed Precision Op Amps
U
DESCRIPTIO
The LT®1124 dual and LT1125 quad are high performance
op amps that offer higher gain, slew rate and bandwidth
than the industry standard OP-27 and competing OP-270/
OP-470 op amps. In addition, the LT1124/LT1125 have
lower IB and I
than the OP-270/OP-470.
In the design, processing and testing of the device, particular attention has been paid to the optimization of the
entire distribution of several key parameters. Slew rate,
gain bandwidth and 1kHz noise are 100% tested for each
individual amplifier. Consequently, the specifications of
even the lowest cost grades (the LT1124C and the
LT1125C) have been spectacularly improved compared
to equivalent grades of competing amplifiers.
Power consumption of the LT1124 is one half of two
OP-27s. Low power and high performance in an 8-pin SO
package make the LT1124 a first choice for surface mounted
systems and where board space is restricted.
For a decompensated version of these devices, with three
times higher slew rate and bandwidth, please see the
LT1126/LT1127 data sheet.
than the OP-27; lower VOS and noise
OS
TYPICAL APPLICATIO
Instrumentation Amplifier with Shield Driver
3
INPUT
+
1/4
LT1125
2
–
GUARD
+
8
–
GUARD
13
–
1/4
LT1125
12
+
1/4
LT1125
1
10
+
9
–
14
U
R
F
3.4k
R
G
100Ω
R
G
100Ω
R
F
3.4k
1k
30k1k
15V
5
4
+
1/4
LT1125
6
–
11
–15V
GAIN
POWER BW
SMALL-SIGNAL BW
NOISE
V
7
OUTPUT
30k
= 30 (1 + RF/RG) ≈ 1000
= 170kHz
= 400kHz
= 3.8µV/ Hz AT OUTPUT
√
= 35µV
OS
1124/25 TA01
Input Offset Voltage Distribution
(All Packages, LT1124 and LT1125)
DUALS
VS = ±15V
T
= 25°C
A
30
20
PERCENT OF UNITS
10
0
–60 –20
–100
INPUT OFFSET VOLTAGE (µV)
758
QUADS
200
2316 UNITS
TESTED
60
1124/25 TA02
10020
1
LT1124/LT1125
1
2
3
4
8
7
6
5
TOP VIEW
OUT A
–IN A
+IN A
V
–
V
+
OUT B
–IN B
+IN B
N8 PACKAGE
8-LEAD PDIP
J8 PACKAGE
8-LEAD CERDIP
A
B
1
2
3
4
5
6
7
TOP VIEW
N PACKAGE
14-LEAD PDIP
J PACKAGE
14-LEAD CERDIP
14
13
12
11
10
9
8
OUT A
–IN A
+IN A
V
+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V
–
+IN C
–IN C
OUT C
B
A
C
D
A
W
O
LUTEXI TIS
S
A
WUW
U
(Note 1)
ARB
G
Supply Voltage ..................................................... ±22V
Input Voltages ......................... Equal to Supply Voltage
Output Short-Circuit Duration......................... Indefinite
Differential Input Current (Note 6) ..................... ±25mA
Lead Temperature (Soldering, 10 sec)................. 300°C
Storage Temperature Range ................ –65°C to 150°C
/
PACKAGE
+IN A
–
V
+IN B
–IN B
T
NOTE: THIS PIN CONFIGURATION DIFFERS FROM THE
8-PIN PDIP CONFIGURATION. INSTEAD, IT FOLLOWS
THE INDUSTRY STANDARD LT1013DS8 SO PACKAGE
PIN LOCATIONS
O
RDER I FOR ATIO
TOP VIEW
1
2
A
3
B
4
S8 PACKAGE
8-LEAD PLASTIC SO
= 140°C, θJA = 190°C
JMAX
8
–IN A
OUT A
7
+
V
6
OUT B
5
WU
ORDER PART
NUMBER
LT1124CS8
LT1124AIS8
LT1124IS8
S8 PART MARKING
1124
1124AI
1124I
U
Operating Temperature Range
LT1124AC/LT1124C
LT1125AC/LT1125C (Note 10) .......... – 40°C to 85°C
LT1124AI/LT1124I ............................ –40°C to 85°C
LT1124AM/LT1124M
LT1125AM/LT1125M ...................... –55°C to 125°C
ORDER PART
NUMBER
LT1124CJ8
LT1124ACN8
LT1124CN8
LT1124AMJ8
LT1124MJ8
T
= 160°C, θJA = 100°C (J8)
JMAX
= 140°C, θJA = 130°C (N8)
T
JMAX
TOP VIEW
1
OUT A
2
–IN A
+IN A
+
V
+IN B
–IN B
OUT B
NC
LECTRICAL C CHARA TERIST
E
A
3
4
5
B
6
7
8
SW PACKAGE
16-LEAD PLASTIC (WIDE) SO
T
= 140°C, θJA = 130°C
JMAX
16
OUT D
15
D
C
–IN D
14
+IN D
–
13
V
12
+IN C
11
–IN C
10
OUT C
9
NC
LT1125CS
ICS
TA = 25°C, VS = ±15V, unless otherwise noted.
T
= 160°C, θJA = 80°C (J)
JMAX
T
= 140°C, θJA = 110°C (N)
JMAX
LT1125CJ
LT1125ACN
LT1125CN
LT1125AMJ
LT1125MJ
LT1124AC/AI/AM LT1124/C/I/M
LT1125AC/AM LT1125/C/M
SYMBOL PARAMETER CONDITIONS (Note 2) MIN TYP MAX MIN TYP MAX UNITS
V
OS
∆V
OS
∆Time Voltage Stability
I
OS
2
Input Offset Voltage LT1124 20 70 25 100 µV
LT1125 25 90 30 140 µV
Long Term Input Offset 0.3 0.3 µV/Mo
Input Offset Current LT1124 5 15 6 20 nA
LT1125 6 20 7 30 nA
LT1124/LT1125
LECTRICAL C CHARA TERIST
E
SYMBOL PARAMETER CONDITIONS (Note 2) MIN TYP MAX MIN TYP MAX UNITS
I
B
e
n
i
n
V
CM
CMRR Common Mode Rejection Ratio VCM = ±12V 112 126 106 124 dB
PSRR Power Supply Rejection Ratio VS = ±4V to ±18V 116 126 110 124 dB
A
VOL
V
OUT
SR Slew Rate RL ≥ 2k (Notes 3, 7) 3 4.5 2.7 4.5 V/µs
GBW Gain Bandwidth Product fO = 100kHz (Note 3) 9 12.5 8 12.5 MHz
Z
O
I
S
Input Bias Current ±7 ±20 ±8 ±30 nA
Input Noise Voltage 0.1Hz to 10Hz (Notes 8, 9) 70 200 70 nV
Input Noise Voltage Density fO = 10Hz (Note 4) 3.0 5.5 3.0 5.5 nV/√Hz
f
Input Noise Current Density fO = 10Hz 1.3 1.3 pA/√Hz
f
Input Voltage Range ±12 ±12.8 ±12 ±12.8 V
Large-Signal Voltage Gain RL ≥ 10k, V
R
Maximum Output Voltage Swing RL ≥ 2k ±13 ±13.8 ±12.5 ±13.8 V
Open-Loop Output Resistance V
Supply Current per Amplifier 2.3 2.75 2.3 2.75 mA
Channel Separation f ≤ 10Hz (Note 9) 134 150 130 150 dB
V
ICS
= 1000Hz (Note 3) 2.7 4.2 2.7 4.2 nV/√Hz
O
= 1000Hz 0.3 0.3 pA/√Hz
O
≥ 2k, V
L
= 0, I
OUT
= ±10V, RL = 2k
OUT
TA = 25°C, VS = ±15V, unless otherwise noted.
LT1124AC/AI/AM LT1124C/I/M
LT1125AC/AM LT1125C/M
= ±10V 5 17 3.0 15 V/µV
OUT
= ±10V 2 4 1.5 3 V/µV
OUT
= 0 75 75 Ω
OUT
P-P
The ● denotes the specifications which apply over the –55°C ≤ TA ≤ 125°C temperature range, VS = ±15V, unless otherwise noted.
LT1124AM LT1124M
LT1125AM LT1125M
SYMBOL PARAMETER CONDITIONS (Note 2) MIN TYP MAX MIN TYP MAX UNITS
V
OS
∆V
OS
∆Temp Voltage Drift
I
OS
I
B
V
CM
CMRR Common Mode Rejection Ratio VCM = ±11.3V ● 106 122 100 120 dB
PSRR Power Supply Rejection Ratio VS = ±4V to ±18V ● 110 122 104 120 dB
A
VOL
V
OUT
SR Slew Rate RL ≥ 2k (Notes 3, 7) ● 2.3 3.8 2 3.8 V/µs
I
S
Input Offset Voltage LT1124 ● 50 170 60 250 µV
LT1125
Average Input Offset (Note 5) ● 0.3 1.0 0.4 1.5 µV/°C
Input Offset Current LT1124 ● 18 45 20 60 nA
LT1125
Input Bias Current ● ±18 ±55 ±20 ±70 nA
Input Voltage Range ● ±11.3 ±12 ±11.3 ±12 V
Large-Signal Voltage Gain RL ≥ 10k, V
≥ 2k, V
R
L
Maximum Output Voltage Swing RL ≥ 2k ● ±12.5 ±13.6 ±12 ±13.6 V
Supply Current per Amplifier ● 2.5 3.25 2.5 3.25 mA
= ±10V ● 3 10 2.0 10 V/µV
OUT
= ±10V ● 1 3 0.7 2 V/µV
OUT
● 55 190 70 290 µV
● 18 55 20 70 nA
3
LT1124/LT1125
LECTRICAL C CHARA TERIST
E
ICS
The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C
temperature range, VS = ±15V, unless otherwise noted.
LT1124AC LT1124C
SYMBOL PARAMETER CONDITIONS (Note 2) MIN TYP MAX MIN TYP MAX UNITS
V
OS
∆V
OS
∆Temp Voltage Drift
I
OS
I
B
V
CM
CMRR Common Mode Rejection Ratio VCM = ±11.5V ● 109 125 102 122 dB
PSRR Power Supply Rejection Ratio VS = ±4V to ±18V ● 112 125 107 122 dB
A
VOL
V
OUT
SR Slew Rate RL ≥ 2k (Notes 3, 7) ● 2.6 4 2.4 4 V/µs
I
S
Input Offset Voltage LT1124 ● 35 120 45 170 µV
LT1125 ● 40 140 50 210 µV
Average Input Offset (Note 5) ● 0.3 1 0.4 1.5 µV/°C
Input Offset Current LT1124 ● 625 735 nA
LT1125 ● 735 845 nA
Input Bias Current ● ±8 ±35 ±9 ±45 nA
Input Voltage Range ● ±11.5 ±12.4 ±11.5 ±12.4 V
Large-Signal Voltage Gain RL ≥ 10k, V
Maximum Output Voltage Swing RL ≥ 2k ● ±12.5 ±13.7 ±12 ±13.7 V
Supply Current per Amplifier ● 2.4 3 2.4 3 mA
≥ 2k, V
R
L
= ±10V ● 4.0 15 2.5 14 V/µV
OUT
= ±10V ● 1.5 3.5 1.0 2.5 V/µV
OUT
LT1125AC LT1125C
The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C temperature range, VS = ±15V,
unless otherwise noted. (Note 10)
LT1124AC/AI LT1124C/I
SYMBOL PARAMETER CONDITIONS (Note 2) MIN TYP MAX MIN TYP MAX UNITS
V
OS
∆V
OS
∆Temp Voltage Drift
I
OS
I
B
V
CM
CMRR Common Mode Rejection Ratio VCM = ±11.4V ● 107 124 101 121 dB
PSRR Power Supply Rejection Ratio VS = ±4V to ±18V ● 111 124 106 121 dB
A
VOL
V
OUT
SR Slew Rate RL ≥ 2k (Notes 3, 7) ● 2.4 3.9 2.1 3.9 V/µs
I
S
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Typical parameters are defined as the 60% yield of parameter
distributions of individual amplifiers; i.e., out of 100 LT1125s (or 100
LT1124s) typically 240 op amps (or 120) will be better than the indicated
specification.
Note 3: This parameter is 100% tested for each individual amplifier.
Note 4: This parameter is sample tested only.
Note 5: This parameter is not 100% tested.
Note 6: The inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise. If differential input
voltage exceeds ±1.4V, the input current should be limited to 25mA.
Input Offset Voltage LT1124 ● 40 140 50 200 µV
LT1125 ● 45 160 55 240 µV
Average Input Offset (Note 5) ● 0.3 1 0.4 1.5 µV/°C
Input Offset Current LT1124 ● 15 40 17 55 nA
Input Bias Current ● ±15 ±50 ±17 ±65 nA
Input Voltage Range ● ±11.4 ±12.2 ±11.4 ±12.2 V
Large-Signal Voltage Gain RL ≥ 10k, V
Maximum Output Voltage Swing RL ≥ 2k ● ±12.5 ±13.6 ±12 ±13.6 V
Supply Current per Amplifier ● 2.4 3.25 2.4 3.25 mA
LT1125
≥ 2k, V
R
L
= ±10V ● 3.5 12 2.2 12 V/µV
OUT
= ±10V ● 1.2 3.2 0.8 2.3 V/µV
OUT
● 15 50 17 65 nA
Note 7: Slew rate is measured in AV = –1; input signal is ±7.5V, output
measured at ±2.5V.
Note 8: 0.1Hz to 10Hz noise can be inferred from the 10Hz noise voltage
density test. See the test circuit and frequency response curve for 0.1Hz to
10Hz tester in the Applications Information section of the LT1007 or
LT1028 data sheets.
Note 9: This parameter is guaranteed but not tested.
Note 10: The LT1124C/LT1125C and LT1124AC/LT1125AC are guaranteed
to meet specified performance from 0°C to 70°C and are designed,
characterized and expected to meet these extended temperature limits, but
are not tested at –40°C and 85°C. The LT1124AI and LT1124I are
guaranteed to meet the extended temperature limits.
LT1125AC LT1125C
4
LT1124/LT1125
FREQUENCY (Hz)
1
0
POWER SUPPLY REJECTION RATIO (dB)
20
40
120
140
160
10
2
10
8
1124/25 G09
10 10310410510610
7
60
100
80
–PSRR
+PSRR
TA = 25°C
UW
LPER
F
O
R
ATYPICA
0.1Hz to 10Hz Voltage Noise 0.01Hz to 1Hz Voltage Noise Voltage Noise vs Frequency
VOLTAGE NOISE (40nV/DIV)
0
26810
4
TIME (SECONDS)
1124/25 G01
Current Noise vs Frequency vs Temperature vs Time
10.0
√
3.0
1.0
0.3
RMS CURRENT NOISE DENSITY (pA/ Hz)
0.1
10 1k 10k
1/f CORNER
100Hz
100
FREQUENCY (Hz)
VS = ±15V
= 25°C
T
A
MAXIMUM
TYPICAL
1124 G04
CCHARA TERIST
E
C
VOLTAGE NOISE (40nV/DIV)
0
20 60 80 100
Input Bias or Offset Current Output Short-Circuit Current
30
20
10
INPUT BIAS OR OFFSET CURRENT (nA)
0
–75
–25 0 50 100
–50 25 75 125
TEMPERATURE (°C)
40
TIME (SECONDS)
LT1124M/LT1125M
LT1124AM/LT1125AM
ICS
VS = ±15V
1124/25 G02
1124/25 G05
100
√
30
10
3
VS = ±15V
1/f CORNER
2.3Hz
1.0
FREQUENCY (Hz)
1
234
RMS VOLTAGE NOISE DENSITY (nV/ Hz)
1
0.1 10 100 1000
50
40
30
20
10
0
–10
–20
–30
SHORT-CIRCUIT CURRENT (mA)
SINKING SOURCING
–40
–50
0
TIME FROM OUTPUT SHORT TO GND (MINUTES)
VS = ±15V
= 25°C
T
A
MAXIMUM
TYPICAL
1124/25 G03
25°C
–55°C
125°C
125°C
25°C
–55°C
LT1124 G06
Input Bias Current Over the Common Mode Rejection Ratio Power Supply Rejection Ratio
Common Mode Range vs Frequency vs Frequency
20
VS = ±15V
= 25°C
T
A
15
10
5
0
–5
–10
INPUT BIAS CURRENT (nA)
–15
–20
–10 5 15
–15
COMMON MODE INPUT VOLTAGE (V)
DEVICE WITH POSITIVE
INPUT CURRENT
DEVICE WITH NEGATIVE
INPUT CURRENT
–5 10
0
1124/25 G07
160
140
120
100
80
60
40
20
COMMON MODE REJECTION RATIO (dB)
0
1k 100k 1M 10M
10k
FREQUENCY (Hz)
TA = 25°C
V
S
V
CM
= ±15V
= ±10V
1124/25 G08
5
LT1124/LT1125
FREQUENCY (MHz)
0.1
–10
VOLTAEG GAIN (dB)
0
30
40
50
1 10 100
1124/25 G12
10
20
GAIN
Ø
VS = ±15V
T
A
= 25°C
C
L
= 10pF
PHASE SHIFT (DEGREES)
180
120
80
140
160
100
200
SUPPLY VOLTAGE (V)
0
0
SUPPLY CURRENT PER AMPLIFIER (mA)
1
2
3
±5 ±10 ±15 ±20
1124/25 G15
125°C
25°C
–55°C
OUTPUT CURRENT (mA)
–8
OUTPUT VOLTAGE SWING (V)
1.0
–1.6
–1.4
48
1124/25 G18
–6 0–10 –4 –2 2 6 10
0.4
0.6
0.8
1.2
–1.2
–1.0
–0.8
I
SINK
I
SOURCE
V
–
V
+
125°C
–55°C
–55°C
125°C
25°C
VS = ±3V TO ±18V
25°C
UW
LPER
F
O
R
ATYPICA
Voltage Gain vs Frequency Voltage Gain vs Temperature Gain, Phase Shift vs Frequency
180
140
100
60
VOLTAGE GAIN (dB)
20
–20
0.01
1 100 10k 100M
FREQUENCY (Hz)
VS = ±15V
= 25°C
T
A
1M
1124/25 G10
Input Offset Voltage Drift Temperature of Representative
Distribution Units Supply Current vs Supply Voltage
40
VS = ±15V
30
20
PERCENT OF UNITS
10
0
–0.4 0
–0.8
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
N8
200
S8
100
J8
96
396 UNITS TESTED
0.4 0.8
1124/25 G13
CCHARA TERIST
E
C
20
18
16
R = 10k
L
14
µ
12
V = 15V
S
10
V = 10V
OUT
8
6
VOLTAGE GAIN (V/ V)
R = 2k
L
4
2
0
–75
–50 25 75 125
LT1124M/LT1125M
±
±
–25 0 50 100
TEMPERATURE (°C)
Offset Voltage Drift with
50
40
30
20
µ
10
0
–10
–20
OFFSET VOLTAGE ( V)
–30
–40
–50
–25 75 125
–50
ICS
LT1124AM/LT1125AM
LT1124AM/LT1125AM
LT1124M/LT1125M
1124/25 G11
VS = ±15V
0 25 50 100
TEMPERATURE (°C)
1124/25 G14
Small-Signal Transient Response Large-Signal Transient Response Load Current
50mV
0
–50mV
6
= +1
A
VCL
= ±15V or ±5V
V
S
= 15pF
C
L
1124/25 G16
10V
–10V
0
A
VCL
= ±15V
V
S
= –1
Output Voltage Swing vs
1124/25 G17
LT1124/LT1125
TIME AFTER POWER ON (MINUTES)
0
0
CHANGE IN OFFSET VOLTAGE (µV)
2
4
8
10
123 5
1124/25 G21
4
6
VS = ±15V
T
A
= 25°C
SO PACKAGE
N, J PACKAGES
UW
LPER
F
O
R
ATYPICA
Common Mode Limit vs
Temperature Channel Separation vs Frequency Warm-Up Drift
+
V
–0.5
–1.0
–1.5
–2.0
–2.5
2.5
2.0
COMMON MODE LIMIT (V)
1.5
REFERRED TO POWER SUPPLY
1.0
–
0.5
V
–60
–20 20 60 140
V+ = 3V TO 18V
V– = –3V TO –18V
100
TEMPERATURE (°C)
1124/25 G19
Total Harmonic Distortion Total Harmonic Distortion Total Harmonic Distortion
and Noise vs Frequency for and Noise vs Frequency for and Noise vs Frequency for
Noninverting Gain Inverting Gain Competitive Devices
0.1
ZL = 2k/15pF
= 20V
V
P-P
O
AV = +1, +10, +100
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
0.010
AV = +100
AV = +10
0.001
AV = +1
CCHARA TERIST
E
C
180
160
140
120
VS = ±15V
= 2k
R
100
L
= 7V
V
OUT
80
TA = 25°C
60
40
CHANNEL SEPARATION (dB)
20
0
0
100 10k 100k 10M
0.1
ZL = 2k/15pF
= 20Vp-p
V
O
= –1, –10, –100
A
V
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
0.010
0.001
ICS
LIMITED BY
THERMAL INTERACTION
P-P
LIMITED BY PIN
TO PIN CAPACITANCE
1k 1M
FREQUENCY (Hz)
AV = –100
AV = –10
AV = –1
1124/25 G20
0.1
ZL = 2k/15pF
= 20Vp-p
V
O
= –10
A
V
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
0.010
0.001
OP270
OP27
LT1124
TOTAL HARMONIC DISTORTION + NOISE (%)
0.0001
100
20 1k 10k 20k
FREQUENCY (Hz)
1124/25 G22
TOTAL HARMONIC DISTORTION + NOISE (%)
0.0001
100
20 1k 10k 20k
FREQUENCY (Hz)
1124/25 G23
TOTAL HARMONIC DISTORTION + NOISE (%)
0.0001
100
20 1k 10k 20k
FREQUENCY (Hz)
1124/25 G24
Total Harmonic Distortion and Total Harmonic Distortion and Intermodulation Distortion
Noise vs Output Amplitude for Noise vs Output Amplitude for (CCIF Method)* vs Frequency
Noninverting Gain Inverting Gain LT1124 and OP270
1
ZL = 2k/15pF
= 1kHz
f
O
= +1, +10, +100
A
V
MEASUREMENT BANDWIDTH
0.1
= 10Hz TO 22kHz
0.010
0.001
TOTAL HARMONIC DISTORTION + NOISE (%)
0.0001
0.3 10 30
*See LT1115 data sheet for definition of CCIF testing
AV = +100
AV = +10
AV = +1
1
OUTPUT SWING (V
P-P
)
1124/25 G25
1
ZL = 2k/15pF
= 1kHz
f
O
= –1, –10, –100
A
V
MEASUREMENT BANDWIDTH
0.1
= 10Hz TO 22kHz
0.010
0.001
TOTAL HARMONIC DISTORTION + NOISE (%)
0.0001
0.3 10 30
AV = –100
AV = –10
AV = –1
1
OUTPUT SWING (Vp-p)
1124/25 G26
0.010
ZL = 2k/15pF
f (IM) = 1kHz
= 13.5kHz
f
O
= 20Vp-p
V
O
= –10
A
V
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
0.001
INTERMODULATION DISTORTION (IMD)(%)
0.0001
3k 10k 20k
FREQUENCY (Hz)
OP270
LT1124
1124/25 G27
7
LT1124/LT1125
PPLICATI
A
U
O
S
I FOR ATIO
WU
U
The LT1124 may be inserted directly into OP-270 sockets.
The LT1125 plugs into OP-470 sockets. Of course, all
standard dual and quad bipolar op amps can also be
replaced by these devices.
Matching Specifications
In many applications the performance of a system depends on the matching between two op amps, rather than
the individual characteristics of the two devices. The three
op amp instrumentation amplifier configuration shown in
this data sheet is an example. Matching characteristics are
not 100% tested on the LT1124/LT1125.
Some specifications are guaranteed by definition. For
example, 70µV maximum offset voltage implies that mis-
match cannot be more than 140µV. 112dB (= 2.5µV/V)
CMRR means that worst case CMRR match is 106dB
(5µV/V). However, Table 1 can be used to estimate the
expected matching performance between the two sides of
the LT1124, and between amplifiers A and D, and between
amplifiers B and C of the LT1125.
Offset Voltage and Drift
Thermocouple effects, caused by temperature gradients
across dissimilar metals at the contacts to the input
terminals, can exceed the inherent drift of the amplifier
unless proper care is exercised. Air currents should be
minimized, package leads should be short, the two input
leads should be close together and maintained at the same
temperature.
The circuit shown in Figure 1 to measure offset voltage is
also used as the burn-in configuration for the LT1124/
LT1125, with the supply voltages increased to ±16V.
50k*
15V
–
100Ω*
+
50k*
V
= 1000V
OUT
*RESISTORS MUST HAVE LOW
THERMOELECTRIC POTENTIAL
Figure 1. Test Circuit for Offset Voltage
and Offset Voltage Drift with Temperature
Table 1. Expected Match
LT1124AC/AM LT1124C/M
LT1125AC/AM LT1125C/M
PARAMETER 50% YIELD 98% YIELD 50% YIELD 98% YIELD UNITS
VOS Match, ∆VOS LT1124 20 110 30 130 µV
LT1125 30 150 50 180 µV
Temperature Coefficient Match 0.35 1.0 0.5 1.5 µV/°C
Average Noninverting I
Match of Noninverting I
CMRR Match 126 115 123 112 dB
PSRR Match 127 118 127 114 dB
B
B
618725 nA
722830 nA
–15V
OS
V
OUT
1124/25 F01
8
LT1124/LT1125
1124/25 F04
+
–
A
+
–
B
+
–
C
+
–
D
OUT
PPLICATI
A
U
O
S
I FOR ATIO
WU
U
High Speed Operation
When the feedback around the op amp is resistive (RF),
a pole will be created with RF, the source resistance and
capacitance (RS, CS), and the amplifier input capacitance
(CIN ≈ 2pF). In low closed loop gain configurations and
with RS and RF in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capacitor
(CF) in parallel with RF eliminates this problem (see
Figure 2). With RS (CS + CIN) = RFCF, the effect of the
feedback pole is completely removed.
C
F
R
F
–
C
R
C
S
S
Figure 2. High Speed Operation
IN
+
OUTPUT
1124/25 F02
During the fast feedthrough-like portion of the output, the
input protection diodes effectively short the output to the
input and a current, limited only by the output short circuit
protection, will be drawn by the signal generator. With R
F
≥500Ω, the output is capable of handling the current
requirements (IL ≤ 20mA at 10V) and the amplifier stays
in its active mode and a smooth transition will occur.
Noise Testing
Each individual amplifier is tested to 4.2nV/√Hz voltage
noise; i.e., for the LT1124 two tests, for the LT1125 four
tests are performed. Noise testing for competing multiple
op amps, if done at all, may be sample tested or tested
using the circuit shown in Figure 4.
e
n OUT
= √(e
)2 + (enB)2 + (enC)2 + (enD)
nA
2
If the LT1125 were tested this way, the noise limit would
be √ 4 • (4.2nV/√Hz)2 = 8.4nV/√Hz. But is this an effective
screen? What if three of the four amplifiers are at a typical
2.7nV/√Hz, and the fourth one was contaminated and has
6.9nV/√Hz noise?
RMS Sum = √(2.7)
2
+ (2.7)2 + (2.7)2 + (6.9)2 = 8.33nV/√Hz
Unity Gain Buffer Applications
When RF ≤ 100Ω and the input is driven with a fast, large
signal pulse (>1V), the output waveform will look as
shown in Figure 3.
R
F
–
+
Figure 3. Unity-Gain Buffer Applications
OUTPUT
4.5V/µs
1124/25 F03
This passes an 8.4nV/√Hz spec, yet one of the amplifiers
is 64% over the LT1125 spec limit. Clearly, for proper
noise measurement, the op amps have to be tested
individually.
Figure 4. Competing Quad Op Amp Noise Test Method
9
LT1124/LT1125
FREQUENCY (Hz)
GAIN ERROR (PERCENT)
0.01
0.1
1.0
0.1 10 100
1124/25 TA04
0.001
1
GAIN ERROR =
CLOSED-LOOP GAIN
OPEN-LOOP GAIN
TYPICAL
PRECISION
OP AMP
LT1124/LT1125
WU
W
U
PERFOR A CE CO PARISO
Table 2 summarizes the performance of the LT1124/
LT1125 compared to the low cost grades of alternate
approaches.
The comparison shows how the specs of the LT1124/
LT1125 not only stand up to the industry standard OP-27,
Table 2. Guaranteed Performance, VS = ±15V, TA = 25°C, Low Cost Devices
LT1124CN8
PARAMETER/UNITS LT1125CN OP-27 GP OP-270 GP OP-470 GP UNITS
Voltage Noise, 1kHz 4.2 4.5 – 5.0 nV/√Hz
100% Tested Sample Tested No Limit Sample Tested
Slew Rate 2.7 1.7 1.7 1.4 V/µs
100% Tested Not Tested
Gain Bandwidth Product 8.0 5.0 – – MHz
100% Tested Not Tested No Limit No Limit
Offset Voltage LT1124 100 100 250 – µV
LT1125 140 – – 1000 µV
Offset Current LT1124 20 75 20 – nA
LT1125 30 – – 30 nA
Bias Current 30 80 60 60 nA
Supply Current/Amp 2.75 5.67 3.25 2.75 mA
Voltage Gain, RL = 2k 1.5 0.7 0.35 0.4 V/µV
Common Mode Rejection Ratio 106 100 90 100 dB
Power Supply Rejection Ratio 110 94 104 105 dB
SO-8 Package Yes - LT1124 Yes No –
but in most cases are superior. Normally dual and quad
performance is degraded when compared to singles, for
the LT1124/LT1125 this is not the case.
PPLICATITYPICAL
Gain 1000 Amplifier with 0.01% Accuracy, DC to 1Hz Gain Error vs Frequency Closed-Loop Gain = 1000
365Ω
1%
THE HIGH GAIN AND WIDE BANDWIDTH OF THE LT1124/LT1125, IS USEFUL IN LOW
FREQUENCY HIGH CLOSED-LOOP GAIN AMPLIFIER APPLICATIONS. A TYPICAL
PRECISION OP AMP MAY HAVE AN OPEN-LOOP GAIN OF ONE MILLION WITH 500kHz
BANDWIDTH. AS THE GAIN ERROR PLOT SHOWS, THIS DEVICE IS CAPABLE OF 0.1%
AMPLIFYING ACCURACY UP TO 0.3Hz ONLY. EVEN INSTRUMENTATION RANGE
SIGNALS CAN VARY AT A FASTER RATE. THE LT1124/LT1125 “GAIN PRECISION —
BANDWIDTH PRODUCT” IS 75 TIMES HIGHER, AS SHOWN.
10
INPUT
340k
1%
2
–
1/2 LT1124
3
+
U
O
SA
20k
15k
TRIM
5%
15V
6 (S0-8)
8 (N8)
7 (SO-8)
1 (N8)
4
RN60C FILM RESISTORS
–15V
OUTPUT
1124/25 TA03
LT1124/LT1125
E
S
CH
NONINVERTING
INPUT (+)
INVERTING
INPUT (–)
Q10
W
A
TI
ICDAGRA
Q13Q9 Q8
–
V
W
Q7
21k 21k
Q1BQ1A
(1/2 LT1124, 1/4 LT1125)
Q18
67pF
570µA
35pF
900Ω
400Ω
20pF
+
V
Q23
360µA
200pF
Q17
Q2A
Q2B
Q11
200µA 100µA 200Ω 6k 200Ω 6k 50Ω
3.6k 3.6k
Q19 Q20
+
V
Q22
Q12Q3Q15 Q16
Q24
Q25
200µA
Q26
100µA
Q27
Q30
Q28
20Ω
OUTPUT
20Ω
Q29
+
V
–
V
1124/25 SS
11
LT1124/LT1125
PACKAGEDESCRIPTI
U
O
Dimensions in inches (millimeters) unless otherwise noted.
J8 Package
8-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
CORNER LEADS OPTION
(4 PLCS)
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
0.300 BSC
(0.762 BSC)
0.008 – 0.018
(0.203 – 0.457)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
0° – 15°
OPTION
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.005
(0.127)
MIN
0.025
(0.635)
RAD TYP
0.045 – 0.068
(1.143 – 1.727)
0.014 – 0.026
(0.360 – 0.660)
N8 Package
0.405
(10.287)
MAX
87
12
65
3
4
0.220 – 0.310
(5.588 – 7.874)
0.015 – 0.060
(0.381 – 1.524)
0.100 ± 0.010
(2.540 ± 0.254)
0.200
(5.080)
MAX
0.125
3.175
MIN
J8 1197
12
876
0.255 ± 0.015*
(6.477 ± 0.381)
12
0.300 – 0.325
(7.620 – 8.255)
0.065
(1.651)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
–0.015
+0.889
8.255
()
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.100 ± 0.010
(2.540 ± 0.254)
0.400*
(10.160)
MAX
3
5
4
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.020
(0.508)
MIN
N8 1197
PACKAGEDESCRIPTI
U
O
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
8
0.189 – 0.197*
(4.801 – 5.004)
7
6
LT1124/LT1125
5
0.228 – 0.244
(5.791 – 6.197)
0.010 – 0.020
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
× 45°
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
0.150 – 0.157**
(3.810 – 3.988)
1
3
2
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
SO8 0996
13
LT1124/LT1125
PACKAGEDESCRIPTI
U
O
Dimensions in inches (millimeters) unless otherwise noted.
J Package
14-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
0.785
12
(19.939)
MAX
0.005
(0.127)
MIN
14
11 891013
0.025
(0.635)
RAD TYP
0.300 BSC
(0.762 BSC)
0.008 – 0.018
(0.203 – 0.457)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
0° – 15°
1
0.045 – 0.068
(1.143 – 1.727)
14-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
234
N Package
14
56
0.014 – 0.026
(0.360 – 0.660)
1213
0.770*
(19.558)
MAX
11
0.220 – 0.310
(5.588 – 7.874)
7
0.015 – 0.060
(0.381 – 1.524)
0.100 ± 0.010
(2.540 ± 0.254)
0.200
(5.080)
MAX
0.125
(3.175)
MIN
J14 1197
8910
14
0.255 ± 0.015*
(6.477 ± 0.381)
2
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
–0.015
+0.889
8.255
()
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.020
(0.508)
MIN
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.005
(0.125)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
31
4
0.045 – 0.065
(1.143 – 1.651)
6
7
0.065
(1.651)
TYP
0.018 ± 0.003
(0.457 ± 0.076)
N14 1197
5
PACKAGEDESCRIPTI
U
O
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
16-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
16
0.398 – 0.413*
(10.109 – 10.490)
15 14
121110 9
13
LT1124/LT1125
NOTE 1
2345
0.050
(1.270)
TYP
1
0.014 – 0.019
(0.356 – 0.482)
TYP
0.291 – 0.299**
(7.391 – 7.595)
0.010 – 0.029
(0.254 – 0.737)
0.009 – 0.013
(0.229 – 0.330)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
*
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
**
NOTE 1
× 45°
0.016 – 0.050
(0.406 – 1.270)
° – 8° TYP
0
0.093 – 0.104
(2.362 – 2.642)
6
78
0.037 – 0.045
(0.940 – 1.143)
0.394 – 0.419
(10.007 – 10.643)
0.004 – 0.012
(0.102 – 0.305)
S16 (WIDE) 0396
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT1124/LT1125
TYPICAL APPLICATION
15V
U
Strain Gauge Signal Conditioner with Bridge Excitation
LT1009
5k
3
+
2.5V
1/4
LT1125
2
–
–15V
350Ω
BRIDGE
15V
13
–
1/4
LT1125
12
+
–15V
14
1k
THE LT1124/LT1125 IS CAPABLE OF PROVIDING EXCITATION CURRENT DIRECTLY
1
TO BIAS THE 350Ω BRIDGE AT 5V WITH ONLY 5V ACROSS THE BRIDGE (AS OPPOSED
TO THE USUAL 10V) TOTAL POWER DISSIPATION AND BRIDGE WARM-UP DRIFT IS
REDUCED. THE BRIDGE OUTPUT SIGNAL IS HALVED, BUT THE LT1124/LT1125 CAN
AMPLIFY THE REDUCED SIGNAL ACCURATELY.
REFERENCE
OUTPUT
15V
5
301k*
1k
*RN60C FILM RESISTORS
10k
ZERO
TRIM
6
+
LT1125
–
1/4
–15V
4
13
GAIN
TRIM
7
50k
0V TO 10V
OUTPUT
1µF 301k*
499Ω*
1124/25 TA05
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1007 Single Low Noise, Precision Op Amp 2.5nV/√Hz 1kHz Voltage Noise
LT1028/LT1128 Single Low Noise, Precision Op Amps 0.85nV/√Hz Voltage Noise
LT1112/LT1114 Dual/Quad Precision Picoamp Input 250pA Max I
LT1113 Dual Low Noise JFET Op Amp 4.5nV/√Hz Voltage Noise, 10fA/√Hz Current Noise
LT1126/LT1127 Decompensated LT1124/LT1125 11V/µs Slew Rate
LT1169 Dual Low Noise JFET Op Amp 6nV/√Hz Voltage Noise, 1fA/√Hz Current Noise, 10pA Max I
LT1792 Single LT1113 4.2nV/√Hz Voltage Noise, 10fA/√Hz Current Noise
LT1793 Single LT1169 6nV/√Hz Voltage Noise, 1fA/√Hz Current Noise, 10pA Max I
Linear Technology Corporation
16
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
B
11245fas, sn11245 LT/TP 0699 REV A 2K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1992
B
B
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