Datasheet LT1113 Datasheet (Linear Technology)

FEATURES

LT1113

Dual Low Noise,

Precision, JFET Input Op Amps

U

DESCRIPTIO

■

100% Tested Low Voltage Noise: 6nV/√Hz Max

■

SO-8 Package Standard Pinout

■

Voltage Gain: 1.2 Million Min

■

Offset Voltage: 1.5mV Max

■

Offset Voltage Drift: 15µV/°C Max

■

Input Bias Current, Warmed Up: 450pA Max

■

Gain Bandwidth Product: 5.6MHz Typ

■

Guaranteed Specifications with ±5V Supplies

■

Guaranteed Matching Specifications

U

APPLICATIO S

■

Photocurrent Amplifiers

■

Hydrophone Amplifiers

■

High Sensitivity Piezoelectric Accelerometers

■

Low Voltage and Current Noise Instrumentation
Amplifier Front Ends

■

Two and Three Op Amp Instrumentation Amplifiers

■

Active Filters

The LT®1113 achieves a new standard of excellence in noise
performance for a dual JFET op amp. The 4.5nV/√Hz 1kHz
noise combined with low current noise and picoampere
bias currents makes the LT1113 an ideal choice for ampli­fying low level signals from high impedance capacitive
transducers.

The LT1113 is unconditionally stable for gains of 1 or more,
even with load capacitances up to 1000pF. Other key fea­tures are 0.4mV VOS and a voltage gain of 4 million. Each
individual amplifier is 100% tested for voltage noise, slew
rate and gain bandwidth.

The design of the LT1113 has been optimized to achieve
true precision performance with an industry standard
pinout in the S0-8 package. A set of specifications are
provided for ±5V supplies and a full set of matching speci­fications are provided to facilitate the use of the LT1113 in
matching dependent applications such as instrumenta­tion amplifier front ends.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

Low Noise Hydrophone Amplifier with DC Servo

2

3

–5V TO –15V

R8
100M

R7
1M

< 70°C

A

5V TO 15V

–

1/2

LT1113

+

R6

100k

8

1

4

7

R3

R1*

3.9k

100M

C1*

R2
200Ω

C

HYDRO-

PHONE

DC OUTPUT ≤ 2.5mV FOR T
OUTPUT VOLTAGE NOISE = 128nV/√Hz AT 1kHz (GAIN = 20)

≈ 100pF TO 5000pF; R4C2 > R8CT; *OPTIONAL

C1 ≈ C

T

T

U

C2

0.47µF

1/2

LT1113

1kHz Input Noise Voltage Distribution

5.0

VS = ±15V
T

A

5.2

5.4

= 25°C

5.6

1113 TA02

40

OUTPUT

R4
1M

–

6

R5
1M

5

+

1113 TA01

30

20

PERCENT OF UNITS (%)

10

0

4.0 4.4

3.8

4.2

INPUT VOLTAGE NOISE (nV/√Hz)

138 S8
276 OP AMPS TESTED

4.8 5.8

4.6

1

LT1113

1

2

3

4

8

7

6

5

TOP VIEW

S8 PACKAGE

8-LEAD PLASTIC SO

B

A

OUT A

–IN A
+IN A

V

–

V

+

OUT B
–IN B
+IN B

A

W

O

LUTEXI TIS

S

A

WUW

U

(Note 1)

ARB

G

Supply Voltage

–55°C to 105°C ............................................... ±20V

105°C to 125°C ............................................... ±16V

Differential Input Voltage ...................................... ±40V

Input Voltage (Equal to Supply Voltage)............... ±20V

Output Short Circuit Duration .......................... 1 Minute

Storage Temperature Range................ –65°C to 150°C

WU

/

PACKAGE

OUT A

–IN A
+IN A

–

V

J8 PACKAGE

8-LEAD CERDIP

T

JMAX

T

JMAX

O

RDER I FOR ATIO

TOP VIEW

1
2

A

3
4

N8 PACKAGE
8-LEAD PDIP

= 160°C, θJA = 100°C/W (J8)
= 150°C, θJA = 130°C/W (N8)

V

8

OUT B

7

–IN B

6

B

+IN B

5

ORDER PART

+

NUMBER

LT1113AMJ8
LT1113MJ8
LT1113ACN8
LT1113CN8

Operating Temperature Range

LT1113AC/LT1113C (Note 2) .......... –40°C to 85°C

LT1113AM/LT1113M .................... –55°C to 125°C

Specified Temperature Range

LT1113AC/LT1113C (Note 3) .......... –40°C to 85°C

LT1113AM/LT1113M .................... –55°C to 125°C

Lead Temperature (Soldering, 10 sec) ................ 300°C

U

ORDER PART

NUMBER

LT1113CS8

S8 PART MARKING

T

= 150°C, θJA = 190°C/W

JMAX

1113

Consult factory for Industrial grade parts.

LECTRICAL C CHARA TERIST

E

SYMBOL PARAMETER CONDITIONS (Note 4) MIN TYP MAX MIN TYP MAX UNITS

V

OS

I

OS

I

B

e

n

i

n

R

IN

C

IN

V

CM

CMRR Common Mode Rejection Ratio V
PSRR Power Supply Rejection Ratio VS = ±4.5V to ± 20V 86 100 83 98 dB
A

VOL

2

Input Offset Voltage 0.40 1.5 0.50 1.8 mV

= ±5V 0.45 1.7 0.55 2.0 mV

V

S

Input Offset Current Warmed Up (Note 5) 30 100 35 150 pA
Input Bias Current Warmed Up (Note 5) 300 450 320 480 pA
Input Noise Voltage 0.1Hz to 10Hz 2.4 2.4 µV
Input Noise Voltage Density fO = 10Hz 17 17 nV/√Hz

= 1000Hz 4.5 6.0 4.5 6.0 nV/√Hz

f

O

Input Noise Current Density fO = 10Hz, fO = 1000Hz (Note 6) 10 10 fA/√Hz
Input Resistance

Differential Mode 10
Common Mode V

Input Capacitance 14 14 pF

Input Voltage Range (Note 7) 13.0 13.5 13.0 13.5 V

Large-Signal Voltage Gain VO = ±12V, RL = 10k 1200 4800 1000 4500 V/mV

= –10V to 8V 10

CM

V

= 8V to 11V 10

CM

= ±5V 27 27 pF

V

S

= –10V to 13V 85 98 82 95 dB

CM

VO = ±10V, RL = 1k 600 4000 500 3000 V/mV

VS = ±15V, VCM = 0V, TA = 25°C, unless otherwise noted.

ICS

LT1113AM/AC LT1113M/C

11
11
10

–10.5 –11.0 –10.5 –11.0 V

10
10
10

11
11
10

P-P

Ω
Ω
Ω

LT1113

LECTRICAL C CHARA TERIST

E

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

V

OUT

SR Slew Rate RL ≥ 2k (Note 9) 2.3 3.9 2.3 3.9 V/µs
GBW Gain Bandwidth Product fO = 100kHz 4.0 5.6 4.0 5.6 MHz
t

S

I

S

∆V
∆I
∆CMRR Common Mode Rejection Match (Note 11) 81 94 78 94 dB
∆PSRR Power Supply Rejection Match (Note 11) 82 95 80 95 dB

Output Voltage Swing RL = 10k ±13.5 ±13.8 ±13.0 ±13.8 V

= 1k ±12.0 ±13.0 ±11.5 ±13.0 V

R

L

Settling Time 0.01%, AV = +1, RL = 1k, 4.2 4.2 µs

≤ 1000pF, 10V Step

C

L

Channel Separation fO = 10Hz, VO = ±10V, RL = 1k 130 126 dB
Supply Current per Amplifier 5.3 6.25 5.3 6.50 mA

V

= ±5V 5.3 6.20 5.3 6.45 mA

S

Offset Voltage Match 0.8 2.5 0.8 3.3 mV

OS

+

Noninverting Bias Current Match Warmed Up (Note 5) 10 80 10 120 pA

B

ICS

VS = ±15V, VCM = 0V, TA = 25°C, unless otherwise noted.

LT1113AM/AC LT1113M/C

The ● denotes specifications which apply over the temperature range 0°C ≤ TA ≤ 70°C. VS = ±15V, VCM = 0V,
unless otherwise noted. (Note 12)

LT1113AC LT1113C

SYMBOL PARAMETER CONDITIONS (Note 4) MIN TYP MAX MIN TYP MAX UNITS

V

OS

∆V
∆Temp

I

OS

I

B

V

CM

CMRR Common Mode Rejection Ratio V
PSRR Power Supply Rejection Ratio VS = ±4.5V to ±20V ● 83 99 81 97 dB
A

VOL

V

OUT

SR Slew Rate RL ≥ 2k (Note 9) ● 2.1 3.7 1.7 3.7 V/µs
GBW Gain Bandwidth Product fO = 100kHz ● 3.2 4.5 3.2 4.5 MHz
I

S

∆V
∆I
∆CMRR Common Mode Rejection Match (Note 11) ● 76 93 74 93 dB
∆PSRR Power Supply Rejection Match (Note 11) ● 79 93 77 93 dB

Input Offset Voltage ● 0.6 2.1 0.7 2.5 mV

= ±5V ● 0.7 2.3 0.8 2.7 mV

V

S

Average Input Offset (Note 8) ● 715 820 µV/°C

OS

Voltage Drift
Input Offset Current ● 50 350 55 450 pA
Input Bias Current ● 600 1200 700 1600 pA

Input Voltage Range ● 12.9 13.4 12.9 13.4 V

= –10V to 12.9V ● 81 97 79 94 dB

CM

Large-Signal Voltage Gain VO = ±12V, RL = 10k ● 900 3600 800 3400 V/mV

= ±10V, RL = 1k ● 500 2600 400 2400 V/mV

V

O

Output Voltage Swing RL = 10k ● ±13.2 ±13.5 ±12.7 ±13.5 V

R

= 1k ● ±11.7 ±12.7 ±11.3 ±12.7 V

L

Supply Current per Amplifier ● 5.3 6.35 5.3 6.55 mA

V

= ±5V ● 5.3 6.30 5.3 6.50 mA

S

Offset Voltage Match ● 0.9 3.5 0.9 4.5 mV

OS

+

Noninverting Bias Current Match ● 30 300 35 400 pA

B

● –10.0 –10.8 –10.0 –10.8 V

3

LT1113

LECTRICAL C CHARA TERIST

E

The ● denotes specifications which apply over the temperature range –40°C ≤ TA ≤ 85°C. VS = ±15V, VCM = 0V,
unless otherwise noted. (Note 10)

SYMBOL PARAMETER CONDITIONS (Note 4) MIN TYP MAX MIN TYP MAX UNITS

V

OS

∆V
∆Temp

I

OS

I

B

V

CM

CMRR Common Mode Rejection Ratio V
PSRR Power Supply Rejection Ratio VS = ±4.5V to ±20V ● 81 98 79 96 dB
A

VOL

V

OUT

SR Slew Rate RL ≥ 2k ● 2.0 3.5 1.6 3.5 V/µs
GBW Gain Bandwidth Product fO = 100kHz ● 2.9 4.3 2.9 4.3 MHz
I

S

∆V
∆I
∆CMRR Common Mode Rejection Match (Note 11) ● 76 93 73 93 dB
∆PSRR Power Supply Rejection Match (Note 11) ● 77 92 75 92 dB

Input Offset Voltage ● 0.7 2.4 0.8 2.8 mV

= ±5V ● 0.8 2.6 0.9 3.0 mV

V

S

Average Input Offset ● 715 820 µV/°C

OS

Voltage Drift
Input Offset Current ● 80 700 90 1000 pA
Input Bias Current ● 1750 3000 1800 5000 pA

Input Voltage Range ● 12.6 13.0 12.6 13.0 V

CM

Large-Signal Voltage Gain VO = ±12V, RL = 10k ● 850 3300 750 3000 V/mV

= ±10V, RL = 1k ● 400 2200 300 2000 V/mV

V

O

Output Voltage Swing RL = 10k ● ±13.0 ±12.5 ±12.5 ±12.5 V

= 1k ● ±11.5 ±12.0 ±11.0 ±12.0 V

R

L

Supply Current per Amplifier ● 5.30 6.35 5.30 6.55 mA

V

= ±5V ● 5.25 6.30 5.25 6.50 mA

S

Offset Voltage Match ● 1.0 4.4 1.0 5.1 mV

OS

+

Noninverting Bias Current Match ● 50 600 55 900 pA

B

ICS

LT1113AC LT1113C

● –10.0 –10.5 –10.0 –10.5 V

= –10V to 12.6V ● 80 96 78 93 dB

The ● denotes specifications which apply over the temperature range –55°C ≤ TA ≤ 125°C. VS = ±15V, VCM = 0V,
unless otherwise noted. (Note 12)

LT1113AM LT1113M

SYMBOL PARAMETER CONDITIONS (Note 4) MIN TYP MAX MIN TYP MAX UNITS

V

OS

∆V
∆Temp

I

OS

I

B

V

CM

CMRR Common Mode Rejection Ratio V
PSRR Power Supply Rejection Ratio VS = ±4.5V to ±20V ● 80 97 78 95 dB

Input Offset Voltage ● 0.8 2.7 0.9 3.3 mV

= ±5V ● 0.8 2.8 0.9 3.4 mV

V

S

Average Input Offset (Note 8) ● 512 815 µV/°C

OS

Voltage Drift
Input Offset Current ● 0.8 15 1.0 25 nA
Input Bias Current ● 25 50 27 70 nA

Input Voltage Range ● 12.6 13.0 12.6 13.0 V

= –10V to 12.6V ● 79 95 77 92 dB

CM

● –10.0 –10.4 –10.0 –10.4 V

4

LT1113

LECTRICAL C CHARA TERIST

E

The ● denotes specifications which apply over the temperature range –55°C ≤ TA ≤ 125°C. VS = ±15V, VCM = 0V,
unless otherwise noted. (Note 12)

SYMBOL PARAMETER CONDITIONS (Note 4) MIN TYP MAX MIN TYP MAX UNITS

A

VOL

V

OUT

SR Slew Rate RL ≥ 2k (Note 9) ● 1.9 3.3 1.6 3.3 V/µs
GBW Gain Bandwidth Product fO = 100kHz ● 2.2 3.4 2.2 3.4 MHz
I

S

∆V
∆I
∆CMRR Common Mode Rejection Match (Note 11) ● 75 92 73 92 dB
∆PSRR Power Supply Rejection Match (Note 11) ● 76 91 74 91 dB

Large-Signal Voltage Gain VO = ±12V, RL = 10k ● 800 2700 700 2500 V/mV

= ±10V, RL = 1k ● 400 1500 300 1000 V/mV

V

O

Output Voltage Swing RL = 10k ● ±13.0 ±12.5 ±12.5 ±12.5 V

= 1k ● ±11.5 ±12.0 ±11.0 ±12.0 V

R

L

Supply Current Per Amplifier ● 5.30 6.35 5.30 6.55 mA

= ±5V ● 5.25 6.30 5.25 6.50 mA

V

S

Offset Voltage Match ● 1.0 5.0 1.0 5.5 mV

OS

+

Noninverting Bias Current Match ● 1.8 12 2.0 20 nA

B

ICS

LT1113AM LT1113M

Note 1: Absolute Maximum Ratings are those values beyond which the

life of the device may be impaired.
Note 2: The LT1113C is guaranteed functional over the Operating

Temperature Range of –40°C to 85°C. The LT1113M is guaranteed
functional over the Operating Temperature Range of –55°C to 125°C.

Note 3: The LT1113C is guaranteed to meet specified performance from
0°C to 70°C. The LT1113C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. For guaranteed I grade parts, consult the
factory. The LT1113M is guaranteed to meet specified performance from
–55°C to 125°C.

Note 4: Typical parameters are defined as the 60% yield of parameter
distributions of individual amplifiers, i.e., out of 100 LT1113s (200 op
amps) typically 120 op amps will be better than the indicated
specification.

Note 5: Warmed-up I
temperature of 50°C from 25°C measurements and 50°C characterization
data.

Note 6: Current noise is calculated from the formula:

i

= (2qIB)

n

where q = 1.6 • 10
swamps the contribution of current noise.

and IOS readings are extrapolated to a chip

B

1/2

–19

coulomb. The noise of source resistors up to 200M

Note 7: Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 2.3mV
(A grade) to 2.8mV (C grade).

Note 8: This parameter is not 100% tested.
Note 9: Slew rate is measured in A

measured at ±2.5V.
Note 10: The LT1113 is designed, characterized and expected to meet

these extended temperature limits, but is not tested at –40°C and 85°C.
Guaranteed I grade parts are available. Consult factory.

Note 11: ∆CMRR and ∆PSRR are defined as follows:

(1) CMRR and PSRR are measured in µV/V on the individual

amplifiers.

(2) The difference is calculated between the matching sides in µV/V.
(3) The result is converted to dB.

Note 12: The LT1113 is measured in an automated tester in less than
one second after application of power. Depending on the package used,
power dissipation, heat sinking, and air flow conditions, the fully
warmed-up chip temperature can be 10°C to 50°C higher than the
ambient temperature.

= –1; input signal is ±7.5V, output

V

5

LT1113

0.1Hz to 10Hz Voltage Noise

LPER

UW

R

F

O

ATYPICA

CCHARA TERIST

E

C

1kHz Output Voltage Noise
Density vs Source Resistance

10k

+

1k

R

SOURCE

–

ICS

Voltage Noise vs Frequency

100

V

N

TA = 25°C

= ±15V

V

S

VOLTAGE NOISE (1µV/DIV)

2

0

Voltage Noise vs
Chip Temperature

10

VS = ±15V

9
8
7
6
5
4
3
2

VOLTAGE NOISE (AT1kHz)(nV/√Hz)

1
0

–75

–50 25

4

TIME (SEC)

0

–25

TEMPERATURE (°C)

100

10

V

N

SOURCE
RESISTANCE

TOTAL 1kHz VOLTAGE NOISE DENSITY (nV/√Hz)

6

8

10

1113 G01

1

100 10k 100k 1M1k

ONLY

SOURCE RESISTANCE (Ω)

TA = 25°C
V

10M

= ±15V

S

100M

1G

1113 G02

Input Bias and Offset Currents vs
Chip Temperature

100n

VS = ±15V

30n
10n

3n

1n
300p
100p

30p
10p

3p

INPUT BIAS AND OFFSET CURRENTS (A)

125

50

100

75

1113 G04

1p

IB, VCM = 10V

–75

–50 25

IB, VCM = 0V

IOS, VCM = 10V

0

–25

TEMPERATURE (°C)

IOS, VCM = 0V

50

75

100

125

1113 G04

10

1/f CORNER

120Hz

RMS VOLTAGE NOISE DENSITY (nV/√Hz)

1

1

10 1k

100 10k

FREQUENCY (Hz)

Input Bias and Offset Currents
Over the Common-Mode Range

400

TA = 25°C

= ±15V

V

S

NOT WARMED UP

300

200

BIAS CURRENT

100

INPUT BIAS AND OFFSET CURRENTS (pA)

0

–15

OFFSET CURRENT

–10 –5 0 5

COMMON-MODE RANGE (V)

TYPICAL

1113 G03

10 15

1113 G06

Common-Mode Limit vs
Temperature

V+ –0

–0.5
–1.0
–1.5
–2.0

4.0

3.5

COMMON-MODE LIMIT (V)

3.0

REFERRED TO POWER SUPPLY

2.5

–

V

+2.0

–60

–20

6

V+ = 5V TO 20V

V– = –5V TO –20V

60

20

TEMPERATURE (°C)

100

1113 G07

Common-Mode Rejection Ratio
vs Frequency

120

100

80

60

40

20

COMMON-MODE REJECTION RATIO (dB)

0

140

1k 100k 1M 10M

10k

FREQUENCY (Hz)

TA = 25°C
V

= ±15V

S

1113 G08

Power Supply Rejection Ratio
vs Frequency

120

100

80

60

40

20

POWER SUPPLY REJECTION RATIO (dB)

0

10

–PSRR

100

1k 10k 100k

FREQUENCY (Hz)

+PSRR

TA = 25°C

1M 10M

1113 G09

LPER

TEMPERATURE (°C)

–75

6

5

4

3

2

1

0

–25

50

75

1113 G18

–50 25

100

125

0

SLEW RATE (V/µs)

SLEW RATE

GBW

12

10

8

6

4

2

0

GAIN-BANDWIDTH PRODUCT (f

O

= 100kHz)(MHz)

LT1113

UW

R

F

O

ATYPICA

CCHARA TERIST

E

C

ICS

Voltage Gain vs Frequency

180

140

100

60

VOLTAGE GAIN (dB)

20

–20

0.01

1

100

FREQUENCY (Hz)

10k

Small-Signal Transient Response

20mV/DIV

TA = 25°C

= ±15V

V

S

1M

100M

1113 G10

Voltage Gain vs
Chip Temperature

10

9
8
7
6
5
4
3

VOLTAGE GAIN (V/µV)

2
1
0

–75

–50 25

–25

CHIP TEMPERATURE (°C)

RL = 1k

0

VS = ±15V

= ±10V, RL = 1k

V

O

= ±12V, RL = 10k

V

O

RL =10k

50

Large-Signal Transient Response

5V/DIV

Gain and Phase Shift vs
Frequency

50

TA = 25°C

= ±15V

V

40

30

20

10

VOLTAGE GAIN (dB)

0

–10

125

100

75

1113 G11

0.1

GAIN

1 10 100

FREQUENCY (MHz)

S

= 10pF

C

L

PHASE

60

80

PHASE SHIFT (DEG)

100

120

140

160

180

1113 G12

Supply Current vs Supply Voltage

6

25°C

5

–55°C

125°C

A

= 1

V

= 10pF

C

L

= ±15V, ± 5V

V

S

1µs/DIV

1113 G13

A

V

C

L

V

S

= 1
= 10pF
= ±15V

Output Voltage Swing vs
Load Current Capacitive Load Handling

V+ –0.8

–1.0
–1.2
–1.4
–1.6

1.4

1.2

1.0

0.8

OUTPUT VOLTAGE SWING (V)

0.6

–

V

+0.4

–8

–10

I

SINK

25°C

–55°C

VS = ±5V TO ±20V

125°C

048

–2

–6 –4

OUTPUT CURRENT (mA)

–55°C

25°C

125°C

2

6

10

I

SOURCE

1113 G16

50

VS = ±15V
T

= 25°C

A

40

≥ 10k

R

L

= 100mV

V

O

AV = +10, RF = 10k, CF = 20pF

30

20

OVERSHOOT (%)

10

0

0.1

2µs/DIV

P-P

A

= 1

V

A

= 10

V

1

10

CAPACITIVE LOAD (pF)

100

1000

1113 G14

10000

1113 G17

SUPPLY CURRENT PER AMPLIFIER (mA)

4

0

±5

±10

SUPPLY VOLTAGE (V)

Slew Rate and Gain-Bandwidth
Product vs Temperature

±15

±20

1113 G15

7

LT1113

LPER

UW

R

F

O

ATYPICA

CCHARA TERIST

E

C

ICS

Distribution of Offset Voltage Drift
with Temperature (J8)

40

30

20

PERCENT OF UNITS

10

0

–10 –8 –2

–12

OFFSET VOLTAGE DRIFT WITH TEMPERATURE (µV/°C)

–4

VS = ±15V

75 J8

150 OP AMPS

0

2–6

4

THD and Noise vs Frequency for
Noninverting Gain

1

ZL = 2k15pF

= 20V

V

P-P

O

AV = +1, +10, +100
MEASUREMENT BANDWIDTH

0.1
= 10Hz TO 80kHz

AV = 100

0.01

0.001

TOTAL HARMONIC DISTORTION + NOISE (%)

0.0001
20 1k 10k 20k

AV = 10

100

FREQUENCY (Hz)

AV = 1

NOISE FLOOR

6

1113 G19

1113 • G22

Distribution of Offset Voltage Drift
with Temperature (N8, S8)

40

30

20

PERCENT OF UNITS

10

8

0

–20 –15 0

–25

OFFSET VOLTAGE DRIFT WITH TEMPERATURE (µV/°C)

–5

THD and Noise vs Frequency for
Inverting Gain

1

ZL = 2k15pF

= 20V

V

P-P

O

AV = –1, –10, –100
MEASUREMENT BANDWIDTH

0.1
= 10Hz TO 80kHz

0.01
AV = –10

0.001

TOTAL HARMONIC DISTORTION + NOISE (%)

0.0001
20 1k 10k 20k

100

FREQUENCY (Hz)

VS = ±15V

78 S8
100 N8
356 OP AMPS

5

10–10

AV = –100

NOISE FLOOR

152025

1113 G20

AV = –1

1113 G23

Warm-Up Drift

500

VS = ±15V

= 25°C

T

A

400

300

200

100

CHANGE IN OFFSET VOLTAGE (µV)

0

123 5

0

TIME AFTER POWER ON (MINUTES)

IN STILL AIR (S8 PACKAGE

SOLDERED ONTO BOARD)

4

Channel Separation vs Frequency

160

140

120

100

80

60

VS = ±15V

40

CHANNEL SEPARATION (dB)

R

L

V

O

20

TA = 25°C

0

10

LIMITED BY
THERMAL INTERACTION

LIMITED BY

= 1k
= 10V

P-P

100 10k 100k 10M

1k 1M

FREQUENCY (Hz)

PIN-TO-PIN

CAPACITANCE

S8 PACKAGE

N8 PACKAGE

J8 PACKAGE

6

1113 G21

1113 G24

THD and Noise vs Output
Amplitude for Noninverting Gain

1

ZL = 2k15pF, fO = 1kHz

= +1, +10, +100

A

V

MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz

0.1

0.01

0.001

TOTAL HARMONIC DISTORTION + NOISE (%)

0.0001

0.3 10 30

AV = 100

AV = 10

AV = 1

1

OUTPUT SWING (V

8

NOISE FLOOR

)

P-P

1113 • G25

THD and Noise vs Output
Amplitude for Inverting Gain

1

ZL = 2k15pF, fO = 1kHz

= –1, –10, –100

A

V

MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz

0.1

0.01

0.001

TOTAL HARMONIC DISTORTION + NOISE (%)

0.0001

AV = –100

AV = –10

AV = –1

NOISE FLOOR

0.3 10 30

1
OUTPUT SWING (V

P-P

)

1113 • G26

CCIF IMD Test (Equal Amplitude
Tones at 13kHz, 14kHz)*

0.1
VS = ±15V

= 2k

R

L

= 25°C

T

A

0.01

AV = ±10

0.001

INTERMODULATION DISTORTION (AT 1kHz)(%)

0.0001
20m 1 30

0.1
OUTPUT SWING (V

* See LT1115 data sheet for definition of CCIF testing.

P-P

)

10

1113 • G27

LT1113

PPLICATI

A

U

O

I FOR ATIO

S

WU

U

The LT1113 dual in the plastic and ceramic DIP packages
are pin compatible with and directly replace such JFET op
amps as the OPA2111 and OPA2604 with improved noise
performance. Being the lowest noise dual JFET op amp
available to date, the LT1113 can replace many bipolar op
amps that are used in amplifying low level signals from
high impedance transducers. The best bipolar op amps
will eventually loose out to the LT1113 when transducer
impedance increases due to higher current noise. The low
voltage noise of the LT1113 allows it to surpass every dual
and most single JFET op amps available. For the best
performance versus area available anywhere, the LT1113
is offered in the narrow SO-8 surface mount package with
standard pinout and no degradation in performance.

The low voltage and current noise offered by the LT1113
makes it useful in a wide range of applications, especially
where high impedance, capacitive transducers are used
such as hydrophones, precision accelerometers and photo
diodes. The total output noise in such a system is the gain
times the RMS sum of the op amp input referred voltage
noise, the thermal noise of the transducer, and the op amp
bias current noise times the transducer impedance.
Figure 1 shows total input voltage noise versus source
resistance. In a low source resistance (<5k) application
the op amp voltage noise will dominate the total noise.

This means the LT1113 will beat out any dual JFET op amp,
only the lowest noise bipolar op amps have the edge
(at low source resistances). As the source resistance
increases from 5k to 50k, the LT1113 will match the best
bipolar op amps for noise performance, since the thermal
noise of the transducer (4kTR) begins to dominate the
total noise. A further increase in source resistance, above
50k, is where the op amp’s current noise component (2qI
R

) will eventually dominate the total noise. At these

TRANS

B

high source resistances, the LT1113 will out perform
the lowest noise bipolar op amp due to the inherently low
current noise of FET input op amps. Clearly, the LT1113
will extend the range of high impedance transducers
that can be used for high signal to noise ratios. This
makes the LT1113 the best choice for high impedance,
capacitive transducers.

The high input impedance JFET front end makes the
LT1113 suitable in applications where very high charge
sensitivity is required. Figure 2 illustrates the LT1113 in its
inverting and noninverting modes of operation. A charge
amplifier is shown in the inverting mode example; here the
gain depends on the principal of charge conservation at
the input of the LT1113. The charge across the transducer
capacitance, CS, is transferred to the feedback capacitor
CF, resulting in a change in voltage, dV, equal to dQ/CF.

1k

C

S

R

S

–

100

+

C

R

S

10

INPUT NOISE VOLTAGE (nV/√Hz)

1

Figure 1. Comparison of LT1113 and LT1124 Total Output 1kHz Voltage Noise Versus Source Resistance

LT1124

RESISTOR NOISE ONLY

100

1k 100M

LT1124*

LT1113*

V

O

S

†

LT1113

LT1113

SOURCE RESISTANCE (Ω)

100k

LT1124

†

10M10k 1M

SOURCE RESISTANCE = 2RS = R
* PLUS RESISTOR

†

PLUS RESISTOR  1000pF CAPACITOR

Vn = AV √V

n2(OP AMP)

+ 4kTR + 2q IB • R

1113 • F01

2

9

LT1113

PPLICATI

A

U

O

I FOR ATIO

S

R2

C

B

R

B

R1

CSR

S

TRANSDUCER

Figure 2. Noninverting and Inverting Gain Configurations

WU

–

+

CB ≅ C

S

RB = R

S

RS > R1 OR R2

U

OUTPUT

The gain therefore is 1 + CF/CS. For unity gain, CF should
equal the transducer capacitance plus the input capaci­tance of the LT1113 and RF should equal RS. In the
noninverting mode example, the transducer current is
converted to a change in voltage by the transducer capaci­tance; this voltage is then buffered by the LT1113 with a
gain of 1 + R1/R2. A DC path is provided by RS, which is
either the transducer impedance or an external resistor.
Since RS is usually several orders of magnitude greater
than the parallel combination of R1 and R2, RB is added to
balance the DC offset caused by the noninverting input
bias current and RS. The input bias currents, although
small at room temperature, can create significant errors
over increasing temperature, especially with transducer
resistances of up to 100M or more. The optimum value for
RB is determined by equating the thermal noise (4kTRS) to
the current noise (2qIB) times R
in RB = RS = 2VT/I






kT

V

== °

T

q

B

mV at C

26 25 .

2

. Solving for RS results

S






A parallel capacitor, CB, is used to cancel the phase shift
caused by the op amp input capacitance and RB.

R

F

C

F

–

CSR

TRANSDUCER

S

C

B

+

R

B

Q = CV;

OUTPUT

CB = CFC
RB = RFR

S
S

dQ

= I = C

dt

dt

1113 • F02

dV

Reduced Power Supply Operation

The LT1113 can be operated from ±5V supplies for lower
power dissipation resulting in lower IB and noise at the
expense of reduced dynamic range. To illustrate this
benefit, let’s look at the following example:

An LT1113CS8 operates at an ambient temperature of
25°C with ±15V supplies, dissipating 318mW of power
(typical supply current = 10.6mA for the dual). The SO-8
package has a θJA of 190°C/W, which results in a die
temperature increase of 60.4°C or a room temperature die
operating temperature of 85.4°C. At ±5V supplies, the die
temperature increases by only one third of the previous
amount or 20.1°C resulting in a typical die operating
temperature of only 45.1°C. A 40 degree reduction of die
temperature is achieved at the expense of a 20V reduction
in dynamic range. If no DC correction resistor is used at
the input, the input referred offset will be the input bias
current at the operating die temperature times the trans­ducer resistance (refer to Input Bias and Offset Currents vs
Chip Temperature graph in Typical Performance Charac­teristics section). A 100mV input VOS is the result of a 1nA
IB (at 85°C) dropped across a 100M transducer resis­tance; at ±5V supplies, the input offset is only 28mV (IB at
45°C is 280pA). Careful selection of a DC correction

10

LT1113

U

O

PPLICATI

A

INPUT: ±5.2V Sine Wave LT1113 Output OPA2111 Output

resistor (RB) will reduce the IR errors due to IB by an order
of magnitude. A further reduction of IR errors can be
achieved by using a DC servo circuit shown in the applica­tions section of this data sheet. The DC servo has the
advantage of reducing a wide range of IR errors to the
millivolt level over a wide temperature variation. The
preservation of dynamic range is especially important
when reduced supplies are used, since input bias currents
can exceed the nanoamp level for die temperatures
over 85°C.

To take full advantage of a wide input common mode
range, the LT1113 was designed to eliminate phase rever­sal. Referring to the photographs shown in Figure 3, the
LT1113 is shown operating in the follower mode (AV = +1)
at ±5V supplies with the input swinging ±5.2V. The output
of the LT1113 clips cleanly and recovers with no phase
reversal, unlike the competition as shown by the last
photograph. This has the benefit of preventing lock-up in
servo systems and minimizing distortion components.
The effect of input and output overdrive on one amplifier
has no effect on the other, as each amplifier is biased
independently.

I FOR ATIO

S

Figure 3. Voltage Follower with Input Exceeding the Common-Mode Range ( VS = ±5V)

WU

U

Advantages of Matched Dual Op Amps

In many applications the performance of a system
depends on the matching between two operational ampli­fiers rather than the individual characteristics of the two op
amps. Two or three op amp instrumentation amplifiers,
tracking voltage references and low drift active filters
are some of the circuits requiring matching between two
op amps.

The well-known triple op amp configuration in Figure 4
illustrates these concepts. Output offset is a function of the
difference between the two halves of the LT1113. This
error cancellation principle holds for a considerable
number of input referred parameters in addition to
offset voltage and bias current. Input bias current will
be the average of the two noninverting input currents
(IB+). The difference between these two currents (∆IB+)
is the offset current of the instrumentation amplifier.
Common mode and power supply rejections will be
dependent only on the match between the two amplifiers
(assuming perfect resistor matching).

11

LT1113

O

PPLICATI

A

15V

3

–

IN

2

6

5

+

IN

WIDEBAND NOISE DC TO 400kHz =

8

+

1/2

LT1113

IC1

–

1

4

–15V

–

1/2

LT1113

IC1

+

INPUT REFERRED NOISE =

7

GAIN =

BANDWIDTH =

C

U

I FOR ATIO

S

R4
1k

R1
1k

R2
200Ω

R3
1k

R5
1k

100
400kHz

6.6nV/√Hz AT 1kHz

6.6 µV

≤

0.01µF

L

2

3

R7
10k

RMS

WU

R6

10k

C1

50pF

–

1/2

LT1113

IC2

+

U

1

OUTPUT

C

L

1113 • F04

Figure 4. Three Op Amp Instrumentation Amplifier

The concepts of common mode and power supply
rejection ratio match (∆CMRR and ∆PSRR) are best
demonstrated with a numerical example:

Typical performance of the instrumentation amplifier:
Input offset voltage = 0.8mV
Input bias current = 320pA
Input offset current = 10pA
Input resistance = 1011Ω
Input noise = 3.4µV

P-P

High Speed Operation

The low noise performance of the LT1113 was achieved by
making the input JFET differential pair large to maximize
the first stage gain. Increasing the JFET geometry also
increases the parasitic gate capacitance, which if left
unchecked, can result in increased overshoot and ringing.
When the feedback around the op amp is resistive (RF),
a pole will be created with RF, the source resistance and
capacitance (RS,CS), and the amplifier input capacitance
(CIN = 27pF). In closed loop gain configurations and
with RS and RF in the kilohm range (Figure 5), this pole
can create excess phase shift and even oscillation.
A small capacitor (CF) in parallel with RF eliminates this
problem. With RS(CS + CIN) = RFCF, the effect of the
feedback pole is completely removed.

Assume CMRRA = +50µV/V or 86dB,
and CMRRB = + 39µV/V or 88dB,
then ∆CMRR = 11µV/V or 99dB;
if CMRRB = -39µV/V which is still 88dB,
then ∆CMRR = 89µV/V or 81dB
Clearly the LT1113, by specifying and guaranteeing all of

these matching parameters, can significantly improve the
performance of matching-dependent circuits.

C

F

R

F

–

C

IN

R

C

S

S

+

OUTPUT

1113 • F05

Figure 5.

12

LT1113

1. ASSUME VOLTAGE NOISE OF LT1113 AND 51Ω SOURCE RESISTOR = 4.6nV/√Hz

2. GAIN WITH n LT1113s IN PARALLEL = n • 200

3. OUTPUT NOISE = √n • 200 • 4.6nV/√Hz

4. INPUT REFERRED NOISE =

OUTPUT NOISE = 4.6

nV/√Hz

n • 200 √n

5. NOISE CURRENT AT INPUT INCREASES √n TIMES

6. IF n = 5, GAIN = 1000, BANDWIDTH = 1MHz, RMS NOISE, DC TO 1MHz =

9µV

= 4µV

√5

8

15V

–15V

4

8

15V

–15V

4

1113 • TA04

1k

7

6

5

1k

1k

1

2

3

–

+

A2

1/2 LT1113

–

+

1k

51Ω

51Ω

51Ω

1

2

3

A1

1/2 LT1113

10k

7

5

6

–

+

1/2 LT1113

–

+

An

1/2 LT1113

1k

1k

OUTPUT

U

O

PPLICATITYPICAL

SA

Accelerometer Amplifier with DC Servo

C1

1250pF

ACCELEROMETER

B & K MODEL 4381

OR EQUIVALENT

R1

100M

5V TO 15V

–

2

1/2 LT1113

+

3

–5V TO –15V

R3
2k

2µF

7

1/2 LT1113

8

1

4

R2

18k

C2

R4

C3

2µF

20M

20M

R5

–

6

+

5

Paralleling Amplifiers to Reduce Voltage Noise

R4C2 = R5C3 > R1 (1 + R2/R3) C1
OUTPUT = 0.8mV/pC* = 8.0mV/g**
DC OUTPUT ≤ 2.7mV
OUTPUT NOISE = 6nV/√Hz AT 1kHz

*PICOCOULOMBS
**g = EARTH’S GRAVITATIONAL CONSTANT

OUTPUT

1113 • TA03

13

LT1113

PPLICATITYPICAL

HAMAMATSU

S1336-5BK

O

C

D

2N3904

U
SA

Low Noise Light Sensor with DC Servo

C1

2pF

–

2

1/2 LT1113

+

3

D1

1N914

R3

1k

R2C2 > C1R1

= PARASITIC PHOTODIODE CAPACITANCE

C

D

= 100mV/µWATT FOR 200nm WAVE LENGTH

V

O

330mV/µWATT FOR 633nm WAVE LENGTH

7

V

R5
1k

–

D2
1N914

R4
1k

R1

1M

1

+V

8

1/2 LT1113

4

–V

C2

0.022µF

–

6

+

5

OUTPUT

R2

100k

1113 • TA05

10Hz Fourth Order Chebyshev Lowpass Filter (0.01dB Ripple)

R2

237k

C1

33nF

R1

237k

V

IN

TYPICAL OFFSET ≈ 0.8mV
1% TOLERANCES
FOR V

= 10V

IN

= –6dB AT f = 16.3Hz
LOWER RESISTOR VALUES WILL RESULT IN LOWER THERMAL NOISE AND LARGER CAPACITORS

R3

249k

C2
100nF

, V

= –121dB AT f > 330Hz

P-P

OUT

–

2

1/2 LT1113

+

3

15V

–15V

8

1

4

R4

154k

R6

249k

C4
330nF

R5

154k

–

6

1/2 LT1113

+

5

C3

10nF

7

1113 • TA06

V

OUT

14

PACKAGEDESCRIPTI

0.300 BSC

(0.762 BSC)

0.008 – 0.018

(0.203 – 0.457)

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS

(1.143 – 1.727)

0° – 15°

O

0.045 – 0.068

FULL LEAD

OPTION

0.045 – 0.065

(1.143 – 1.651)

0.014 – 0.026

(0.360 – 0.660)

U

Dimensions in inches (millimeters) unless otherwise noted.

J8 Package

8-Lead CERDIP (Narrow 0.300, Hermetic)

(LTC DWG # 05-08-1110)

CORNER LEADS OPTION

(4 PLCS)

0.023 – 0.045

(0.584 – 1.143)

HALF LEAD

OPTION

0.015 – 0.060

(0.381 – 1.524)

0.100
(2.54)

BSC

0.200

(5.080)

MAX

0.125

3.175
MIN

0.005

(0.127)

MIN

0.025

(0.635)

RAD TYP

0.405

(10.287)

MAX

87

12

65

3

4

0.220 – 0.310

(5.588 – 7.874)

J8 1298

LT1113

0.300 – 0.325

(7.620 – 8.255)

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

TYP

8-Lead Plastic Small Outline (Narrow 0.150)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

× 45°

0.016 – 0.050

(0.406 – 1.270)

0°– 8° TYP

N8 Package

8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

0.045 – 0.065

(1.143 – 1.651)

0.100
(2.54)

BSC

0.018 ± 0.003

(0.457 ± 0.076)

S8 Package

(LTC DWG # 05-08-1610)

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

TYP

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

0.020

(0.508)

MIN

0.255 ± 0.015*
(6.477 ± 0.381)

0.228 – 0.244

(5.791 – 6.197)

(10.160)

876

1234

0.189 – 0.197*
(4.801 – 5.004)

7

8

1

2

0.400*

MAX

6

3

5

N8 1098

5

0.150 – 0.157**
(3.810 – 3.988)

4

SO8 1298

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LT1113

U

O

PPLICATITYPICAL

SA

Light Balance Detection Circuit

R1

1M

I

1

PD

1

I

2

PD

2

C1

2pF TO 8pF

–

1/2 LT1113

+

V

= 1M • (I1 – I2)

OUT

PD

= HAMAMATSU S1336-5BK

1,PD2

WHEN EQUAL LIGHT ENTERS PHOTODIODES, V

V

OUT

1113 • TA07

OUT

< 3mV.

Unity Gain Buffer with Extended Load Capacitance Drive Capability

R2

1k

C1

–

1/2 LT1113

+

V

IN

R1

33Ω

V

C

L

C1 = CL ≤ 0.1µF
OUTPUT SHORT-CIRCUIT CURRENT
(∼30mA) WILL LIMIT THE RATE AT WHICH THE
VOLTAGE CAN CHANGE ACROSS LARGE CAPACITORS

OUT

(I = CdV)
dt

1113 • TA08

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1028 Single Low Noise Precision Op Amp V
LT1124 Dual Low Noise Precision Op Amp V
LT1169 Dual Low Noise Precision JFET Op Amp 10pA I
LT1462 Dual Picoamp IB C-LoadTM Op Amp IB = 2pA Max, 10000pF C-Load, IS = 45µA
LT1464 Dual Picoamp IB C-Load Op Amp IB = 2pA Max, 10000pF C-Load, IS = 200µA
LT1792 Single Low Noise Precision Op Amp Single LT1113
LT1793 Single Low Noise Precision Op Amp Single LT1169
C-Load is a trademark of Linear Technology Corporation.

Linear Technology Corporation

16

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

= 1.1nV/√Hz Max

NOISE

= 4.2nV/√Hz Max

NOISE

B

1113fa LT/TP 0100 2K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1993