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1
DESCRIPTION
The LR38574 is a CMOS timing generator IC
which generates timing pulses for driving 1 090 k/
1 310 k-pixel CCD area sensors and processing
pulses.
FEATURES
• Designed for 1/3-type 1 090 k/1 310 k-pixel CCD
area sensors
• Frequency of driving horizontal CCD : 12.27 MHz
• Both double speed drive monitoring mode and
still mode are possible
• Two still mode types :
3 fields period and 4 fields period
• External shutter control function with serial data
input is possible
• +3 V and +4.5 V power supplies
• Package :
48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch
PIN CONNECTIONS
LR38574
LR38574
Timing Generator IC for
1 090 k/1 310 k-pixel CCDs
1
48 47 46 45 44 43 42 41 40 39 37
13 14 15 16 17 18 19 20 21 22 23 24
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
OFDC
V
1x
VH1Ax
VH1Bx
V2x
VDD3
GND
V
3x
VH3Ax
VH3Bx
V4x
OFDX
ID
ED
2
ED1
ED0
HD
GND
V
DD3
VD
DCLK
CLK
CKO
CKI
PBLK
BCPX
CLPX
ADCK
GND
FCDS
FS
V
DD3
ACLX
RS
GND
VCON
SHTR
DRMDFRTST
3
VDD4
FH2
GND
FH1VDD4
CCD
TST
2
TST1
38
48-PIN QFP
TOP VIEW
(QFP048-P-0707)
LR38574
2
BLOCK DIAGRAM
ID
ED2ED1
ED0
HD
GND
V
DD3
VD
DCLK
CLK
CKO
CKI
36 35 34 33 32 31 30 29 28 27 26 25
VCON
GND
RS
ACLX
V
DD3
FS
FCDS
GND
ADCK
CLPX
BCPX
PBLK
OFDC
V
1X
VH1AX
VH1BX
V2X
VDD3
GND
V
3X
VH3AX
VH3BX
V4X
OFDX
TST1
TST2
CCD
V
DD4
FH1
GND
FH
2
VDD4
TST3
FR
DRMD
SHTR
1/2 1/8
GATE
OSC
DATA LATCH & SHUTTER CONTROL
RESET
RESET
RESET
1/2
GATE
H COUNTER
V COUNTER
LEVEL
SHIFTER
DECODER
13
14
15
16
17
18
19
20
21
22
23
24
123456789101112
48
47
46
45
44
43
42
41
40
39
38
37
3
LR38574
PIN NO.
SYMBOL I/O
POLARITY
PIN NAME DESCRIPTION
1 OFDC O3
Control pulse output
for OFD voltage
A pulse to control OFD voltage.
2V
1X O3
Vertical transfer
pulse output 1
A vertical transfer pulse for CCD.
Connect to V
1X pin of vertical driver IC.
3VH1AX O3
Readout pulse
output 1A
A pulse that transfers the charge of the photo-diode to
the vertical shift register.
Connect to VH1AX pin of vertical driver IC.
4VH1BX O3
Readout pulse
output 1B
A pulse that transfers the charge of the photo-diode to
the vertical shift register.
Connect to VH1BX pin of vertical driver IC.
5V2X O3
Vertical transfer
pulse output 2
A vertical transfer pulse for CCD.
Connect to V
2X pin of vertical driver IC.
6VDD3 – Power supply Supply of +3.3 V power.
A grounding pin.Ground–GND7–
9VH
3AX O3
Readout pulse
output 3A
A pulse that transfers the charge of the photo-diode to
the vertical shift register.
Connect to VH
3AX pin of vertical driver IC.
8V
3X O3
Vertical transfer
pulse output 3
A vertical transfer pulse for CCD.
Connect to V
3X pin of vertical driver IC.
A pulse that transfers the charge of the photo-diode to
the vertical shift register.
Connect to VH
3BX pin of vertical driver IC.
Readout pulse
output 3B
O3VH3BX10
11 V
4X O3
Vertical transfer
pulse output 4
A vertical transfer pulse for CCD.
Connect to V
4X pin of vertical driver IC.
A pulse that sweeps the charge of the photo-diode for
the electronic shutter. Connect to OFD pin of CCD
through the vertical driver IC and DC offset circuit.
Held at H level at normal mode.
OFD pulse outputO3OFDX12
13 PBLK O3
Pre-blanking pulse
output
A pulse that corresponds to the cease period of the
horizontal transfer pulse.
A pulse to clamp the optical black signal.
This pulse stays high during the absence of effective
pixels within the vertical blanking or the period of
sweep-out signal.
Optical black clamp
pulse output
O3BCPX 14
15 CLPX O3 Clamp pulse output
A pulse to clamp the dummy outputs of CCD signal.
This pulse stays high during the sweep-out period.
An output pin for AD converter. The output phase of
ADCK is selected by serial data step by 90˚.
AD clock outputO6MA3ADCK16
–
PIN DESCRIPTION
17 GND – Ground A grounding pin.–
4
LR38574
PIN NO.
SYMBOL I/O
POLARITY
PIN NAME DESCRIPTION
20 V
DD3 – Power supply Supply of +3.3 V power.
An input pin for resetting all internal circuits at power on.
Connect to V
DD through the diode and GND through the
capacitor.
All clear inputICU3ACLX21
– A grounding pin.Ground –GND 23
22 RS O6MA3 S/H pulse output
A pulse to sample-hold the signal.
The output phase of RS is selected by serial data.
24 VCON ICU3 VD control input
An input pin to control internal vertical clock for long
shutter speed.
H level or open : VD
L level : VD is masked by the pulse which
is latched at the rising edge of VD.
It's necessary to be set SMD = high and number of the
fields data n ≥ 2 in serial data control at VCON operation.
–
–
A pulse to sample-hold the signal from CCD.
The output phase of FS is selected by serial data.
CDS pulse output 2O6MA3FS 19
–
–
An input pin for reference clock oscillation.
The frequency is 24.54545 MHz.
Clock inputOSCI3CKI25
26 CKO OSCO3 Clock output
An output pin for reference clock oscillation.
The output is the inverse of CKI (pin 25).
–
An output pin to generate HD and VD pulses.
The frequency is 12.72737 MHz.
Clock outputO6MA3CLK27
28 DCLK O6MA3 Clock output
An output pin for DSP IC. The frequency is 12.72727 MHz.
The output phase of DCLK is selected by serial data
step by 90˚.
An input pin for reference of vertical pulse.
Connect to VD pin of DSP IC.
Vertical reference
pulse input
IC3VD29
30 V
DD3 – Power supply Supply of +3.3 V power.–
– A grounding pin.Ground –GND31
32 HD IC3
Horizontal drive
pulse input
An input pin for reference of horizontal pulse.
Connect to HD pin of DSP IC.
An input pin for the strobe pulse, to control the functions
of LR38574. For details, see "Serial Data Control".
Strobe pulse inputICSU3ED
033 –
–34 ED
1 ICSU3
Shift register clock
input
An input pin for the clock of the shift register, to control
the functions of LR38574. For details, see "Serial Data
Control".
18 FCDS O6MA3 CDS pulse output 1
A pulse to clamp the feed-through level from CCD.
The output phase of FCDS is selected by serial data.
5
LR38574
PIN NO.
SYMBOL I/O
POLARITY
PIN NAME DESCRIPTION
A test pin. Set open or to L level in the normal mode.Test pin 1ICD4TST
137
Supply of +4.5 V power.Power supplyV
DD440 – –
O6MA4341 FH
1
Horizontal transfer
pulse output 1
A horizontal transfer pulse for CCD.
Connect to ØH1 pin of CCD.
–
The pulse is used in color separator.
The signal switches between high and low at every line.
Line index pulse
output
O3ID36
–38 TST2 ICD4 Test pin 2 A test pin. Set open or to L level in the normal mode.
An input pin to select CCD. It should be used with
MODE input which is in the serial data.
CCD selection inputICU4CCD39 –
A grounding pin.GroundGND42 – –
O6MA4343 FH
2
Horizontal transfer
pulse output 2
A horizontal transfer pulse for CCD.
Connect to Ø
H2 pin of CCD.
Supply of +4.5 V power. Power supplyV
DD444 – –
–
–
ICD445 TST3 Test pin 3 A test pin. Set open or to L level in the normal mode.
A pulse to reset the charge of output circuit.
The output phase of FR is selected by serial data.
Reset pulse outputFR46 O6MA43
ICU347 DRMD
Drive mode selection
input
An input pin to select the period of still mode.
L level : 3 fields period
H level or open : 4 fields period
A trigger pulse for effective signal period. Trigger outputSHTR48 O3
IC3 : Input pin (CMOS level)
ICU3 : Input pin (CMOS level with pull-up resistor)
ICSU3 : Input pin (CMOS level with schmitt-trigger)
ICU4 : Input pin (CMOS level with pull-up resistor)
ICD4 : Input pin (CMOS level with pull-down resistor)
O3 : Output pin (output high level is V
DD3.)
O6MA3 : Output pin (output high level is V
DD3.)
O6MA43 : Output pin (output high level is V
DD4.)
OSCI3 : Input pin for oscillation
OSCO3 : Output pin for oscillation
–35 ED2 ICSU3
Shift register data
input
An input pin for the data of the shift register, to control
the functions of LR38574. For details, see "Serial Data
Control".
CCD MODE CCD
–
HH
–
LH LZ23J3V
HL–
LL LZ23H3V1
LR38574
6
Serial Data Control
SERIAL DATA INPUT TIMING
The data is shifted at the rising edge of ED
1, and is
latched at the rising edge of ED
0.
PWSA is effective at the rising edge of ED
0, but
others are effective at the horizontal line in which
VH
1AX to VH3BX are active.
ED
0 should be low level during data inputs of ED1
and ED2.
As all internal data are set to low level by ACLX or
PWSA, ED
0 to ED1 should be input for desirable
operations.
As all internal data except PWSA are set to low
level by PWSA, ED
0 to ED1 should be input for
desirable operations.
ED0
ED1
ED2 D29D28 D30 D31D27D26D25D24D23D22D21D09 D10D08D07D06D05D04D03D02D01D00
...
D
11 D20
7
LR38574
DATA
SERIAL DATA INPUTS
NAME FUNCTION DATA = L DATA = H
AT ACLX = L
D00-D06 SD0-SD6 Step of high speed shutter – All L
–Number of exposed fields
SD
7D07
All L
D
09 SD9
D08 SD8
LIntegration mode controlINMDD11
L–Electronic shutter mode controlSMDD10
–PWSAD12
LNegativePLCHD13
Polarity control of FCDS, FS and
RS pulses
Power save control Normal
Monitoring Still
Power save
Positive
L
Uncontinuously
BCPCNTD15 BCP control
Continuously
2 lines/8 lines
Monitoring mode selection
with CCD (pin 39)
D
14 MODE
2 lines/4 lines
L
LZ23H3V1
CCD = L CCD = L
––
CCD = H
LZ23J3V
CCD = H
D18 MR1 L
D
17 ML2 L
Phase control
D16 ML1
–
L
MC
3D23
MC2D22
L
MC
1D21
L
MR
3D20
LMR2D19
D31 MA2
D30 MA1
D29 MF3
D28 MF2
D27 MF1
D26 MS3
D25 MS2
D24 MS1
L
L
L
L
L
L
L
L
L
L
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL
Supply voltage V
DD3, VDD4
VI3
VO3
TOPR
TSTG –55 to +150
–20 to +70
–0.3 to V
DD3 + 0.3
–0.3 to V
DD3 + 0.3
–0.3 to +6.0
RATING UNIT
V
V
V
˚C
˚CStorage temperature
Operating temperature
Output voltage
Input voltage
–
–
–
–
–
VI4
VO4
–0.3 to VDD4 + 0.3
–0.3 to V
DD4 + 0.3 V
V
8
LR38574
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD3 = 3.0 V to VDD4, VDD4 = 4.2 to 5.5 V, TOPR = –20 to +70 ˚C)
Input "Low" voltage VIL3-1
Input "High" voltage VIH3-1
Input "Low" voltage VIL3-2
VIH3-2
Hysteresis voltage VT+ –VT–
Input "Low" voltage VIL4
Input "Low" current |IIL3-1|
Input "High" current |I
IH3-1|
Input "Low" current |IIL3-2|
Input "Low" current |I
IL4-1|
Input "High" current |I
IH4-1|
Input "Low" current |I
IL4-2|
Input "High" current |IIH4-2|
Output "Low" voltage V
OL3-1
Output "High" voltage VOH3-1
Output "Low" voltage VOL3-2
Output "High" voltage VOH3-2
Output "Low" voltage VOL3-3
Output "High" voltage VOH4
PARAMETER SYMBOL CONDITIONS
Input "High" voltage
V
IH4Input "High" voltage
MIN.
0.2V
DD3
0.8V
DD3
V
DD3
– 0.5
4.0
4.0
2.0
0.8V
DD4
0.08V
DD3
V
DD4
– 0.5
V
DD3
– 0.5
TYP.
0.4
MAX.
0.75VDD3
0.2V
DD3
0.4
60
2.0
2.0
60
60
1.0
1.0
0.2V
DD4
0.4
Schmitt-buffer
IOH = –3 mA
I
OL = 3 mA
I
OH = –1 mA
IOL = 2 mA
V
I = VDD4
VI = 0 V
V
I = VDD4
VI = 0 V
V
I = 0 V
VI = VDD3
VI = 0 V
I
OH = –10 mA
I
OL = 3 mA V
Output "Low" voltage V
OL4 0.4IOL = 10 mA V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
UNIT
V
7
NOTE
3
1, 2
6
5
4
9
1
µAV
I = VDD3 2.0|IIH3-2|Input "High" current
2, 3
4, 5
NOTES :
1. Applied to inputs (IC3, OSCI3).
2. Applied to input (ICU3).
3. Applied to input (ICSU3).
4. Applied to input (ICU4).
5. Applied to input (ICD4).
6. Applied to output (O3).
7. Applied to output (OSCO3). (Output (OSCO3) measures
on condition that input (OSCI3) level is 0 V or V
DD3.)
8. Applied to output (O6MA3).
9. Applied to output (O6MA43).
8
VI
OH = –3 mA
V
DD3
– 0.5
VOH3-3Output "High" voltage
PACKAGES FOR CCD AND CMOS DEVICES
9
36
25
37
48
121
0.15
±0.05
0.1
±0.1
9.0
±0.3
7.0
±0.2
7.0
±0.2
(1.0)(1.0)
(1.0)
(1.0)
0.5
TYP.
0.2
±0.08
9.0
±0.3
0.65
±0.2
1.45
±0.2
24
13
Package
base plane
8.0
±0.2
0.08
0.1
M
48 QFP (QFP048-P-0707)
PACKAGE (Unit : mm)
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