Datasheet LP87702-Q1 Datasheet (Texas Instruments)

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Page 1

SW_B0VIN_B0

VIN_B1

VANA

VIN

FB_B0

VOUT0

LOAD

SDA (EN3)

SCL (EN2)

nINT

CLKIN (GPO2/WD_DIS)

GNDs

EN1

SW_B1

FB_B1

VOUT1

PG0

VMON1

VMON2

PG1 (GPO1)

WDI WD_RESET

SW_BST

VOUT_BST

VOUT2

LOAD

GPO0

NRST

Output Current (mA)

Efficiency (%)

1 10 100 1000 5000

100

Exce

VIN=3.3V, VOUT=1.2V VIN=3.3V, VOUT=1.8V VIN=3.3V, VOUT=2.3V

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Technical Documents

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Reference Design

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

LP87702-Q1 Dual Buck Converter and 5-V Boost With Diagnostic Functions

1 Features

• AEC-Q100 Qualified for Automotive Applications: – Device Temperature Grade 1: –40°C to

+125°C, T

• FMEDA and Functional Safety Manual available to support your ASIL compliant system designs

• Two High-Efficiency Step-Down DC/DC converters:

– Maximum Output Current 3.5 A – 2-MHz, 3-MHz, or 4-MHz Switching Frequency – Auto PWM/PFM and Forced-PWM Operations – Output Voltage = 0.7 V to 3.36 V

• 5-V Boost Converter With Bypass-Mode Option: – Maximum Output Current 600 mA

• Two Inputs for External Voltage Monitoring

• Two Programmable Power-Good Signals

• Dedicated Reference Voltage for Diagnostics

• Window Watchdog With Reset Output

• External Clock Input to Synchronize Switching

• Spread-Spectrum Modulation

• Programmable Start-up and Shutdown Delays and Sequencing With Enable Signal

• Configurable General Purpose Outputs (GPOs)

• I2C-Compatible Interface Supporting Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes

• Interrupt Function With Programmable Masking

• Output Short-Circuit and Overload Protection

• Overtemperature Warning and Protection

• Overvoltage Protection (OVP) and Undervoltage Lockout (UVLO)

Simplified Schematic

2 Applications

Automotive Radar, Automotive Camera, Automotive Sensor Fusion, Industrial Radar, Building Automation

3 Description

The LP87702-Q1 helps meet the power management requirements of the latest platforms, particularly in automotive radar and camera and industrial radar applications. The device contains two step-down DC/DC converters, and a 5-V boost converter/bypass switch. To support safety critical applications. the device integrates two voltage monitoring inputs for external power supplies, and a window watchdog.

The automatic PWM/PFM (AUTO mode) operation gives high efficiency over a wide output current range for buck converters. The LP87702-Q1 uses remote voltage sensing to compensate IR drop between the converter output and the point-of-load, thus improving the accuracy of the output voltage.

Programmable start-up and shutdown sequences synchronized to the enable signal are supported, including general purpose digital outputs. During start-up and voltage change, the device controls the output slew rate for minimum output voltage overshoot and inrush current. This device contains one-time-programmable (OTP) memory. Each orderable part number has specific OTP settings for a given application. Details of the default OTP configuration for each orderable part number can be found in the technical reference manual.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

LP87702-Q1 VQFN (32) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at

the end of the data sheet.

Buck Efficiency vs Output Current

(1)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Page 2

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

www.ti.com

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 I2C Serial Bus Timing Parameters.......................... 12

6.7 Typical Characteristics............................................ 15

7 Detailed Description............................................ 16

7.1 Overview................................................................. 16

7.2 Functional Block Diagram....................................... 17

7.3 Feature Descriptions............................................... 17

7.4 Device Functional Modes ....................................... 40

7.5 Programming........................................................... 42

7.6 Register Maps......................................................... 45

8 Application and Implementation ........................ 81

8.1 Application Information............................................ 81

8.2 Typical Application.................................................. 81

9 Power Supply Recommendations...................... 90

10 Layout................................................................... 90

10.1 Layout Guidelines ................................................. 90

10.2 Layout Example .................................................... 91

11 Device and Documentation Support................. 92

11.1 Device Support...................................................... 92

11.2 Receiving Notification of Documentation Updates 92

11.3 Community Resources.......................................... 92

11.4 Trademarks........................................................... 92

11.5 Electrostatic Discharge Caution............................ 92

11.6 Glossary................................................................ 92

12 Mechanical, Packaging, and Orderable

Information........................................................... 92

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (July 2018) to Revision B Page

• Added FMEDA and Functional Safety Manual support availability feature............................................................................ 1

• Changed Description wording ................................................................................................................................................ 1

• Added cross reference to VANA

...................................................................................................................................... 5

OVP

• Added test condition .............................................................................................................................................................. 9

• Changed from typical value to max value ........................................................................................................................... 10

• Added comment on VANA

setting and it's impact on device input voltage range ......................................................... 16

OVP

• Added comment on minimum WDI pulse length .................................................................................................................. 26

• Changed BOOST_SC_INT bit set delay from immediate to 1 ms ...................................................................................... 37

• Changed multiple register bit descriptions............................................................................................................................ 45

Changes from Original (December 2017) to Revision A Page

• First release of production-data data sheet ........................................................................................................................... 1

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Page 3

2 3 4 5 61 7

20 19 18 1723 2122

GPO0

NRST

VIN_B1

SW_B1

PGND_B1

SCL (EN2)

SDA (EN3)

CLK(GPO2)

PGND_B0

WD_RESET

VANA

AGND

FB_B1

FB_B0

SW_B0

VIN_B0

THERMAL PAD

SW_B1

26 15

PG0

VMON1

VMON2 PGND_BST

VOUT_BST

SW_BST

EN1

WDI

PG1 (GPO1)

nINT

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5 Pin Configuration and Functions

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

32-Pin VQFN With Thermal Pad

RHB Package

Top View

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LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

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Pin Functions

NUMBER NAME

1 nINT D/O Open-drain interrupt output. Active LOW. 2 FB_B0 A Output voltage feedback for Buck0. 3 FB_B1 A Output voltage feedback for Buck1. 4 AGND G Ground. 5 VANA P Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx. 6 WD_RESET D/O Reset output from window watchdog 7 WDI D/I Digital input signal for window watchdog 8 VOUT_BST P/O Boost output. Bypass switch output when this mode is selected. 9 SW_BST P/I Boost input. Bypass switch input when this mode is selected. 10 PGND_BST P/G Power ground for boost. 11 NRST D/I Reset signal for the device. 12 GPO0 D/O General purpose digital output 0.

13, 14 VIN_B1 P/I 15, 16 SW_B1 P/O Buck1 switch node.

17, 18 PGND_B1 P/G Power Ground for Buck1. 19 EN1 D/I Programmable Enable 1 signal.

20 SCL D/I

21 SDA D/I/O

22 CLKIN D/I/O 23, 24 PGND_B0 P/G Power ground for Buck0.

25, 26 SW_B0 P/O Buck0 switch node. 27, 28 VIN_B0 P/I 29 PG0 D/O Programmable power-good indication signal.

30 VMON1 A/I Voltage monitoring input 1. 31 VMON2 A/I Voltage monitoring input 2.

32 PG1 D/O Thermal pad N/A G

A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin

TYPE DESCRIPTION

Input for Buck1. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.

Serial interface clock input for I2C access. Connect a pullup resistor. Alternative function is programmable enable 2 signal.

Serial interface data input and output for I2C access. Connect a pullup resistor. Alternative function is programmable enable 3 signal.

External clock input. Alternative function is general purpose digital output 2 (GPO2). Second alternative function is watchdog disable (WD_DIS)

Input for Buck0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.

Programmable power-good indication signal. Alternative function is general purpose digital output 1 (GPO1).

Product Folder Links: LP87702-Q1

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LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

VIN_B0, VIN_B1, SW_BST, VANA

SW_B0, SW_B1 Voltage on buck switch nodes –0.3 (VIN_Bx + 0.3 V) with

FB_B0, FB_B1 Voltage on buck voltage sense nodes –0.3 (VANA + 0.3 V) with

VOUT_BST Voltage on boost output –0.3 6 V SCL (EN2), SDA

(EN3), VMON1, VMON2

NRST, EN1, nINT Voltage on logic pins (input or output pins) –0.3 6 V PG0, PG1 (GPO1),

GPO0, CLKIN (GPO2), WDI, WD_RESET

J-MAX

stg

Maximum lead temperature (soldering, 10 sec.) 260 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground.

Voltage on input power connections –0.3 6

Voltage on voltage monitoring pins –0.3 (VANA + 0.3 V) with

Voltage on logic pins (input or output pins) –0.3 (VANA + 0.3 V) with

Junction temperature −40 150 °C Storage temperature –65 150 °C

(1) (2)

MIN MAX UNIT

6-V max

6-V max V

6.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human-body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2

Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B

(1)

All pins ±500 Corner pins (1, 8, 9, 16,

17, 24, 25, 32)

±2000

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

INPUT VOLTAGE

VIN_B0, VIN_B1, SW_BST, VANA Voltage on input power connections. See also

VANA

OVP

. VMON1, VMON2 Voltage on voltage monitoring pins 0 5.5 NRST, EN1, EN2, EN3, nINT Voltage on logic pins (input or output pins) 0 5.5 PG0, PG1 (GPO1), GPO0, CLKIN

Voltage on logic pins (input or output pins)

(GPO2), WDI, WD_RESET

Voltage on I2C interface, Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4

SCL, SDA

MHz) Modes Voltage on I2C interface, Standard (100 kHz), Fast

(400 kHz), and Fast+ (1 MHz) Modes

TEMPERATURE

Junction temperature –40 140 °C Ambient temperature –40 125 °C

2.8 5.5 V

0 VANA V

0 1.95 V

VANA with 3.6-V

max

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LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

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6.4 Thermal Information

(1)

R R R

θJA θJCtop θJB

JT JB

θJCbot

THERMAL METRIC

Junction-to-ambient thermal resistance 31.7 °C/W Junction-to-case (top) thermal resistance 17.1 °C/W Junction-to-board thermal resistance 5.6 °C/W Junction-to-top characterization parameter 0.2 °C/W Junction-to-board characterization parameter 5.6 °C/W Junction-to-case (bottom) thermal resistance 1.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

RHB (VQFN)

32 PINS

UNIT

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

EXTERNAL COMPONENTS

IN_BUCK

OUT_BUC

K_POL

Input filtering capacitance for buck converters

Output filtering capacitance for buck converters

Point-of-load (POL) capacitance for buck converters

Effective capacitance, connected from VIN_Bx to PGND_Bx

Effective total capacitance. Maximum includes POL capacitance

Optional POL capacitance 22 µF

Output filtering

OUT_BST

ESR

BUCK

capacitance for boost converter

Input and output

capacitor ESR Inductor for buck

converters

Effective capacitance 10 22 40 µF

[1-10] MHz 2 10 mΩ

Inductance of the inductor

Inductance of the inductor, 2-MHz switching 1

BST

Inductor for boost converters

Inductance of the inductor –30% 30%

DCR

Inductor DCR 25 mΩ

BUCK CONVERTERS

(VIN_Bx)

(VANA)

Input voltage range 2.8 3.3 5.5 V

Programmable voltage range 0.7 1 3.36 V

OUT_Bx

Output voltage

Step size, 0.7 V ≤ V

Step size, 1.4 V ≤ V Output current Output current 3.5 Minimum voltage

difference between V electrical characteristics

(VIN_Bx)

and V

OUT_Bx

for

(VIN_Bx)

– V

OUT,IOUT_Bx

– V

OUT,IOUT_Bx

< 0.73 V 10

OUT

< 1.4 V 5

OUT

≤ 3.36 V 20

OUT

≤ 2 A 0.8 > 2 A 1

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

VOUT_Bx

= 5 V and V

1.9 10 µF

15 22 100 µF

0.47

–30% 30%

, V

VOUT_BST

OUT_Bx

, and I

= 1 V,

(3)

OUT

mVStep size, 0.73 V ≤ V

µH

µHInductance of the inductor, 4-MHz switching 1

(1) All voltage values are with respect to network ground. (2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. (3) The maximum output current can be limited by the forward current limit I

junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction

. The maximum output current is also limited by the

LIM FWD

temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.

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Electrical Characteristics (continued)

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DC DC

LNR

LDR

LDSR

LNSR

DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature

Ripple voltage

DC line regulation I DC load regulation in

PWM mode Transient load step

response

Transient line response

Force PWM mode, V

PFM mode, V

voltage level is increased by max. 20 mV

PFM mode, V

voltage level is increased by max. 20 mV

PWM mode, V

OUT

= 22 + 22 µF (GCM31CR71A226KE02)

OUT

PFM mode, L = 0.47 µH, C

(GCM31CR71A226KE02)

= I

OUT

OUT(max)

mode, V

= 22 + 22 µF, L = 0.47 µH, fSW= 4 MHz

µs, I

= 1.0 V, I

OUT_Bx

= 0 A to 3 A, TR= TF= 1 µs, PWM

OUT

(VIN_Bx)

OUT

= 3.3V, V

VIN_Bx

stepping 3 V ↔ 3.5 V, TR= TF= 10

= I

OUT(max)

˂ 1.0 V –20 20 mV

OUT

≥ 1.0 V –2% 2%

OUT

˂ 1.0 V, the average output

≥ 1.0 V, the average output

= 1.2 V, fSW= 4 MHz,

= 22 + 22 µF

OUT

from 0 to I

OUT

= 1.2 V, C

OUT_Bx

Programmable range 1.5 4.5

LIM FWD

LIM NEG

DS(ON) BUCK HS FET

DS(ON) BUCK LS FET

Forward current limit for both bucks (peak for every switching cycle)

Negative current limit 1.6 2 3 A On-resistance, high-side

FET

On-resistance, low-side FET

Switching frequency, PWM mode

OTP programmable

Start-up time (soft start)

Step size 0.5 Accuracy, V Accuracy, 2.8 V ≤ V

(VIN_Bx)

≥ 3 V, I

(VIN_Bx)

= 4 A –5% 7.5% 20%

LIM

< 3 V, I

Each phase, between VIN_Bx and SW_Bx pins (I = 1.0 A)

Each phase, between SW_Bx and PGND_Bx pins (I = 1.0 A)

2-MHz setting or V

4-MHz setting and V From ENx to V

control begins)

OUT_Bx

< 0.8 V 1.8 2 2.2

OUT_Bx

≥ 0.8 V 2.7 3 3.3

OUT_Bx

≥ 1.1 V 3.6 4 4.4

OUT_Bx

= 0.35 V (slew-rate

Overshoot during startup

Output voltage slew-

(4)

rate Output voltage slew-

(4)

rate Output voltage slew-

(4)

rate Output voltage slew-

(4)

rate Output voltage slew-

(4)

rate Output voltage slew-

(4)

rate

SLEW_RATEx[2:0] = 010, V

SLEW_RATEx[2:0] = 011, V

SLEW_RATEx[2:0] = 100, V

SLEW_RATEx[2:0] = 101, V

SLEW_RATEx[2:0] = 110, V

SLEW_RATEx[2:0] = 111, V

VOUT_Bx

= V

VANA

OUT(max)

LIM

VIN_Bx

OUT

= 4 A –20% 7.5% 20%

≥ 0.7 V –15% 10 15% mV/µs

≥ 0.7 V –15% 7.5 15% mV/µs

≥ 0.7 V –15% 3.8 15% mV/µs

≥ 0.7 V –15% 1.9 15% mV/µs

≥ 0.7 V –15% 0.94 15% mV/µs

≥ 0.7 V –15% 0.47 15% mV/µs

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

VOUT_Bx

= 5 V and V

–20 40 mV

–2% 2% + 20mV

±0.05 %/V

0.3%

, V

VOUT_BST

OUT_Bx

, and I

= 1 V,

OUT

±65 mV

±20 mV

60 110 mΩ

55 80 mΩ

MHz3-MHz setting and V

120 µs

50 mV

p-p

(4) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current. Applies when

internal oscillator is used.

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LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Electrical Characteristics (continued)

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Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

VOUT_Bx

= 5 V and V

, V

VOUT_BST

OUT_Bx

, and I

= 1 V,

OUT

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PFM-PWM

PWM-PFM

PFM-to-PWM switch current threshold

PWM-to-PFM switch current threshold

(5)

Output pull-down resistance

520 mA

240 mA

Converter disabled 75 125 175 Ω

BOOST CONVERTER

IN_BST

Input voltage range for boost power inputs

Input voltage range when

2.8 3.3 4 V

4.5 5.5 V bypass switch mode selected

BOOST_VSET = 00 4.9

OUT_BST

Output voltage, boost mode

BOOST_VSET = 01 5.0 BOOST_VSET = 10 5.1

BOOST_VSET = 11 5.2

OUT_BST

LIM_BST

Output current Both boost and bypass mode 0.6 A Output current limit BOOST_ILIM = 00, V

BOOST_ILIM = 01, V BOOST_ILIM = 10, V BOOST_ILIM = 11, V

< 3.6 V 0.8 1 1.3 A

IN_BST

< 3.6 V 1.1 1.4 1.9

IN_BST

< 3.6 V 1.5 1.9 2.3

IN_BST

< 3.6 V 2.2 2.8 3.4

IN_BST

DC output voltage accuracy, includes

OUT_BST

_DC

voltage reference, DC load and line regulations, process and

Default output voltage –3% 3%

temperature. Boost mode

DROP

LDSR

SHORT

DS(ON) BST HS FET

DS(ON) BST LS FET

Voltage drop, bypass mode,

Ripple voltage, boost mode

DC load regulation,

LDR

boost mode Transient load step

response, boost mode Short circuit current

limitation

On-resistance, high-side FET

On-resistance, low-side FET

Switching frequency, boost mode

Start-up time, boost mode

Output pull-down resistance

Iout = 250 mA 83 mV

22 µF effective output capacitance 20 mV

= 1 mA to I

OUT

= 1 mA to 250 mA, TR= TF= 1 µs, 22

OUT

µF effective output capacitance, VIN > 3 V

OUT(max)

–220 220 mV

0.3%

During start-up, both boost and bypass mode. Short circuit current limit applies until V

OUT_BST

= V

IN_BST

Pin-to-pin, between SW_BST and VOUT_BST pins (I = 250 mA)

Pin-to-pin, between SW_BST and PGND_BST pins (I = 250 mA)

625 mA

145 220 mΩ

90 175 mΩ

2-MHz setting 1.8 2 2.2 MHz 4-MHz setting 3.6 4 4.4 MHz From enable to boost VOUT within 3% of

target value. C

OUT_BST

= 22 µF

450 µs

Converter disabled 135 Ω

(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and

the inductor current level.

p-p

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Electrical Characteristics (continued)

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

EXTERNAL CLOCK AND PLL

Nominal frequency 1 24

External input clock

(6)

Nominal frequency step size 1 Required accuracy from nominal frequency –30% 10% Delay for detecting loss of external clock,

External clock detection

nominal internal clock, clock accuracy ±10% Delay for detecting valid external clock,

nominal internal clock, clock accuracy ±10%

Clock change delay (internal to external)

Delay from valid clock detection to use of external clock

PLL output clock jitter Cycle to cycle 300 ps, p-p

MONITORING FUNCTIONS

Voltage threshold, VANA_THRESHOLD = 0 3.3

Voltage threshold, VANA_THRESHOLD = 1 5.0 VANA Voltage Monitoring

Voltage window, VANA_WINDOW = 00 +/-3% +/-4% +/-5%

Voltage window, VANA_WINDOW = 01 +/-4% +/-5% +/-6%

Voltage window, VANA_WINDOW = 10 or 11 +/-9% +/-10% +/-11%

VMONx_THRESHOLD = 000 0.65

VMONx_THRESHOLD = 001 0.8

VMONx_THRESHOLD = 010 1.0 VMON1 and VMON2

Voltage Monitoring Thresholds

VMONx_THRESHOLD = 011 1.1

VMONx_THRESHOLD = 100 1.2

VMONx_THRESHOLD = 101 1.3

VMONx_THRESHOLD = 110 1.8

VMONx_THRESHOLD = 111 1.8

VMONx_WINDOW = 00,

VMONx_THRESHOLD from 000 to 111

VMON1 and VMON2 Voltage Monitoring Windows

VMONx_WINDOW = 01,

VMONx_THRESHOLD from 000 to 111

VMONx_WINDOW = 10,

VMONx_THRESHOLD from 000 to 111

VMONx_WINDOW = 11,

VMONx_THRESHOLD from 000 to 111

BUCKx_WINDOW = 00 +/-20 +/-30 +/-40 Buck0 and Buck1

Voltage Monitoring Windows

BUCKx_WINDOW = 01 +/-37 +/-50 +/-63

BUCKx_WINDOW = 10 +/-57 +/-70 +/-83

BUCKx_WINDOW = 11 +/-77 +/-90 +/-103

BOOST_WINDOW = 00 +/-0.6% +/-2% +/-3.4%

Boost Voltage Monitoring

BOOST_WINDOW = 01 +/-2.6% +/-4% +/-5.4%

BOOST_WINDOW = 10 +/-4.6% +/-6% +/-7.4%

BOOST_WINDOW = 11 +/-6.6% +/-8% +/-9.4%

Deglitch time

VANA, VMONx and BOOST monitoring 12 17

BUCKx monitoring 6 9

PROTECTION FUNCTIONS

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

VOUT_Bx

= 5 V and V

600 µs

+/-1% +/-2% +/-3%

+/-2% +/-3% +/-4%

+/-3% +/-4% +/-5%

+/-5% +/-6% +/-7%

, V

VOUT_BST

OUT_Bx

, and I

= 1 V,

1.8

OUT

MHz

µs

μs

(6) The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.

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Page 10

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Electrical Characteristics (continued)

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Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Temperature rising, TDIE_WARN_LEVEL =

0 Thermal warning

Hysteresis 20

Thermal shutdown

Temperature rising 140 150 160

Hysteresis 20

Voltage rising, VANA_OVP_SEL = 0 5.6 5.8 6.1

Voltage falling, VANA_OVP_SEL = 0 5.45 5.73 5.96

VANA

VANA Overvoltage

OVP

Voltage rising, VANA_OVP_SEL = 1 4.1 4.3 4.6

Voltage falling, VANA_OVP_SEL = 1 3.95 4.23 4.46

Hysteresis 40 200 mV

VANA

VANA Undervoltage

UVL

Lockout BUCKx short circuit

Voltage rising 2.51 2.63 2.75

Voltage falling 2.5 2.6 2.7

Threshold 0.32 0.35 0.45 V detection

Bypass short circuit current limit

LOAD CURRENT MEASUREMENT FOR BUCK CONVERTERS

Current measurement range

Current corresponding to maximum output

code (note: maximum current for LP87702

buck is 3.5A) Resolution LSB 20 mA Measurement accuracy I

> 1A <10%

OUT

Auto mode (automatically changing to PWM Measurement time

mode for the measurement)

PWM mode 25

CURRENT CONSUMPTION

Shutdown current

NRST = 0 1 µA consumption

Standby current consumption, converters

NRST = 1 9 µA disabled

Active current consumption, one buck converter enabled in Auto mode, internal RC

= 0 mA, not switching 55 µA

OUT_Bx

oscillator Active current

consumption, two buck converters enabled in Auto mode, internal RC

= 0 mA, not switching 90 µA

OUT_Bx

oscillator Active current

consumption during PWM operation, one

= 0 mA 15 mA

OUT_Bx

buck converter enabled Active current

consumption during PWM operation, two

= 0 mA 27 mA

OUT_Bx

buck converters enabled

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

115 125 135

130 140 150

VIN_Bx

OUT_BST

, V

VOUT_Bx

, V

VOUT_BST

= 5 V and V

270 420 mA

, and I

= 1 V,

OUT_Bx

10.22 A

OUT

°CTemperature rising, TDIE_WARN_LEVEL =

°C

µs

Product Folder Links: LP87702-Q1

Page 11

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Electrical Characteristics (continued)

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Active current consumption, Boost converter in PWM

OUT_BST

= 0 mA, fSW= 4 MHz 18 mA operation PLL and clock detector

current consumption

Additional current consumption when enabled, 2 MHz external clock

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

VOUT_Bx

= 5 V and V

, V

VOUT_BST

OUT_Bx

, and I

= 1 V,

OUT

2 mA

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Page 12

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Electrical Characteristics (continued)

www.ti.com

Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUT SIGNALS SCL, SDA, NRST, EN1, EN2, EN3, CLKIN, WDI

HYS

Input low level 0.4 Input high level 1.2 Hysteresis of Schmitt

Trigger inputs ENx, CLKIN, WDI pull-

down resistance NRST pull-down

resistance

ENx_PD = 1, CLKIN_PD = 1, WDI_PD = 1 500 kΩ

Always enabled 500 kΩ

DIGITAL OUTPUT SIGNALS nINT, SDA

Output low level

External pull-up resistor for nINT

SDA: I nINT: I

To VIO Supply 10 kΩ

= 20 mA 0.5

SOURCE

= 2 mA 0.4

SOURCE

DIGITAL OUTPUT SIGNALS PGOOD, PG1, GPO0, GPO1, GPO2, WD_RESET

Output low level I Output high level,

configured to push-pull

= 2 mA 0.4

SOURCE

= 2 mA V

SINK

Supply voltage for

external pull-up resistor, configured to open-drain

External pull-up resistor, configured to open-drain

ALL DIGITAL INPUTS

All logic inputs except NRST, over pin

LEAK

Input current

voltage range, when PD not enabled NRST, over pin voltage range. Other logic

inputs when PD enabled.

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

10 80 200 mV

- 0.4 V

VANA

−1 1 µA –1 20 µA

, V

VOUT_Bx

= 5 V and V

VOUT_BST

OUT_Bx

10 kΩ

VANA

, and I

= 1 V,

OUT

6.6 I2C Serial Bus Timing Parameters

(1)

See

. MIN MAX UNIT

Standard mode 100 Fast mode 400

SCL

LOW

(1) Cbrefers to the capacitance of one bus line. Cbis expressed in pF units. 12

Serial clock frequency

Fast mode + 1

High-speed mode, Cb= 400 pF 1.7 Standard mode 4.7

SCL low time

Fast mode + 0.5 High-speed mode, Cb= 100 pF 160 High-speed mode, Cb= 400 pF 320

Product Folder Links: LP87702-Q1

kHz

MHzHigh-speed mode, Cb= 100 pF 3.4

µsFast mode 1.3

Page 13

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I2C Serial Bus Timing Parameters (continued)

(1)

See

. MIN MAX UNIT

Standard mode 4

HIGH

SU;DAT

HD;DAT

SU;STA

HD;STA

BUF

SU;STO

rDA

fDA

rCL

SCL high time

Data setup time

Data hold time

Setup time for a start or a repeated start condition

Hold time for a start or a repeated start condition

Bus free time between a stop and start condition

Setup time for a stop condition

Rise time of SDA signal

Fall time of SDA signal

Rise time of SCL signal

Fast mode + 0.26 High-speed mode, Cb= 100 pF 60 High-speed mode, Cb= 400 pF 120 Standard mode 250 Fast mode 100 Fast mode + 50 High-speed mode 10 Standard mode 0.01 3.45

Fast mode + 0.01 High-speed mode, Cb= 100 pF 10 70 High-speed mode, Cb= 400 pF 10 150 Standard mode 4.7

Fast mode + 0.26 High-speed mode 160 ns Standard mode 4

Fast mode + 0.26 High-speed mode 160 ns Standard Mode 4.7

Fast mode + 0.5 Standard Mode 4

Fast mode + 0.26 High-speed mode 160 ns Standard mode 1000 Fast mode 20+0.1 C Fast mode + 120 High-speed mode, Cb= 100 pF 10 80 High-speed mode, Cb= 400 pF 20 160 Standard mode 250 Fast mode 20+0.1 C Fast mode + 20+0.1 C High-speed mode, Cb= 100 pF 10 80 High-speed mode, Cb= 400 pF 20 160 Standard mode 1000 Fast mode 20+0.1 C Fast mode + 120 High-speed mode, Cb= 100 pF 10 40 High-speed mode, Cb= 400 pF 20 80

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

µsFast mode 0.6

µsFast mode 0.01 0.9

µsFast mode 0.6

µsFast Mode 1.3

µsFast Mode 0.6

b b

300

250 120

300

Product Folder Links: LP87702-Q1

Page 14

SCL

SDA

LOW

rCL

HD;DAT

HIGH

fCL

SU;DAT

SU;STA

SU;STO

START

REPEATED

START

STOP

HD;STA

START

rDA

BUF

fDA

HD;STA

RS P

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

I2C Serial Bus Timing Parameters (continued)

(1)

See

. MIN MAX UNIT

Standard mode 1000 Fast mode 20+0.1 C Fast mode + 120 High-speed mode, Cb= 100 pF 10 80 High-speed mode, Cb= 400 pF 20 160 Standard mode 300 Fast mode 20+0.1 C Fast mode + 20+0.1 C High-speed mode, Cb= 100 pF 10 40 High-speed mode, Cb= 400 pF 20 80

Fast mode, Fast mode + 50

High-speed mode 10

rCL1

fCL

Rise time of SCL signal after a repeated start condition and after an acknowledge bit

Fall time of a SCL signal

Capacitive load for each bus line (SCL and SDA)

Pulse width of spike suppressed (Spikes shorter than indicated width are suppressed)

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300

b b

300 120

400 pF

Figure 1. I2C Timing

Product Folder Links: LP87702-Q1

Page 15

Input Voltage (V)

Input Current (mA)

2.8 3 3.2 3.4 3.6 3.8 4

D014

OUT

= 5.0 V Load = 0 mA

Input Voltage (V)

Input Current (µA)

2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

D013

OUT

= 1.2 V Load = 0 mA

Input Voltage (V)

Input Current (mA)

2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

D012

OUT

= 1.2 V Load = 0 mA

Input Voltage (V)

Input Current (µA)

2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

0.5

1.5

2.5

3.5

D016

(NRST)

= 0 V

Input Voltage (V)

Input Current (µA)

2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

D015

(NRST)

= 1.8 V Regulators disabled

LP87702-Q1

www.ti.com

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

6.7 Typical Characteristics

Unless otherwise specified: VIN= 3.3 V, TA= 25°C, ƒSW-setting 4 MHz, L0 = L1 = 0.47 µH (TOKO DFE252012PD-R47M), L2 = 1 µH (TFM252012ALMA1R0), C

OUT_BUCK

using connections in the Figure 81.

Figure 2. Shutdown Current Consumption vs Input Voltage Figure 3. Standby Current Consumption vs Input Voltage

= 22 µF, and C

POL_BUCK

= 22 µF, C

OUT_BOOST

= 22 µF. Measurements are done

Figure 4. Active State Current Consumption vs Input

Voltage, One Buck Converter Enabled in PFM Mode

Figure 6. Active State Current Consumption vs Input Voltage, Boost Converter Enabled in PWM Mode

Figure 5. Active State Current Consumption vs Input Voltage, One Buck Converter Enabled in PWM Mode

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LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

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7 Detailed Description

7.1 Overview

The LP87702-Q1 is a high-efficiency, high-performance power supply IC with two step-down DC/DC converters (Buck0 and Buck1) and boost converter for automotive and industrial applications. Input voltage range is from 2.8 V to 5.5 V. Typical application input voltage levels are 3.3 V and 5 V. With 3.3V input and boost enabled, VANA to 5.8 V (typ). VANA output characteristics of the various converters. Boost has an alternate bypass switch mode. Selection between boost and bypass modes is defined in OTP and is fixed.

is set to 4.3V (typ). When input voltage is 5 V, boost can be used as a load switch and VANA

OVP

is selected in OTP by VANA_OVP_SEL and is a fixed factory setting. Table 1 lists the

OVP

Table 1. Supply Specification

SUPPLY

Boost 4.9 to 5.2 100 600

Buck0 0.7 to 3.36

Buck1 0.7 to 3.36

RANGE (V) RESOLUTION (mV) I

OUT

10 (0.7 V to 0.73 V)

5 (0.73 V to 1.4 V)

20 (1.4 V to 3.36 V) 10 (0.7 V to 0.73 V)

5 (0.73 V to 1.4 V)

20 (1.4 V to 3.36 V)

OUTPUT

MAXIMUM OUTPUT CURRENT (mA)

MAX

3500

OVP

is set

The LP87702-Q1 converters support switching clock synchronization to an external clock connected to CLKIN input. The external clock can be from 1 MHz to 24 MHz with 1-MHz steps. Alternatively, optional spread spectrum mode can be enabled to reduce EMI.

LP87702-Q1 features include diagnostics, monitoring and protections for both device internal and system level operation:

• Soft start

• Input undervoltage lockout

• Programmable undervoltage or window (over- and undervoltage) monitoring for the input (from VANA pin)

• Programmable undervoltage or window (over- and undervoltage) monitoring for the buck and boost converter outputs

• Two inputs (VMONx) with programmable undervoltage or window (over- and undervoltage) thresholds, for monitoring external rails in the system

• One dedicated power-good output (PG0) to which selected monitoring signals can be combined

• Second programmable power-good output (PG1), multiplexed with general purpose output (GPO1)

• Power good flags with maskable interrupt

• Programmable window watchdog

• Buck and boost converter overload detection

• Thermal warning with two selectable thresholds

• Thermal shutdown

LP87702-Q1 control interface:

• Up to three enable inputs ( EN1, EN2 and EN3) with programmable power-up/power-down sequence control

• Optional I2C (multiplexed with EN2 and EN3 inputs)

• Interrupt signal (nINT) to host

• Reset input (NRST)

• One dedicated general purpose output (GPO0)

• Watchdog disable WD_DIS, multiplexed with CLKIN/GPO2

Product Folder Links: LP87702-Q1

Page 17

Diagnostics

UVLO

Reset

Digital

Logic

Registers

I2C

Enable/

Disable,

Delay

Control

Slew-Rate

Control

Interrupts

nINT

SDA / EN3

SCL / EN2

EN1

VANA

OTP

EPROM

Thermal

Monitor

Oscillator

Buck0

ILIM Det

Pwrgood

Det

Overload

and SC

Det

Buck1

Boost

ILIM Det Pwrgood

Det

Overload

and SC Det

ILIM Det

Pwrgood Det

Overload and

SC Det

Ref &

Bias

Iload ADC

CLKIN / GPO2/ WD_DIS

GPO0

Ref &

Bias

PG0

PG1/ GPO1

VMON1

VMON2

Window

Watchdog

WD_RESET

WDI

NRST

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7.2 Functional Block Diagram

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

7.3 Feature Descriptions

7.3.1 Step-Down DC/DC Converters

7.3.1.1 Overview

The LP87702-Q1 includes two high-efficiency step-down DC/DC converters. The buck converters deliver 0.7-V to

3.36-V regulated voltage rails from 2.8-V to 5.5-V input-supply voltage. The converters are designed for flexibility;

most of the functions are programmable, thus optimizing the converter operation for each application:

• DVS support with programmable slew rate

• Automatic mode control based on the loading (PWM or PFM mode)

• Forced PWM mode option

• Optional external clock input to minimize crosstalk

• Optional spread spectrum technique to reduce EMI

• Synchronous rectification

• Current mode loop with PI compensator

• Soft start

• Programmable output voltage monitoring with maskable interrupt and selectable connection PG0 and/or PG1

• Average output current sensing (for PFM entry and load current measurement)

Product Folder Links: LP87702-Q1

Page 18

POWER GOOD

LOOP COMP

RAMP

GENERATOR

HS FET

CURRENT

SENSE

LS FET

CURRENT

SENSE

GATE

CONTROL

IADC

VDAC

ERROR

AMP

GND

NEG

CURRENT

LIMIT

ZERO

CROSS

DETECT

POS

CURRENT

LIMIT

VIN

OUT

CONTROL

BLOCK

PROGRAMMABLE

PARAMETERS

VOLTAGE

SETTING

SLEW RATE

CONTROL

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

www.ti.com

Feature Descriptions (continued)

Some of the key parameters that can be programmed via registers (with default values set by OTP bits):

• Output voltage

• Forced PWM operation

• Switch current limit

• Output voltage slew rate

• Enable and disable delays with ENx pin control

There are two modes of operation for the buck converters, depending on the output current required: pulse width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 520 mA or higher. Lighter output current loads will cause the converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode is disabled. The forced PWM mode can be selected to maintain fixed switching frequency at all load currents. When buck is disabled, buck output is isolated from the input voltage rail. Output has an optional pulldown resistor.

A block diagram of a single buck converter is shown in Figure 7.

Figure 7. Detailed Block Diagram Showing One Buck Converter

7.3.1.2 Transition Between PWM and PFM Modes

The LP87702-Q1 buck converter operates in PWM mode at load current of about 520 mA or higher. At lighter load current levels the device automatically switches into PFM mode for reduced current consumption when forced PWM mode is disabled (AUTO mode operation). By combining the PFM and the PWM modes a high efficiency is achieved over a wide output-load current range.

7.3.1.3 Buck Converter Load Current Measurement

Buck load current can be monitored via I2C registers. The monitored buck converter is selected with the LOAD_CURRENT_BUCK_SELECT bit in SEL_I_LOAD register. A write to this selection register starts a current measurement sequence. The converter is forced to PWM mode during the measurement. The measurement sequence is 50 µs long at maximum. LP87702-Q1 can be configured to give out an I_MEAS_INT interrupt in INT_TOP_1 register after the load current measurement sequence is finished. Load current measurement interrupt can be masked with I_MEAS_MASK bit in TOP_MASK_1 register. The measurement result can be read from I_LOAD_1 and I_LOAD_2 registers. The Buck converter load current measurement result is 9-bit wide, with 8 LSB bits stored in I_LOAD_1 register and 1 MSB bit stored in I_LOAD_2 register. The single bit resolution is 20 mA, with a maximum load current value of 10.22A.

Product Folder Links: LP87702-Q1

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LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Feature Descriptions (continued)

7.3.2 Boost Converter

The LP87702-Q1 device integrates a boost converter with programmable output voltage from 4.9V to 5.2V in

0.1V steps, and input voltage range from 2.8V to 4V. The boost converter has flexibility to support wide range of

application conditions:

• Forced PWM operation

• Optional external clock input to minimize crosstalk

• Optional spread spectrum technique to reduce EMI

• Synchronous rectification

• Current mode loop with PI compensator

• Soft start

• Programmable output voltage monitoring with maskable interrupt and selectable connection to PG0 and/or PG1

Following parameters can be programmed via registers, with default values set by OTP bits unless otherwise noted:

• Output voltage level (BOOST_VSET)

• Switch current limit (BOOST_ILIM)

• Enable and disable delays when ENx pin control is used (BOOST_DELAY register)

• Output pulldown resistor enable/disable when boost is disabled (BOOST_RDIS_EN bit, discharge is enabled by default)

• Output voltage monitoring enable/disable and monitoring window thresholds

The boost converter operates in forced PWM mode with fixed switching frequency across all load currents. When boost is disabled, boost output is isolated from the input voltage rail.

Boost converter supports an alternative operating mode as a bypass/load switch, with input voltage range from

4.5V to 5.5V. Operating mode is selected in OTP and is fixed, changing the mode on-the-fly is not supported.

7.3.3 Spread-Spectrum Mode

Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add EMI-filters and shields to the boards. The LP87702-Q1 device supports spread-spectrum switching frequency modulation mode that is register controlled. This mode minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency varies between 0.85 × fSWand fSW, where fSWis switching frequency selected in the OTP. Spread spectrum modulation reduces conducted and radiated emissions by the converter and associated passive components and PCB traces (see Figure 8). This feature is available only when internal RC oscillator is used (EN_PLL is 0 in PLL_CTRL register) and it is enabled with the EN_SPREAD_SPEC bit in CONFIG register, and it affects both buck converters and the boost converter.

Product Folder Links: LP87702-Q1

Page 20

24 MHz

Oscillator

CLKIN

Divider

´(;7_CLK

_)5(4´

PLL

Divider

CLKIN

Detector

Clock Select

Logic

Internal

24 MHz

clock

1 MHz

´(1_3//´

24 MHz

Power Spectrum is

Spread and Lowered

Frequency

Radiated Energy

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Feature Descriptions (continued)

Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread spectrum architecture of the LP87702-Q1 spreads that energy over a large bandwidth.

Figure 8. Spread Spectrum Modulation

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7.3.4 Sync Clock Functionality

The LP87702-Q1 device contains a CLKIN input to synchronize buck and boost converters' switching clock with the external clock. The block diagram of the clocking and PLL module is shown in Figure 9. Depending on the EN_PLL bit in PLL_CTRL register and the external clock availability, the external clock is selected and interrupt is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits in PLL_CTRL register and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy limits (–30%/+10%) for valid clock detection.

The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases the external clock is expected but it is not available. These cases are Startup (Read OTP-to-standby transition) when EN_PLL = 1 and buck or boost converter is enabled (standby-to-active transition) when EN_PLL = 1.

Figure 9. Clock and PLL Module

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LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Feature Descriptions (continued)

Table 2. PLL Operation

DEVICE

OPERATION MODE

STANDBY 0 Disabled No Internal RC

ACTIVE 0 Disabled No Internal RC

STANDBY 1 Enabled

ACTIVE 1 Enabled

EN_PLL

7.3.5 Power-Up

The power-up sequence for the LP87702-Q1 is as follows:

• VANA (and VIN_Bx) reach minimum recommended levels (V

• Driving NRST input high initiates OTP read and enables the system I/O interface. Minimum delay from NRST reset input rising edge to I2C write or read access is 1.2ms.

• Device enters STANDBY mode. Watchdog operation starts.

• The host can change the default register setting by I2C if needed.

• The converters can be enabled/disabled and the GPOx signals can be controlled by ENx pins and by I2C interface.

PLL AND CLOCK

DETECTOR STATE

INTERRUPT FOR

EXTERNAL CLOCK

When external clock

disappears or appears

When external clock

disappears or appears

> VANA

VANA

UVLO

CLOCK

Automatic change to internal

RC oscillator when External

clock is not available

Automatic change to internal

RC oscillator when External

clock is not available

7.3.6 Buck and Boost Control

7.3.6.1 Enabling and Disabling Converters

The buck converters can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to enable and disable the buck converters:

• Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 00 in BUCKx_CTRL_1 register)

• Using ENx control pin (BUCKx_EN bit is 1 in BUCKx_CTRL_1 register AND BUCKx_EN_PIN_CTRL bit is not 00 in BUCKx_CTRL_1 register)

Similarly there are two ways to enable and disable the boost converter:

• Using BOOST_EN bit in BOOST_CTRL register (BOOST_EN_PIN_CTRL bit is 0 in BOOST_CTRL register)

• Using ENx control pin (BOOST_EN bit is 1 in BOOST_CTRL register AND BOOST_EN_PIN_CTRL bit is not 00 in BOOST_CTRL register)

If the ENx control pin is used to enable and disable then the delay from the control signal rising edge to start-up is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_STARTUP_DELAY[3:0] bits in BOOST_DELAY register. The delay from falling edge of control signal to shutdown is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_SHUTDOWN_DELAY[3:0] bits in BOOST_DELAY register. The delays are valid only when ENx pin control is used, not when converters are enabled by I2C write to BUCKx_EN and BOOST_EN bits.

The control of the converters (with 0-ms delays) is shown in Table 3.

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LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

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Table 3. Converter Control

BUCKx_EN_PIN_C

TRL /

BOOST_EN_PIN_C

TRL

0 Don't Care Don't Care Don't Care Don't Care Disabled 1 00 Don't Care Don't Care Don't Care BUCKx_VSET[7:0] / BOOST_VSET[1:0]

1 01 Low Don't Care Don't Care Disabled 1 01 High Don't Care Don'tCare BUCKx_VSET[7:0] / BOOST_VSET[1:0] 1 10 Don't Care Low Don't Care Disabled 1 10 Don't Care High Don't Care BUCKx_VSET[7:0] / BOOST_VSET[1:0] 1 11 Don't Care Don't Care Low Disabled 1 11 Don't Care Don't Care High BUCKx_VSET[7:0] / BOOST_VSET[1:0]

EN1 PIN EN2 PIN EN3 PIN

BUCKx OUTPUT VOLTAGE /

BOOST OUTPUT VOLTAGE

Enable/disable control

with

BUCKx_EN/BOOST_EN

bit

Enable/disable control

with EN1 pin

Enable/disable control

with EN2 pin

Enable/disable control

with EN3 pin

BUCKx_EN /

BOOST_EN

BUCKx converter is enabled by an ENx pin or by I2C write access as shown in Figure 10. The soft-start circuit limits the in-rush current during start-up. Output voltage increase rate is typically 30 mV/μsec during soft start. When the output voltage rises to 0.35-V level, the output voltage becomes slew-rate controlled. If there is a short circuit at the output and the output voltage does not increase above a 0.35-V level in 1 ms, the converter is disabled, and interrupt is set. When the output voltage rises above the undervoltage power-good threshold level the BUCKx_PG_INT interrupt flag in INT_BUCK register is set.

Power-good thresholds are defined by BUCKx_WINDOW bits. A PGOOD_WINDOW bit in PGOOD_CTRL register sets the detection method for the valid buck output voltage, either undervoltage detection or undervoltage and overvoltage detection. The powergood interrupt flag when reaching valid output voltage can be masked using BUCKx_PGR_MASK bit in BUCK_MASK register. The power-good interrupt flag can be also generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by BUCKx_PGF_MASK bit in BUCK_MASK register. When window monitoring (under and overvoltage monitoring) is selected, mask bits apply when voltage is crossing either threshold. A BUCKx_PG_STAT bit in BUCK_STAT register shows always the validity of the output voltage; '1' means valid, and '0' means invalid output voltage.

Product Folder Links: LP87702-Q1

Page 23

0.6V

Enable

Time

Voltage

Soft start

Ramp

BUCKx_SLEW_RATE[2:0]

Resistive pull-down

(if enabled)

BUCKx_VSET[7:0]

INT_BUCK(BUCKx_PG_INT)

nINT

BUCK_STATUS(BUCKx_PG_STAT)

0.35V

Voltage decrease because of load

BUCK_STATUS(BUCKx_STAT)

BUCK_MASK(BUCKx_PGF_MASK) = 0

BUCK_MASK(BUCKx_PGR_MASK) = 0

Host clears

interrupts

Powergood

interrupts

00 1

0 1

10 0 1 0 1 0 1 0

BUCKx_WINDOW[1:0]

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The boost converter is enabled by an ENx pin or by I2C write access as shown in Figure 11. The soft-start circuit limits the in-rush current during start-up. Output voltage increase rate is less than 100 mV/μsec during soft start. If there is a short circuit at the output and the output voltage does not reach input voltage level in 1 ms, the converter is disabled, and interrupt is set. When the output voltage reaches the power-good threshold level the BOOST_PG_INT interrupt flag in INT_BOOST register is set.

Power-good thresholds are defined by BOOST_WINDOW bits. A PGOOD_WINDOW bit in PGOOD_CTRL register sets the detection method for the valid boost output voltage, either undervoltage detection or undervoltage and overvoltage detection. The power-good interrupt flag when reaching valid output voltage can be masked using BOOST_PGR_MASK bit in BOOST_MASK register. The power-good interrupt flag can be also generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by BOOST_PGF_MASK bit in BOOST_MASK register. A BOOST_PG_STAT bit in BOOST_STAT register shows always the validity of the output voltage; '1' means valid and '0' means invalid output voltage.

The ENx input pins have integrated pulldown resistors. The pulldown resistors are enabled by default and host can disable those with ENx_PD bits in CONFIG register.

Figure 10. Buck Converter Enable and Disable

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Enable

Time

Voltage

Resistive pull-down

(if enabled)

BOOST_VSET[1:0]

INT_BOOST(BOOST_PG_INT)

nINT

Host clears

interrupts

Powergood

interrupts

BOOST_STATUS(BOOST_PG_STAT)

00 1

Voltage decrease because of load

BOOST_STATUS(BOOST_STAT)

00 1

0 1

10 0 1 0 1 0

BOOST_MASK(BOOST_PGF_MASK) = 0

BOOST_MASK(BOOST_PGR_MASK) = 0

1 0

BOOST_WINDOW[1:0]

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7.3.6.2 Changing Buck Output Voltage

The output voltage of BUCKx converter can be changed by writing to the BUCKx_VOUT register. The voltage change for buck converter is always slew-rate controlled, and the slew-rate is defined by the BUCKx_SLEW_RATE[2:0] bits in BUCKx_CTRL_2 register. During voltage change the forced PWM mode is used automatically. When the programmed output voltage is achieved, the mode becomes the one defined by load current, and the BUCKx_FPWM bit.

The voltage change and power-good interrupts are shown in Figure 12.

Figure 11. Boost Converter Enable and Disable

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Time

Voltage

Ramp for Buck

BUCKx_CTRL2(BUCKx_SLEW_RATE[2:0])

BUCKx_VSET

INT_BUCK(BUCKx_PG_INT)

nINT

Host clears

interrupt

Powergood

interrupt

Powergood

BUCK_STATUS(BUCKx_STAT)

Powergood

BUCK_STATUS(BUCKx_PG_STAT)

Host clears

interrupt

Powergood

interrupt

1 0 1 0 1

0 1 0 1 0

BUCK_MASK(BUCKx_PGF_MASK)=0

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7.3.7 Enable and Disable Sequences

The LP87702-Q1 device supports programmable start-up and shutdown sequencing. An enable control signal is used to initiate the start-up sequence and to turn off the device according to the programmed shutdown sequence. Up to three enable inputs are available: EN1 is a dedicated enable input and EN2, EN3 are multiplexed with I2C interface. The buck converter is selected for sequence control with:

• BUCKx_CTRL_1(BUCKx_EN) = 1

• BUCKx_CTRL_1(BUCKx_EN_PIN_CTRL) = 0x1 or 0x2 or 0x3, for EN1 or EN2 or EN3 control, respectively

• BUCKx_VOUT.(BUCKx_VSET[7:0]) = Required voltage when EN pin is high

• The delay from rising edge of EN pin to the converter enable is set by BUCKx_DELAY(BUCKx_STARTUP_DELAY[3:0]) bits and

• The delay from falling edge of EN pin to the converter disable is set by BUCKx_DELAY(BUCKx_SHUTDOWN_DELAY[3:0])

In the same way the boost converter is selected for delayed control with:

• BOOST_CTRL(BOOST_EN) = 1

• BOOST_CTRL(BOOST_EN_PIN_CTRL) = 0x1 or 0x2 or 0x3, for EN1 or EN2 or EN3 control, respectively

• BOOST_CTRL(BOOST_VSET[2:0]) = Required voltage when EN pin is high

• The delay from rising edge of EN pin to the converter enable is set by BOOST_DELAY(BOOST_STARTUP_DELAY[3:0]) bits and

• The delay from falling edge of EN pin to the converter disable is set by BOOST_DELAY(BOOST_SHUTDOWN_DELAY[3:0])

Figure 12. Buck Output Voltage Change

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ENx

Internal

ENx

1 ms

3 ms

Internal

1 ms

4 ms

3 ms

1 ms

4 ms

Typical sequence

Sequence with short EN low and high periods

Startup cntr

Shutdown cntr

0 0 1

0 1 2 3 4 5 6 0

0 1 2 0 1 2 3 4 5

Internal

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An example of start-up and shutdown sequences for buck converters are shown in Figure 13. The start-up and shutdown delays for Buck0 converter are 1 ms and 4 ms and for Buck1 converter 3 ms and 1 ms. The delay settings are used only for enable/disable control with EN signal.

Figure 13. Start-up and Shutdown Sequencing Example

7.3.8 Window Watchdog

Operation of the LP87702-Q1 watchdog is shown in Figure 14 for an example when ENx pin is used for controlling power sequence and ENx pin is active.

WDI is the watchdog function input pin and WD_RESET is the reset output . WDI pin needs to be pulsed within a certain timing window to avoid watchdog expiration. Minimum pulse width is 100 µs. Watchdog expiration always causes a reset pulse at WD_RESET output, otherwise device behavior after watchdog expiration is programmable. WD_RESET output polarity and mode, push-pull or open drain, are also programmable.

Watchdog default settings are read from OTP during device start-up. Default settings in WD_CTRL_1 and WD_CTRL_2 register can be over-written via I2C (as long as WD_LOCK bit is not set to 1). Writing WD_LOCK = 1 in WD_CTRL_2 register locks watchdog settings until NRST input is driven low, power cycle or register reset by SW_RESET.

Long open, close and open window periods are independently programmable as shown in Table 4. When long open or open window expires before WDI input is received, watchdog enters WD Reset state. Also when WDI is received during close window, watchdog enters WD Reset. Long open period can be extended by a I2C write to WD_CTRL_1 or WD_CTRL_2 register; register access initializes the long open counter and the long open period restarts (except in Stop mode).

LP87702-Q1 behavior after WD expiration is programmable :

• When WD_RESET_CNTR_SEL = 00, system restart is disabled and converters are maintained ON. WD_RESET pin is active for 10 ms. Watchdog returns to Long Open mode.

• When WD_RESET_CNTR_SEL = 01 (restart after first reset pulse), LP87702-Q1 performs shutdown

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LP87702-Q1

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sequence followed by start-up sequence so the converters are disabled and re-enabled according to the OTP programmed sequences. During start-up, device reloads OTP defaults when WD_EN_OTP_READ = 1. Settings valid before shutdown are maintained when WD_EN_OTP_READ = 0. WD_RESET output pin is active for a period of (10 ms + maximum shutdown delay). Maximum shutdown delay can be selected as 7.5 ms (SHUTDOWN_DELAY_SEL = 0) or 15 ms (SHUTDOWN_DELAY_SEL = 1). After the restart watchdog returns to Long Open mode.

• Status bit WD_SYSTEM_RESTART_FLAG is set to indicate that system restart has happened. Status can be cleared by writing "1" to WD_CLR_SYSTEM_RESTART_FLAG. WD_RESET_CNTR_SEL can be set to 10 or 11 to select restart after 2 or 4 WD expirations, respectively. Current status of reset counter is available in WD_RESET_CNTR_STATUS. Reset counter can be cleared by writing WD_CLR_RESET_CNTR to 1.

• Watchdog can also be programmed to perform shutdown sequence and enter STOP mode after the first WD expiration. In STOP mode converters are OFF. WD_RESET output pin is activated for a period of (10 ms + maximum shutdown delay), in STOP mode WD_RESET is inactive. NRST, power cycle, register reset SW_RESET, writing WD_CLR_SYSTEM_RESTART_FLAG = 1 or writing WD_SYSTEM_RESTART_FLAG_MODE = 0 is required to recover. This WD operating mode is selected by setting OTP bit WD_SYS_RESTART_FLAG_MODE = 1.

Watchdog settings in WD_CTRL_1 and WD_CTRL_2 registers are locked by setting WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK = 1.

Description above is for a case where ENx pin is used for controlling power sequence and ENx pin is active. Depending on OTP settings and ENx pin state watchdog behavior can be slightly different:

• When ENx pin is used for controlling power sequence and ENx pin is not active, shutdown sequence can not be performed. WD_RESET pulse length is fixed 31 ms.

• When ENx pins are not used for power sequence control and all converters and GPOs enabled via I2C, there is no OTP defined power sequence. WD expiration does not cause converter disable/enable sequence even when OTP settings for watchdog are such that restart is enabled. In this case WD_RESET pulse is 11 ms.

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Long Open

Open

WD Reset

Increase Reset Counter value,

WDI Rising

CloseTime Expired

WDI Rising

LongOpenTime Expired

OpenTime Expired

Shutdown Sequence

WD_RESET output

active for (7.5ms +10ms)

or (15ms+10ms)

Read OTP

Stop

WD_EN_OTP_READ = 0

WD_EN_OTP_READ = 1

WD_SYS_RESTART_FLAG_MODE = 1

Restart Disabled OR

Reset Counter < Counter Select

Restart Enabled AND

Reset Counter >= Counter Select

(from all states except Stop)

Release ENx

pin gating

Shutdown

NRST low OR

VANA < VANA_UVLO

NRST high AND

VANA > VANA_UVLO

(WD_SYSTEM_RESTART_FLAG = 0

WD_SYSTEM_RESTART_FLAG_MODE = 0)

AND

WD_EN_OTP_READ = 1

(WD_SYSTEM_RESTART_FLAG = 0

WD_SYSTEM_RESTART_FLAG_MODE = 0)

AND

WD_EN_OTP_READ = 0

WD_RESET output

active for 10ms

Set

WD_SYSTEM_

RESTART_FLAG = 1

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Figure 14. Watchdog Operation

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Table 4. Watchdog Window Periods

CONTROL BIT DEFAULT VALUES

00 - 200 ms

WD_LONG_OPEN_TIME OTP

WD_CLOSE_TIME OTP

WD_OPEN_TIME OTP

01 - 600 ms 10 - 2000 ms 11 - 5000 ms

00 - 10 ms 01 - 20 ms 10 - 50 ms

11 - 100 ms

00 - 20 ms 01 - 100 ms 10 - 200 ms 11 - 600 ms

LP87702-Q1 supports option to disable watchdog. WD_DIS pin function is multiplexed with CLKIN/GPIO2 functions. Watchdog disable option can be selected by setting register bit WD_DIS_CTRL = 1. When WD_DIS_CTRL = 1, WD is disabled if CLKIN/GPIO2/WD_DIS pin is HIGH and enabled if CLKIN/GPIO2/WD_DIS pin is LOW. If WD_DIS_CTRL is toggled to disable and re-enable WD, WD starts from Long Open window after re-enabling.

Default for WD_DIS_CTRL is set in OTP. WD_DIS_CTRL value can be changed via I2C until WD settings are locked. When WD_LOCK is set to 1, WD is enabled regardless of WD_DIS_CTRL value. WD_DIS_CTRL bit is protected by write lock. Three consecutive codes have to be written to WD_DIS_UNLOCK_CODE to open WD_DIS_CTRL for write access.

7.3.9 Device Reset Scenarios

There are four reset methods implemented on the LP87702-Q1:

• Software reset with SW_RESET bit in RESET register

• NRST input signal low

• Undervoltage lockout (UVLO) reset from VANA supply

• Watchdog expiration (depending on watchdog settings) A SW reset occurs when SW_RESET bit is set to 1. The bit is automatically cleared after writing. This event

disables all the converters immediately, drives GPO signals low, resets all the register bits to the default values and OTP bits are loaded (see Figure 20). I2C interface is not reset during software reset. The host must wait at least 1.2 ms after writing SW reset until making a new I2C read or write to the device.

If VANA supply voltage falls below UVLO threshold level or NRST signal is set low then all the converters are disabled immediately, GPOx signals are driven low and all the register bits are reset to the default values. When the VANA supply voltage rises above UVLO threshold level and NRST signal rises above threshold level, OTP bits are loaded to the registers and a start-up is initiated according to the register settings. The host must wait at least 1.2 ms before reading or writing to I2C interface.

Depending on watchdog settings, watchdog expiration can reset the device to OTP default values.

7.3.10 Diagnostics and Protection Features

The LP87702-Q1 provides four levels of protection features:

• Information of input and output voltages. Non-valid voltage sets interrupt or PGx signal – Validity of the output voltage of BUCK or BOOST converters – Validity of VANA, VMON1 and VMON2 input voltages

• Warnings causing interrupt – Peak current limit detection in BUCK or BOOST converters – Thermal warning

• Protection events which are disabling the converters – Short-circuit and overload protection for BUCK and BOOST converters – Input overvoltage protection (VANA

OVP

)

– Watchdog expiration (optional, depends on watchdog settings)

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– Thermal shutdown

• Protection events which are causing the device to shutdown – Undervoltage lockout (VANA

UVLO

)

• Protections not causing interrupt or converter disable – Negative current limit detection in BUCK or BOOST converters

7.3.10.1 Voltage Monitorings

The LP87702-Q1 device has programmable voltage monitoring for the BUCKx and BOOST converter output voltages and for VANA, VMON1 and VMON2 inputs. Monitoring of each signal is independently enabled in PGOOD_CTRL register. Voltage monitoring can be under-voltage monitoring only (PGOOD_WINDOW = 0) or overvoltage and undervoltage monitoring (PGOOD_WINDOW = 1). This selection is common for all enabled monitorings. Enabled monitoring signals are combined to generate power-good (PG0, PG1) and/or interrupts as described in Power-Good Information to Interrupt and PG0 and PG1 Pins. Monitoring comparators have a dedicated reference and bias block, which is independent of the main reference and bias block.

Nominal level for the output voltage of BUCKx converter is set with BUCKx_VSET in BUCKx_VOUT register. Overvoltage and undervoltage detection levels, with respect to nominal level, are selected with BUCKx_WINDOW as ± 30 mV, ± 50 mV, ± 70 mV or ± 90 mV. Nominal level for the output voltage of BOOST converter is set with BOOST_VSET in BOOST_CTRL register. Available levels are 4.9 V, 5 V, 5.1 V and 5.2 V. Overvoltage and undervoltage detection levels, with respect to nominal level, are selected with BOOST_WINDOW as ± 2%, ± 4%, ± 6% or ± 8%. Converter monitoring window selection bits are in PGOOD_LEVEL_3 register.

Input voltage of LP87702-Q1 is monitored at VANA pin. Nominal level can be selected as 3.3 V or 5 V with VANA_THRESHOLD bit. Overvoltage and undervoltage detection levels are selected with VANA_WINDOW as ± 4%, ± 5% or ± 10% (nominal). VANA_THRESHOLD and VANA_WINDOW are set in PGOOD_LEVEL_2 register.

VMON1 and VMON2 inputs can be used for monitoring external rails in the system. VMONx settings are defined in PGOOD_LEVEL_1 and PGOOD_LEVEL_2 registers. Nominal value for the input level of VMONx is selected with VMONx_THRESHOLD, between 0.65 V to 1.8 V. Higher voltage levels or levels not directly supported can be monitored using an external resistor divider. In this case VMONx_THRESHOLD must be set as 0.65V to have high-impedance input and the resistor divider must scale the monitored level down to 0.65 V at VMONx pin. Overvoltage and undervoltage detection levels are selected with VMONx_WINDOW as ± 2%, ± 3%, ± 4% or ± 6%.

For more details on the accuracy of the monitoring windows and deglitch filtering see Specifications.

7.3.10.2 Interrupts

The LP87702-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT output pin is driven high after all flag bits and pending interrupts are cleared.

Fault detection is indicated by RESET_REG_INT interrupt flag bit set in INT_TOP_2 register after start-up event.

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Table 5. Summary of Interrupt Signals

EVENT SAFE STATE INTERRUPT BIT INTERRUPT MASK STATUS BIT RECOVERY/INTERRUPT

Buck current limit triggered (20-µs debounce)

Boost current limit triggered

Buck short circuit (V

< 0.35V at 1 ms

VOUT

after enable) or Overload (V decreasing below 0.35 V during operation, 1 ms debounce)

Boost short circuit Converter disable BOOST_INT = 1

Thermal warning No effect TDIE_WARN_INT) = 1 TDIE_WARN_MASK TDIE_WARN_STAT Write 1 to TDIE_WARN_INT bit

Thermal shutdown All converters disabled

VANA overvoltage (VANA

Buck power-good, output voltage becomes valid

Buck power-good, output voltage becomes invalid

Boost power-good, output voltage becomes valid

Boost power-good, output voltage becomes invalid

VMON1 power-good, input voltage becomes valid

VMON1 power-good, input voltage becomes invalid

VMON2 power-good, input voltage becomes valid

VMON2 power-good, input voltage becomes invalid

VANA power-good, input voltage becomes valid

VANA power-good, input voltage becomes invalid

External clock appears or disappears

Load current measurement ready

Supply voltage VANA (VANA falling)

Supply voltage VANA (VANA rising)

Software requested reset

OVP

UVLO

VOUT

)

triggered

No effect BUCK_INT = 1

No effect BOOST_INT = 1

Converter disable BUCKx_INT = 1

immediately and GPOx set to low

All converters disabled immediately and GPOx set to low

No effect BUCK_INT = 1

No effect BOOST_INT = 1

No effect DIAG_INT = 1

No effect to converters SYNC_CLK_INT

No effect I_MEAS_INT = 1 I_MEAS_MASK N/A Write 1 to I_MEAS_INT bit

Immediate shutdown, registers reset to default values

Start-up, registers reset to default values and OTP bits loaded

Immediate shutdown followed by powerup, registers reset to default values

BUCKx_ILIM_INT = 1

BOOST_ILIM_INT = 1

BUCKx_SC_INT = 1

BOOST_SC_INT = 1

TDIE_SD_INT = 1 N/A TDIE_SD_STAT Write 1 to TDIE_SD_INT bit

OVP_INT N/A OVP_STAT Write 1 to OVP_INT bit

BUCKx_PG_INT = 1

BOOST_PG_INT = 1

VMON1_PG_INT = 1

VMON2_PG_INT = 1

VANA_PG_INT = 1

(1)

N/A N/A N/A N/A

RESET_REG_INT = 1 RESET_REG_MASK N/A Write 1 to RESET_REG_INT

BUCKx_ILIM_MASK BUCKx_ILIM_STAT Write 1 to BUCKx_ILIM_INT bit

BOOST_ILIM_MASK BOOST_ILIM_STAT Write 1 to BOOST_ILIM_INT

N/A N/A Write 1 to BUCKx_SC_INT bit

N/A N/A Write 1 to BOOST_SC_INT bit

BUCKx_PGR_MASK BUCKx_PG_STAT Write 1 to BUCKx_PG_INT bit

BUCKx_PGF_MASK BUCKx_PG_STAT Write 1 to BUCKx_PG_INT bit

BOOST_PGR_MASK BOOST_PG_STAT Write 1 to BOOST_PG_INT bit

BOOST_PGF_MASK BOOST_PG_STAT Write 1 to BOOST_PG_INT bit

VMON1_PGR_MASK VMON1_PG_STAT Write 1 to VMON1_PG_INT bit

VMON1_PGF_MASK VMON1_PG_STAT Write 1 to VMON1_PG_INT bit

VMON2_PGR_MASK VMON2_PG_STAT Write 1 to VMON2_PG_INT bit

VMON2_PGF_MASK VMON2_PG_STAT Write 1 to VMON2_PG_INT bit

VANA_PGR_MASK VANA_PG_STAT Write 1 to VANA_PG_INT bit

VANA_PGF_MASK VANA_PG_STAT Write 1 to VANA_PG_INT bit

SYNC_CLK_MASK SYNC_CLK_STAT Write 1 to SYNC_CLK_INT bit

Interrupt is not cleared if current limit is active

bit Interrupt is not cleared if current limit is active

Interrupt is not cleared if temperature is above thermal warning level

Interrupt is not cleared if temperature is above thermal shutdown level

Interrupt is not cleared if VANA voltage is above VANA

bit

(1) Interrupt generated during Clock Detector operation and in case Clock is not available when Clock Detector is enabled.

CLEAR

OVP

level

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7.3.10.3 Power-Good Information to Interrupt and PG0 and PG1 Pins

LP87702-Q1 supports both interrupt based indication of power-good levels for various voltage settings and using two power-good signals, PG0 and PG1. The selection of monitored signals is independent for the interrupt (nINT) and PG0, PG1 signals. Each signal can include:

• The output voltage of one or both BUCKx converters

• The output voltage of the BOOST converter

• Input voltage of VANA

• Input voltage of VMON1 and/or VMON2

• Thermal warning

The block diagram for power-good connections to PG0 and PG1 pins and interrupt is shown in Figure 15. Monitored signals are enabled in PGOOD_CTRL register. Converter output voltage monitoring (not current limit

monitoring) can be selected for the indication. Monitoring is enabled by EN_PGOOD_BUCKx and EN_PGOOD_BOOST bits. When a converter is disabled, the monitoring is automatically masked to prevent it forcing PGx inactive or causing an interrupt. Also monitoring of VANA, VMON1 and VMON2 inputs can be independently enabled via PGOOD_CTRL register. The type of voltage monitoring for PGx signals and nINT is selected by PGOOD_WINDOW bit. If the bit is 0, only undervoltage is monitored and if the bit is 1 both undervoltage and overvoltage are monitored. For voltage monitoring thresholds see Voltage Monitorings. .

Monitoring interrupts from all the output rails, input rails and thermal warning are combined to nINT pin. Dedicated mask bits are used to select which interrupts control the state of nINT pin. See Table 5 for summary of interrupts, mask bits and interrupt clearing.

Similarly, enabled monitoring signals from all the output rails, input rails and thermal warning are combined to PG0 and PG1 output pins. Register bits SEL_PGx_x in PG0_CTRL and PG1_CTRL select which of the signals control the state of PG0 and PG1, respectively. The polarity and the output type (push-pull or open-drain) of PG0 and PG1 are selected by PGx_POL and PGx_OD bits in PG_CTRL register.

PGx is only active or asserted when all monitored input voltages and all output voltages of monitored and enabled converters are within specified tolerance of set target value.

PGx is inactive or de-asserted if any of the monitored input voltages or output voltages of monitored and enabled converters are outside specified tolerance of set target value.

When PGx_RISE_DELAY = 1, PGx is set as active or asserted with 11 ms delay from the point of time where all enabled power resource output voltages are within specified tolerance for each requested/programmed output voltage.

Thermal shutdown and VANA overvoltage protection events force PGx to default state (assuming PGx polarity set in OTP is active high, PGx are drive low).

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PG1 CONTROL

Mask

Falling

Status

INT

Mask

Rising

PG0

PG1/GPO1

Mask

Status

INT

Mask

Falling

Status

INT

Mask

Rising

Mask

Falling

Status

INT

Mask

Rising

Mask

Falling

Status

INT

Mask

Rising

Mask

Falling

Status

INT

Mask

Rising

Mask

Falling

Status

INT

Mask

Rising

nINT

Boost

Powergood

Buck0

Powergood

Buck1

Powergood

VANA

Powergood

Thermal

Warn

VMON1

Powergood

VMON2

Powergood

SEL_PG0_VMON1

SEL_PG0_VANA

SEL_PG0_BUCK1

SEL_PG0_BUCK0

SEL_PG0_BOOST

SEL_PG0_VMON2

GPO1

VANA

VMON1

VMON2

PP/OD

Polarity

PP/OD

EN_PGOOD_BOOST

EN_PGOOD_BUCK0

EN_PGOOD_BUCK1

EN_PGOOD_VANA

EN_PGOOD_VMON1

EN_PGOOD_VMON2

GPO1_SEL

SEL_PG0_TWARN

PG0 CONTROL

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Figure 15. Block Diagram of Power-Good Connections

LP87702-Q1 power-good detection has two operating modes, selected in OTP: gated (that is, unusual) or continuous (that is, invalid) mode of operation. These modes are described in PGx Pin Gated (Unusual) Mode and in PGx pin Operation in Continuous Mode.

7.3.10.3.1 PGx Pin Gated (Unusual) Mode

In this mode the PGx signal detects unexpected or unusual situations. Mode is selected by setting PGx_MODE bit to 0 in PG_CTRL register.

For the gated mode of operation, PGx behaves as follows:

• PGx is set to active or asserted state upon exiting OTP configuration as an initial default state.

• For each enabled rail PGx status is active or asserted during an 800-μs gated time period from the enable activation, thereby gating-off the status indication.

• During normal power-up sequencing and requested voltage changes, PGx state typically remains active or asserted for normal conditions.

• During an abnormal power-up sequencing and requested voltage changes, PGx status could change to inactive or de-asserted after an 800-μs gated time period if any output voltage is outside of regulation range.

• Using the gated mode of operation could allow the PGx signal to initiate an immediate power shutdown sequence if the PGx signal is wired-OR with signal connected to EN input. This type of circuit configuration provides a smart PORz function for processor that eliminates the need for additional components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.

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(VANA)

VANA_UVLO

State

Shut

down

Read

OTP

Standby

PGx pin

VOUT (Buck1)

VOUT (Boost)

Powergood (Boost)

Active

800us Timer

EN (Buck1)

800us Timer

EN (Boost)

4ms

2ms

Clear fault

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PGx signal is set inactive if the output voltage of a monitored buck or boost converter is invalid or the output voltage is not valid at 800 µs from the enable of the converter. This should be considered when selecting the BUCKx_SLEW_RATE setting. To avoid PGx triggering at start-up keep the sum of soft start time and slew rate controlled part of voltage ramp below 800 µs. In addition when invalid input voltage at VANA, VMON1 or VMON2 pin is detected PGx is inactive.

Detected fault sets the corresponding fault bit in PG0_FAULT or in PG1_FAULT register. The detected fault must be cleared to continue the PGx monitoring. The over-voltage and thermal faults are cleared by writing 1 to the corresponding interrupt bits in INT_TOP_1 register. Converter, VMONx and VANA faults are cleared by writing 1 to the corresponding register bit in INT_BUCK, INT_BOOST and INT_DIAG register, respectively. An example of PGx pin operation in gated mode is shown in Figure 16 and the different use cases for PGx signal operation are summarized in Table 6.

7.3.10.3.2 PGx pin Operation in Continuous Mode

In this mode the PGx signal shows the validity of the requested voltages continuously. Mode is selected by setting PGx_MODE bit to 1 in PG_CTRL register.

For the continuous mode of operation, PGx behaves as follows:

• PGx is set to active or asserted state upon exiting OTP configuration as an initial default state.

• PGx is set to inactive or de-asserted as soon as converter is enabled.

• PGx status begins indicating output voltage regulation status immediately and continuously.

• During power-up sequencing and requested voltage changes, PGx will toggle between inactive or deasserted while output voltages are outside of regulation ranges and active or asserted when inside of regulation ranges.

When invalid output voltage of monitored converter is detected, corresponding bit in PG0_FAULT or PG1_FAULT register is set to 1 and PGx signal becomes inactive. The PG0_FAULT and PG1_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing 1 to the bit. The PGx signal indicates also interrupts from VANA, VMON1 and VMON2 inputs and thermal warning and shutdown. All are cleared by clearing the interrupt bits.

Figure 16. PGx Pin Operation in Gated Mode.

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(VANA)

VANA_UVLO

State

Shut

down

Read

OTP

Standby

PGx pin

VOUT (Buck1)

VOUT (Boost)

Powergood (Boost)

Active

EN (Buck1)

EN (Boost)

4ms

2ms

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When converter voltage is transitioning from one target voltage to another, the PGx signal is set inactive. When PGx signal becomes inactive, the source for the fault can be read from PGx_FAULT register. If the invalid

output voltage becomes valid again the PGx signal becomes active. Thus the PGx signal shows all the time if the monitored output voltages are valid. An example of PGx pin operation in continuous mode is shown in Figure 17.

The PGx signal can be also configured so that it maintains inactive state even when the monitored outputs are valid but there are PG_FAULT_x bits pending clearance. This type of operation is selected by setting PGOOD_FAULT_GATES_PGx bit to 1.

7.3.10.3.3 Summary of PG0, PG1 Gated and Continuous Operating Modes

Table 6 summarizes the PGx behavior in different application scenarios, for the gated and continuous operating

modes.

Figure 17. PGx Pin Operation in Continuous Mode

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Table 6. PGx Operation

PGx SIGNAL

STATUS / USE CASE CONDITION

Device start-up Until device state is STANDBY Low Low Converter not selected for PGx

monitoring Converter selected for PGx

monitoring and disabled by host Converter start-up delay ongoing EN = 1 OK NOK Converter start-up until valid

output voltage reached Converter start-up until valid

output voltage reached Output voltage within window

limits after start-up Output voltage spikes

(over/undervoltage)

Voltage setting change, output voltage ramp

Output voltage within window limits after voltage change

Converter shutdown delay ongoing

Buck converter disabled by host, slew-rate controlled ramp down ongoing

Converter disabled by host, pulldown resistor active (if selected)

Converter short-circuit interrupt pending (converter selected for PGx monitoring)

Thermal shutdown interrupt pending

Input (VANA) overvoltage interrupt pending

Supply voltage below VANA

(1) NOK (Not OK) means faulty situation. PGx pin is inactive if at least one NOK situation is detected. (2) PGx pin is generated from PG_FAULT register bits and INT_TOP_1 register bits TDIE_SD_INT, OVP_INT and

INT_TOP_2(RESET_REG_INT) bit.

BUCKx_SC_INT / BOOST_SC_INT =

UVLO

EN_PGOOD_x = 0 OK OK

BUCKx_EN / BOOST_EN = 0 OR

(Pin ctrl AND EN = 0)

Valid output voltage reached in 800

µs

Valid output voltage not reached at

800 µs

Must be inside limits longer than

debounce time

If spikes are outside voltage

monitoring threshold(s) longer than

debounce time

OK (if new voltage reached in 800

NOK after 800 µs (if new voltage

Must be inside limits longer than

debounce time

Faulty converter disabled by short-

circuit detection

Converters disabled by thermal

shutdown detection

TDIE_SD_INT = 1

Converters disabled by overvoltage

detection

OVP_INT = 1

GATED MODE

PGx_MODE = 0

OK OK

OK NOK

NOK NOK

OK OK

NOK NOK

µs)

not reached at 800 µs)

OK OK

NOK NOK

Low Low

(1)(2)

CONTINUOUS MODE

PGx_MODE = 1

NOK

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7.3.10.4 Warning Interrupts for System Level Diagnostics

7.3.10.4.1 Output Power Limit

The buck converters have programmable output peak current limits. The limits are individually programmed for both converters with BUCKx_ILIM[2:0] bits. If the load current is increased so that the current limit is triggered, the converter continues to regulate to the limit current level (current peak regulation). The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 20 µs, the LP87702-Q1 device sets the BUCKx_ILIM_INT bit and pulls the nINT pin low. The host processor can read BUCKx_ILIM_STAT bits to see if the converter is still in peak current regulation mode. During startup or output voltage ramp (output voltage change has been programmed) no interrupt is generated.

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Time

Voltage

VOUTx

350 mV

Time

Current

ILIMx

20 µs

nINT

BUCK_STAT(BUCKx_STAT)

Resistive

pull-down

Regulator disabled by

digital

Host clearing the interrupt by writing to flags

New startup if

enable is valid

1 ms

010

INT_BUCK(BUCKx_SC_INT)

010

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If the load is so high that the output voltage decreases below a 350-mV level, the LP87702-Q1 device disables the converter and sets the BUCKx_SC_INT bit. The interrupt is cleared when the host processor writes 1 to BUCKx_SC_INT bit. The Buck overload situation is shown in Figure 18.

The boost converter has programmable output peak current limits. The limits are set with BOOST_ILIM bits. If the load current is increased so that the current limit is triggered, the converter continues to regulate to the limit current level (current peak regulation). The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 64 µs, the LP87702-Q1 device sets the BOOST_ILIM_INT bit and pulls the nINT pin low. The host processor can read BOOST_ILIM_STAT bits to see if the converter is still in peak current regulation mode.

If the load is so high that the output voltage decreases 150mV (typical) below input voltage level converter is disabled after 1 ms. If the output voltage decreases to 2.5 V, boost stops switching. After 1 ms deglitch time boost is fully disabled and interrupt BOOST_SC_INT bit is set. The interrupt is cleared when the host processor writes 1 to BOOST_SC_INT bit. The Boost overload situation is shown in Figure 19.

Figure 18. Buck Overload Situation

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Time

Voltage

VOUTx

2.5 V

Time

Current

ILIMx

Ps

nINT

BOOST_STAT(BOOST_STAT)

Resistive

pull-down

Converter disabled

by digital

Host clearing the interrupt by writing to flags

New startup if

enable is valid

1ms

010

INT_BOOST(BOOST_SC_INT)

010

VIN

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The buck converters have a fixed current limit for negative output peak current (I current increases it is limited below I Operation of the negative peak current limit of the boost converter is similar and limit value is 1.4 A (typical).

7.3.10.4.2 Thermal Warning

The LP87702-Q1 device includes a protection feature against over-temperature by setting an interrupt for host processor. The threshold level of the thermal warning is selected with TDIE_WARN_LEVEL bit.

If the LP87702-Q1 device temperature increases above thermal warning level the device sets TDIE_WARN_INT bit and pulls nINT pin low. The status of the thermal warning can be read from TDIE_WARN_STAT bit and the interrupt is cleared by writing 1 to TDIE_WARN_INT bit. The thermal warning interrupt can be masked by setting TDIE_WARN_MASK bit to 1.

7.3.10.5 Protections Causing Converter Disable

If the converter is disabled because of protection or fault (short-circuit protection, thermal shutdown, overvoltage protection, or undervoltage lockout), the output power FETs are set to high-impedance mode, and the output pulldown resistor is enabled (if enabled with BUCKx_RDIS_EN and BOOST_RDIS_EN bits). The turnoff time of the output voltage is defined by the output capacitance, load current, and the resistance of the integrated pulldown resistor. The pulldown resistors are active as long as VANA voltage is above approximately 1.2-V level.

7.3.10.5.1 Short-Circuit and Overload Protection

A short-circuit protection feature allows the LP87702-Q1 to protect itself and external components against short circuit at the output or against overload during start-up. During start-up, short-circuit at buck converter output is detected when the output voltage is below 350mV (typical) 1 ms after the buck converter is enabled. For boost the fault threshold is 150mV (typical) below input voltage level. Boost converter is disabled if the output voltage is below the threshold level 1 ms after the boost converter is enabled.

Figure 19. Boost Overload Situation

). When negative coil

LIM_NEG

, converter continues to operate and no interrupt is generated.

LIM_NEG

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In a similar way the overload situation is protected during normal operation. If the feedback-pin voltage of the buck converter falls below 0.35 V and remains below the threshold level for 1 ms the buck converter is disabled. If the output voltage of the boost converter decreases 150 mV below input voltage level, converter is disabled after 1 ms. If the output voltage decreases to 2.5 V, boost is disabled immediately.

In the Buck converter short-circuit and overload situations the BUCKx_SC_INT and the BUCK_INT bits are set to 1, the BUCKx_STAT bit is set to 0 and the nINT signal is pulled low. In the boost converter short-circuit and overload situations the BOOST_SC_INT and the BOOST_INT bits are set to 1, the BOOST_STAT bit is set to 0 and the nINT signal is pulled low. The host processor clears the interrupt by writing 1 to the BUCKx_SC_INT or BOOST_SC_INT bit. Upon clearing the interrupt the converter makes a new start-up attempt if the converter is in enabled state.

7.3.10.5.2 Overvoltage Protection

The LP87702-Q1 device monitors the input voltage from VANA pin in standby and active operation modes. If the input voltage rises above VANA

voltage level, all the converters are disabled immediately (without switching

OVP

ramp, no shutdown delays), pulldown resistors discharge the output voltages (BUCKx_RDIS_EN = 1 and BOOST_RDIS_EN = 1), GPOs are set to logic low level, nINT signal is pulled low, OVP_INT bit is set to 1 and BUCKx_STAT and BOOST_STAT bits are set to 0. The host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above over-voltage detection level the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit. Converters cannot be enabled as long as the input voltage is above over-voltage detection level or the overvoltage interrupt is pending.

7.3.10.5.3 Thermal Shutdown

The LP87702-Q1 has an overtemperature protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the converters are disabled immediately (without switching ramp, no shutdown delays), the TDIE_SD_INT bit is set to 1, the nINT signal is pulled low, and the device enters STANDBY. nINT is cleared by writing 1 to the TDIE_SD_INT bit. If the temperature is above thermal shutdown level the interrupt is not cleared. The host can read the status of the thermal shutdown from the TDIE_SD_STAT bit. Converters cannot be enabled as long as the junction temperature is above thermal shutdown level or the thermal shutdown interrupt is pending.

7.3.10.6 Protections Causing Device Power Down

7.3.10.6.1 Undervoltage Lockout

When the input voltage falls below VANA

at the VANA pin, the buck and boost converters are disabled

UVLO

immediately (without switching ramp, no shutdown delays), and the output capacitor is discharged using the pulldown resistor, and the LP87702-Q1 device enters SHUTDOWN. When V

voltage is above VANA

(VANA)

UVLO

threshold level, the device powers up to STANDBY state. If the reset interrupt is unmasked by default (RESET_REG_MASK = 0 in TOP_MASK_2 register) the

RESET_REG_INT interrupt in INT_TOP_2 register indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the RESET_REG_INT flag after detecting an nINT low signal, it knows that the input supply voltage has been below VANA

level (or the host has requested reset with RESET(SW_RESET) bit), and the registers are reset to

UVLO

default values.

7.3.11 OTP Error Correction

LP87702-Q1 supports OTP bit error detection and 1-bit error correction per five registers. ECC_STATUS register bit SED is set if a single bit error was detected and corrected. In case two bit errors have been detected in any bank of five registers, DED bit is set.

7.3.12 Operation of GPO Signals

The LP87702-Q1 device supports up to 3 general purpose output (GPO) signals. The GPO1 signal is multiplexed with PG1 signal and the GPO2 signal is multiplexed with CLKIN and WD_DIS signals. The selection between signal use are set with GPO1_SEL and GPO2_SEL bits in GPO_CONTROL_2 register.

The type of the output, either push-pull with V

(VANA)

level or open drain, are set with GPO0_OD and

GPO1_PG1_OD bits in GPO_CONTROL_1 register and GPO2_OD bit in GPO_CONTROL_2 register

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The logic level of the GPOx pins are is set by GPO0_OUT and GPO1_OUT bits in GPO_CONTROL_1 register and GPO2_OUT bit in GPO_CONTROL_2 register.

The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence with ENx pin is selected by GPOx_EN_PIN_CTRL bits. The delays during start-up and shutdown are set by bits in GPOx_DELAY registers.

7.3.13 Digital Signal Filtering

The digital signals have a debounce filtering. The signal/supply is sampled with a clock signal and a counter. This results as an accuracy of one clock period for the debounce window.

Table 7. Digital Signal Filtering

EVENT SIGNAL/SUPPLY

Enable/Disable for BUCKx, BOOST or GPOx

VANA undervoltage lockout VANA Immediate (VANA voltage rising) Immediate (VANA voltage falling) VANA overvoltage VANA 1 µs (VANA voltage rising) 1 µs (VANA voltage falling) Thermal warning TDIE_WARN_INT 20 µs 20 µs Thermal shutdown TDIE_SD_INT 20 µs 20 µs Current limit, BUCKx 20 µs 20 µs Current limit, BOOST 64 µs 64 µs Overload FB_B0, FB_B1, VOUT_BST 1 ms N/V PGx pin and power-good

interrupt (voltage monitoring) PGx pin and power-good

interrupt (voltage monitoring)

(1) No glitch filtering, only synchronization.

PG0, PG1 / FB_B0, FB_B1 6 µs 6 µs

PG0, PG1 / VOUT_BST, VANA, VMON1, VMON2

ENx 3 µs

RISING EDGE FALLING EDGE

LENGTH LENGTH

(1)

15 µs 15 µs

3 µs

(1)

7.4 Device Functional Modes

7.4.1 Modes of Operation

SHUTDOWN: The V

reference, control and bias circuitry of the LP87702-Q1 device are turned off.

READ OTP: The main supply voltage V

are disabled and the reference and bias circuitry of the LP87702-Q1 are enabled. The OTP bits are loaded to registers. I2C access is not allowed during OTP read. This applies also to watchdog (see

Window Watchdog.

STANDBY: The main supply voltage V

can be read or written by the host processor via the system serial interface. Watchdog is active and WDI input is expected to toggle to avoid watchdog expiration. The converters are disabled and the reference, control and bias circuitry of the LP87702-Q1 are enabled. The converters can be enabled if needed.

ACTIVE: The main supply voltage V

converter is enabled. All registers can be read or written by the host processor via the system serial interface. Watchdog is active and WDI input is expected to toggle to avoid watchdog expiration.

The operating modes and transitions between the modes are shown in Figure 20. For the window watchdog detailed operation see Window Watchdog.

voltage is below VANA

(VANA)

is above VANA

(VANA)

is above VANA

(VANA)

is above VANA

(VANA)

threshold level or NRST signal is low. All switch,

UVLO

level and NRST signal is high. The converters

UVLO

level and NRST signal is high. All registers

UVLO

level and NRST signal is high. At least one

UVLO

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SHUTDOWN

STANDBY

ACTIVE

CONVERTER

ENABLED

READ

OTP

REG

RESET

I2C RESET

FROM ANY STATE

NRST low OR

VANA

< VANA

UVLO

CONVERTER(S)

DISABLED

NRST high AND

VANA

> VANA

UVLO

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Device Functional Modes (continued)

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Figure 20. Device Operation Modes.

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START

Condition

STOP

Condition

data change allowed

data

valid

data change allowed

data valid

data change allowed

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7.5 Programming

7.5.1 I2C-Compatible Interface

The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the ICs connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines should each have a pull-up resistor placed somewhere on the line and remain HIGH even when the bus is idle. The LP87702-Q1 supports standard mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).

7.5.1.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when clock signal is LOW.

Figure 21. Data Validity Diagram

7.5.1.2 Start and Stop Conditions

The LP87702-Q1 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C master always generates the START and STOP conditions.

Figure 22. Start and Stop Sequences

The I2C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I2C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 23 shows the SDA and SCL signal timing for the I2C-Compatible Bus. See the Figure 1 for timing values.

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START MSB Chip Address LSB

ACK from slave

ACK from slave ACK from slave

SCL

START id = 0x60 W ACK address = 0x40 ACK ACKaddress 0x40 data STOP

W ACK MSB Register Address LSB ACK MSB Data LSB ACK STOP

LOW

rCL

HD;DAT

HIGH

fCL

SU;DAT

SU;STA

SU;STO

START

REPEATED

START

STOP

HD;STA

START

rDA

BUF

fDA

HD;STA

RS P

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Programming (continued)

Figure 23. I2C-Compatible Timing

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP87702-Q1 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP87702-Q1 generates an acknowledge after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

If the V LP87702-Q1 device does not drive SDA line. The ACK signal and data transfer to the master is disabled at that time.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1 indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.

Figure 24. Write Cycle (w = write; SDA = 0), id = Device Address = 60Hex for LP87702-Q1

NOTE

voltage is below VANA

(VANA)

threshold level during I2C communication the

UVLO

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Bit 7

MSB LSB

I2C Slave Address (chip address)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

R/W Bit 0

ACK from slave

START MSB Chip Address LSB

SCL

ACK from slave

MSB Register Address LSB

RS R MSB Data LSB STOP

ACK from slave NACK from masterREPEATED START Data from slave

SDA

START

id = 0x60 W

ACK

address = 0x3F

ACK

address 0x3F data

NACK

STOP

MSB Chip Address LSB

id = 0x60

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Programming (continued)

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

Figure 25. Read Cycle ( r = read; SDA = 1), id = Device Address = 60Hex for LP87702-Q1

7.5.1.4 I2C-Compatible Chip Address

The device address for the LP87702-Q1 is 0x60. After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data will be written. The third byte contains the data for the selected register.

A. Here device address is 1100000Bin = 60Hex.

7.5.1.5 Auto Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8bit word is sent to the LP87702-Q1, the internal address index counter will be incremented by one and the next register will be written. Table 8 below shows writing sequence to two consecutive registers. Note that auto increment feature does not work for read.

MASTER ACTION

LP87702Q1

START DEVICE

ADDRES S = 60H

Figure 26. Device Address

Table 8. Auto-Increment Example

WRITE REGISTE

ACK ACK ACK ACK

R ADDRES S

DATA DATA STOP

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7.6 Register Maps

7.6.1 Register Descriptions

The LP87702-Q1 is controlled by a set of registers through the system serial interface port. This register map describes the default values for bits which are not read from OTP memory. The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state. OTP values for each orderable part number are described in a separate technical reference manual TRM.

7.6.1.1 LP8770_map Registers

Table 9 lists the memory-mapped registers for the LP8770_map registers. All register offset addresses not listed

in Table 9 should be considered as reserved locations and the register contents should not be modified.

Table 9. LP8770_MAP Registers

Offset Acronym Register Name Section

0h DEV_REV DEV_REV Register (Offset =

1h OTP_CODE OTP_CODE Register (Offset

2h BUCK0_CTRL_1 BUCK0_CTRL_1 Register

3h BUCK0_CTRL_2 BUCK0_CTRL_2 Register

4h BUCK1_CTRL_1 BUCK1_CTRL_1 Register

5h BUCK1_CTRL_2 BUCK1_CTRL_2 Register

6h BUCK0_VOUT BUCK0_VOUT Register

7h BUCK1_VOUT BUCK1_VOUT Register

8h BOOST_CTRL BOOST_CTRL Register

9h BUCK0_DELAY BUCK0_DELAY Register

Ah BUCK1_DELAY BUCK1_DELAY Register

Bh BOOST_DELAY BOOST_DELAY Register

Ch GPO0_DELAY GPO0_DELAY Register

Dh GPO1_DELAY GPO1_DELAY Register

Eh GPO2_DELAY GPO2_DELAY Register

Fh GPO_CONTROL_1 GPO_CONTROL_1 Register

10h GPO_CONTROL_2 GPO_CONTROL_2 Register

11h CONFIG CONFIG Register (Offset =

12h PLL_CTRL PLL_CTRL Register (Offset =

13h PGOOD_CTRL PGOOD_CTRL Register

14h PGOOD_LEVEL_1 PGOOD_LEVEL_1 Register

0h) [reset = 0h]

= 1h) [reset = 0h]

(Offset = 2h) [reset = 8h]

(Offset = 3h) [reset = 1Ah]

(Offset = 4h) [reset = 8h]

(Offset = 5h) [reset = 1Ah]

(Offset = 6h) [reset = 0h]

(Offset = 7h) [reset = 0h]

(Offset = 8h) [reset = 8h]

(Offset = 9h) [reset = 0h]

(Offset = Ah) [reset = 0h]

(Offset = Bh) [reset = 0h]

(Offset = Ch) [reset = 0h]

(Offset = Dh) [reset = 0h]

(Offset = Eh) [reset = 0h]

(Offset = Fh) [reset = AAh]

(Offset = 10h) [reset = Ah]

11h) [reset = 3Ch]

12h) [reset = 2h]

(Offset = 13h) [reset = 0h]

(Offset = 14h) [reset = 0h]

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Table 9. LP8770_MAP Registers (continued)

Offset Acronym Register Name Section

15h PGOOD_LEVEL_2 PGOOD_LEVEL_2 Register

16h PGOOD_LEVEL_3 PGOOD_LEVEL_3 Register

17h PG_CTRL PG_CTRL Register (Offset =

18h PG0_CTRL PG0_CTRL Register (Offset

19h PG0_FAULT PG0_FAULT Register (Offset

1Ah PG1_CTRL PG1_CTRL Register (Offset

1Bh PG1_FAULT PG1_FAULT Register (Offset

1Ch WD_CTRL_1 WD_CTRL_1 Register

1Dh WD_CTRL_2 WD_CTRL_2 Register

1Eh WD_STATUS WD_STATUS Register

1Fh RESET RESET Register (Offset =

20h INT_TOP_1 INT_TOP_1 Register (Offset

21h INT_TOP_2 INT_TOP_2 Register (Offset

22h INT_BUCK INT_BUCK Register (Offset =

23h INT_BOOST INT_BOOST Register (Offset

24h INT_DIAG INT_DIAG Register (Offset =

25h TOP_STATUS TOP_STATUS Register

26h BUCK_STATUS BUCK_STATUS Register

27h BOOST_STATUS BOOST_STATUS Register

28h DIAG_STATUS DIAG_STATUS Register

29h TOP_MASK_1 TOP_MASK_1 Register

2Ah TOP_MASK_2 TOP_MASK_2 Register

2Bh BUCK_MASK BUCK_MASK Register

2Ch BOOST_MASK BOOST_MASK Register

2Dh DIAG_MASK DIAG_MASK Register (Offset

2Eh SEL_I_LOAD SEL_I_LOAD Register

2Fh I_LOAD_2 I_LOAD_2 Register (Offset =

30h I_LOAD_1 I_LOAD_1 Register (Offset =

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(Offset = 15h) [reset = 0h]

(Offset = 16h) [reset = 0h]

17h) [reset = 2h]

= 18h) [reset = 0h]

= 19h) [reset = 0h]

= 1Ah) [reset = 0h]

= 1Bh) [reset = 0h]

(Offset = 1Ch) [reset = 0h]

(Offset = 1Dh) [reset = 1h]

(Offset = 1Eh) [reset = 0h]

1Fh) [reset = 0h]

= 20h) [reset = 0h]

= 21h) [reset = 0h]

22h) [reset = 0h]

= 23h) [reset = 0h]

24h) [reset = 0h]

(Offset = 25h) [reset = 0h]

(Offset = 26h) [reset = 0h]

(Offset = 27h) [reset = 0h]

(Offset = 28h) [reset = 0h]

(Offset = 29h) [reset = 0h]

(Offset = 2Ah) [reset = 1h]

(Offset = 2Bh) [reset = 0h]

(Offset = 2Ch) [reset = 0h]

= 2Dh) [reset = 0h]

(Offset = 2Eh) [reset = 0h]

2Fh) [reset = 0h]

30h) [reset = 0h]

Product Folder Links: LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Table 9. LP8770_MAP Registers (continued)

Offset Acronym Register Name Section

31h FREQ_SEL FREQ_SEL Register (Offset

32h BOOST_ILIM_CTRL BOOST_ILIM_CTRL Register

33h ECC_STATUS ECC_STATUS Register

34h WD_DIS_CTRL_CODE WD_DIS_CTRL_CODE

35h WD_DIS_CONTROL WD_DIS_CONTROL

= 31h) [reset = 0h]

(Offset = 32h) [reset = 0h]

(Offset = 33h) [reset = 0h]

= 0h]

Complex bit access types are encoded to fit into small table cells. Table 10 shows the codes that are used for access types in this section.

Table 10. LP8770_map Access Type Codes

Access Type Code Description Read Type

R R Read

Write Type

W W Write

Reset or Default Value

-n Value after reset or the default

i,j,k,l,m,n When these variables are used in

y When this variable is used in a

value

a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.

7.6.1.1.1 DEV_REV Register (Offset = 0h) [reset = 0h]

DEV_REV is shown in Figure 27 and described in Table 11. Return to Summary Table.

Figure 27. DEV_REV Register

7 6 5 4 3 2 1 0

RESERVED DEVICE_ID RESERVED

R-0h R-0h R-0h

Table 11. DEV_REV Register Field Descriptions

Bit Field Type Reset Description

7-6 RESERVED R 0h 5-3 DEVICE_ID R 0h

Product Folder Links: LP87702-Q1

Device specific ID code. (Default from OTP memory)

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Table 11. DEV_REV Register Field Descriptions (continued)

Bit Field Type Reset Description

2-0 RESERVED R 0h Reserved

7.6.1.1.2 OTP_CODE Register (Offset = 1h) [reset = 0h]

OTP_CODE is shown in Figure 28 and described in Table 12. Return to Summary Table.

Figure 28. OTP_CODE Register

7 6 5 4 3 2 1 0

OTP_ID OTP_REV

R-0h R-0h

Table 12. OTP_CODE Register Field Descriptions

Bit Field Type Reset Description

7-2 OTP_ID R 0h

1-0 OTP_REV R 0h

Identification Code of the OTP EPROM. (Default from OTP memory)

Version number of the OTP ID. (Default from OTP memory)

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7.6.1.1.3 BUCK0_CTRL_1 Register (Offset = 2h) [reset = 8h]

BUCK0_CTRL_1 is shown in Figure 29 and described in Table 13. Return to Summary Table.

Figure 29. BUCK0_CTRL_1 Register

7 6 5 4 3 2 1 0

RESERVED RESERVED BUCK0_FPWM BUCK0_RDIS_

R/W-0h R-0h R/W-0h R/W-1h R/W-0h R/W-0h

BUCK0_EN_PIN_CTRL BUCK0_EN

Table 13. BUCK0_CTRL_1 Register Field Descriptions

Bit Field Type Reset Description

7-6 RESERVED R/W 0h

5 RESERVED R 0h Reserved 4 BUCK0_FPWM R/W 0h

3 BUCK0_RDIS_EN R/W 1h

2-1 BUCK0_EN_PIN_CTRL R/W 0h

Forces the BUCK0 converter to operate in PWM mode: 0 - Automatic transitions between PFM and PWM modes (AUTO

mode). 1 - Forced to PWM operation. (Default from OTP memory)

Enable output discharge resistor when BUCK0 is disabled: 0 - Discharge resistor disabled 1 - Discharge resistor enabled.

Enable/disable control for BUCK0: 0x0 - only BUCK0_EN bit controls BUCK0 0x1 - BUCK0_EN bit AND EN1 pin control BUCK0 0x2 - BUCK0_EN bit AND EN2 pin control BUCK0 0x3 - BUCK0_EN bit AND EN3 pin control BUCK0 (Default from OTP memory)

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Table 13. BUCK0_CTRL_1 Register Field Descriptions (continued)

Bit Field Type Reset Description

0 BUCK0_EN R/W 0h

Enable BUCK0 converter: 0 - BUCK0 converter is disabled 1 - BUCK0 converter is enabled. (Default from OTP memory)

7.6.1.1.4 BUCK0_CTRL_2 Register (Offset = 3h) [reset = 1Ah]

BUCK0_CTRL_2 is shown in Figure 30 and described in Table 14. Return to Summary Table.

Figure 30. BUCK0_CTRL_2 Register

7 6 5 4 3 2 1 0

RESERVED BUCK0_ILIM BUCK0_SLEW_RATE

R/W-0h R/W-3h R/W-2h

Table 14. BUCK0_CTRL_2 Register Field Descriptions

Bit Field Type Reset Description

7-6 RESERVED R/W 0h 5-3 BUCK0_ILIM R/W 3h

2-0 BUCK0_SLEW_RATE R/W 2h

Sets the switch peak current limit of BUCK0. Can be programmed at any time during operation:

0x0 - 1.5 A 0x1 - 2.0 A 0x2 - 2.5 A 0x3 - 3.0 A 0x4 - 3.5 A 0x5 - 4.0 A 0x6 - 4.5 A 0x7 - Reserved (Default from OTP memory)

Sets the output voltage slew rate for BUCK0 converter (rising and falling edges):

0x0 - Reserved 0x1 - Reserved 0x2 - 10 mV/μs 0x3 - 7.5 mV/μs 0x4 - 3.8 mV/μs 0x5 - 1.9 mV/μs 0x6 - 0.94 mV/μs 0x7 - 0.47 mV/μs (Default from OTP memory)

LP87702-Q1

7.6.1.1.5 BUCK1_CTRL_1 Register (Offset = 4h) [reset = 8h]

BUCK1_CTRL_1 is shown in Figure 31 and described in Table 15. Return to Summary Table.

Figure 31. BUCK1_CTRL_1 Register

7 6 5 4 3 2 1 0

RESERVED BUCK1_FPWM BUCK1_RDIS_

R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h

Product Folder Links: LP87702-Q1

BUCK1_EN_PIN_CTRL BUCK1_EN

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Table 15. BUCK1_CTRL_1 Register Field Descriptions

Bit Field Type Reset Description

7-5 RESERVED R/W 0h

4 BUCK1_FPWM R/W 0h

3 BUCK1_RDIS_EN R/W 1h

2-1 BUCK1_EN_PIN_CTRL R/W 0h

0 BUCK1_EN R/W 0h

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Forces the BUCK1 converter to operate in PWM mode: 0 - Automatic transitions between PFM and PWM modes (AUTO

mode). 1 - Forced to PWM operation. (Default from OTP memory)

Enable output discharge resistor when BUCK1 is disabled: 0 - Discharge resistor disabled 1 - Discharge resistor enabled.

Enable/disable control for BUCK1: 0x0 - only BUCK1_EN bit controls BUCK1 0x1 - BUCK1_EN bit AND EN1 pin control BUCK1 0x2 - BUCK1_EN bit AND EN2 pin control BUCK1 0x3 - BUCK1_EN bit AND EN3 pin control BUCK1 (Default from OTP memory)

Enable BUCK1 converter: 0 - BUCK1 converter is disabled 1 - BUCK1 converter is enabled. (Default from OTP memory)

7.6.1.1.6 BUCK1_CTRL_2 Register (Offset = 5h) [reset = 1Ah]

BUCK1_CTRL_2 is shown in Figure 32 and described in Table 16. Return to Summary Table.

Figure 32. BUCK1_CTRL_2 Register

7 6 5 4 3 2 1 0

RESERVED BUCK1_ILIM BUCK1_SLEW_RATE

R/W-0h R/W-3h R/W-2h

Table 16. BUCK1_CTRL_2 Register Field Descriptions

Bit Field Type Reset Description

7-6 RESERVED R/W 0h 5-3 BUCK1_ILIM R/W 3h

2-0 BUCK1_SLEW_RATE R/W 2h

Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation:

0x0 - 1.5 A 0x1 - 2.0 A 0x2 - 2.5 A 0x3 - 3.0 A 0x4 - 3.5 A 0x5 - 4.0 A 0x6 - 4.5 A 0x7 - Reserved (Default from OTP memory)

Sets the output voltage slew rate for BUCK1 converter (rising and falling edges):

0x0 - Reserved 0x1 - Reserved 0x2 - 10 mV/μs 0x3 - 7.5 mV/μs 0x4 - 3.8 mV/μs 0x5 - 1.9 mV/μs 0x6 - 0.94 mV/μs 0x7 - 0.47 mV/μs (Default from OTP memory)

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7.6.1.1.7 BUCK0_VOUT Register (Offset = 6h) [reset = 0h]

BUCK0_VOUT is shown in Figure 33 and described in Table 17. Return to Summary Table.

Figure 33. BUCK0_VOUT Register

7 6 5 4 3 2 1 0

BUCK0_VSET

R/W-0h

Table 17. BUCK0_VOUT Register Field Descriptions

Bit Field Type Reset Description

7-0 BUCK0_VSET R/W 0h

Output voltage of BUCK0 converter: 0x00 ... 0x13, Reserved, DO NOT USE

0.7 V - 0.73 V, 10 mV steps 0x14 - 0.7V ... 0x17 - 0.73 V

0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V

1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V (Default from OTP memory)

LP87702-Q1

7.6.1.1.8 BUCK1_VOUT Register (Offset = 7h) [reset = 0h]

BUCK1_VOUT is shown in Figure 34 and described in Table 18. Return to Summary Table.

Figure 34. BUCK1_VOUT Register

7 6 5 4 3 2 1 0

BUCK1_VSET

R/W-0h

Table 18. BUCK1_VOUT Register Field Descriptions

Bit Field Type Reset Description

7-0 BUCK1_VSET R/W 0h

Output voltage of BUCK1 converter 0x00 ... 0x13, Reserved, DO NOT USE

0.7 V - 0.73 V, 10 mV steps 0x14 - 0.7V ... 0x17 - 0.73 V

0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V

1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V (Default from OTP memory)

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7.6.1.1.9 BOOST_CTRL Register (Offset = 8h) [reset = 8h]

BOOST_CTRL is shown in Figure 35 and described in Table 19. Return to Summary Table.

Figure 35. BOOST_CTRL Register

7 6 5 4 3 2 1 0

BOOST_VSET RESERVED BOOST_FPWM BOOST_RDIS_

R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h

BOOST_EN_PIN_CTRL BOOST_EN

Table 19. BOOST_CTRL Register Field Descriptions

Bit Field Type Reset Description

7-6 BOOST_VSET R/W 0h

5 RESERVED R/W 0h 4 RESERVED R/W 1h 3 BOOST_RDIS_EN R/W 1h

2-1 BOOST_EN_PIN_CTRL R/W 0h

0 BOOST_EN R/W 0h

Output voltage of Boost: 0x0 - 4.9V 0x1 - 5.0V 0x2 - 5.1V 0x3 - 5.2V (Default from OTP memory)

Enable output discharge resistor when BOOST is disabled: 0 - Discharge resistor disabled 1 - Discharge resistor enabled.

Enable/disable control for Boost: 0x0 - only BOOST_EN bit controls Boost 0x1 - BOOST_EN bit AND EN1 pin control Boost 0x2 - BOOST_EN bit AND EN2 pin control Boost 0x3 - BOOST_EN bit AND EN3 pin control Boost (Default from OTP memory)

Enable Boost converter: 0 - Boost converter is disabled 1 - Boost converter is enabled. (Default from OTP memory)

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7.6.1.1.10 BUCK0_DELAY Register (Offset = 9h) [reset = 0h]

BUCK0_DELAY is shown in Figure 36 and described in Table 20. Return to Summary Table.

Figure 36. BUCK0_DELAY Register

7 6 5 4 3 2 1 0

BUCK0_SHUTDOWN_DELAY BUCK0_STARTUP_DELAY

R/W-0h R/W-0h

Table 20. BUCK0_DELAY Register Field Descriptions

Bit Field Type Reset Description

7-4 BUCK0_SHUTDOWN_DE

LAY

R/W 0h

Product Folder Links: LP87702-Q1

Shutdown delay of BUCK0 from falling edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

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Table 20. BUCK0_DELAY Register Field Descriptions (continued)

Bit Field Type Reset Description

3-0 BUCK0_STARTUP_DELAYR/W 0h

Startup delay of BUCK0 from rising edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

7.6.1.1.11 BUCK1_DELAY Register (Offset = Ah) [reset = 0h]

BUCK1_DELAY is shown in Figure 37 and described in Table 21. Return to Summary Table.

Figure 37. BUCK1_DELAY Register

7 6 5 4 3 2 1 0

BUCK1_SHUTDOWN_DELAY BUCK1_STARTUP_DELAY

R/W-0h R/W-0h

Table 21. BUCK1_DELAY Register Field Descriptions

Bit Field Type Reset Description

7-4 BUCK1_SHUTDOWN_DE

LAY

3-0 BUCK1_STARTUP_DELAYR/W 0h

R/W 0h

Shutdown delay of BUCK1 from falling edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

Startup delay of BUCK1 from rising edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

LP87702-Q1

7.6.1.1.12 BOOST_DELAY Register (Offset = Bh) [reset = 0h]

BOOST_DELAY is shown in Figure 38 and described in Table 22. Return to Summary Table.

Figure 38. BOOST_DELAY Register

7 6 5 4 3 2 1 0

BOOST_SHUTDOWN_DELAY BOOST_STARTUP_DELAY

R/W-0h R/W-0h

Table 22. BOOST_DELAY Register Field Descriptions

Bit Field Type Reset Description

7-4 BOOST_SHUTDOWN_D

ELAY

R/W 0h

Product Folder Links: LP87702-Q1

Shutdown delay of Boost from falling edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

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Table 22. BOOST_DELAY Register Field Descriptions (continued)

Bit Field Type Reset Description

3-0 BOOST_STARTUP_DELAYR/W 0h

Startup delay of Boost from rising edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

7.6.1.1.13 GPO0_DELAY Register (Offset = Ch) [reset = 0h]

GPO0_DELAY is shown in Figure 39 and described in Table 23. Return to Summary Table.

Figure 39. GPO0_DELAY Register

7 6 5 4 3 2 1 0

GPO0_SHUTDOWN_DELAY GPO0_STARTUP_DELAY

R/W-0h R/W-0h

Table 23. GPO0_DELAY Register Field Descriptions

Bit Field Type Reset Description

7-4 GPO0_SHUTDOWN_DELAYR/W 0h

3-0 GPO0_STARTUP_DELAY R/W 0h

Shutdown delay of GPO0 from falling edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

Startup delay of GPO0 from rising edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

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7.6.1.1.14 GPO1_DELAY Register (Offset = Dh) [reset = 0h]

GPO1_DELAY is shown in Figure 40 and described in Table 24. Return to Summary Table.

Figure 40. GPO1_DELAY Register

7 6 5 4 3 2 1 0

GPO1_SHUTDOWN_DELAY GPO1_STARTUP_DELAY

R/W-0h R/W-0h

Table 24. GPO1_DELAY Register Field Descriptions

Bit Field Type Reset Description

7-4 GPO1_SHUTDOWN_DELAYR/W 0h

Product Folder Links: LP87702-Q1

Shutdown delay of GPO1 from falling edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

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Table 24. GPO1_DELAY Register Field Descriptions (continued)

Bit Field Type Reset Description

3-0 GPO1_STARTUP_DELAY R/W 0h

Startup delay of GPO1 from rising edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

7.6.1.1.15 GPO2_DELAY Register (Offset = Eh) [reset = 0h]

GPO2_DELAY is shown in Figure 41 and described in Table 25. Return to Summary Table.

Figure 41. GPO2_DELAY Register

7 6 5 4 3 2 1 0

GPO2_SHUTDOWN_DELAY GPO2_STARTUP_DELAY

R/W-0h R/W-0h

Table 25. GPO2_DELAY Register Field Descriptions

Bit Field Type Reset Description

7-4 GPO2_SHUTDOWN_DELAYR/W 0h

3-0 GPO2_STARTUP_DELAY R/W 0h

Shutdown delay of GPO2 from falling edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

Startup delay of GPO2 from rising edge of control signal: 0000 - 0 ms 0001 - 0.5 ms (1ms if CONFIG(STARTUP_DELAY_SEL)=1) ... 1111 - 7.5 ms (15ms if CONFIG(STARTUP_DELAY_SEL)=1) (Default from OTP memory)

LP87702-Q1

7.6.1.1.16 GPO_CONTROL_1 Register (Offset = Fh) [reset = AAh]

GPO_CONTROL_1 is shown in Figure 42 and described in Table 26. Return to Summary Table.

Figure 42. GPO_CONTROL_1 Register

7 6 5 4 3 2 1 0

GPO1_PG1_O

R/W-1h R/W-1h R/W-0h R/W-1h R/W-1h R/W-0h

GPO1_EN_PIN_CTRL GPO1_OUT GPO0_OD GPO0_EN_PIN_CTRL GPO0_OUT

Table 26. GPO_CONTROL_1 Register Field Descriptions

Bit Field Type Reset Description

7 GPO1_PG1_OD R/W 1h

Product Folder Links: LP87702-Q1

GPO1 / PG1 signal type: 0 - Push-pull output (VANA level) 1 - Open-drain output (Default from OTP memory)

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Table 26. GPO_CONTROL_1 Register Field Descriptions (continued)

Bit Field Type Reset Description

6-5 GPO1_EN_PIN_CTRL R/W 1h

4 GPO1_OUT R/W 0h

3 GPO0_OD R/W 1h

2-1 GPO0_EN_PIN_CTRL R/W 1h

0 GPO0_OUT R/W 0h

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Control for GPO1 output: 0x0 - only GPO1_OUT bit controls GPO1 0x1 - GPO1_OUT bit AND EN1 pin control GPO1 0x2 - GPO1_OUT bit AND EN2 pin control GPO1 0x3 - GPO1_OUT bit AND EN3 pin control GPO1 (Default from OTP memory)

Control for GPO1 signal (when configured to GPO1): 0 - Logic low level 1 - Logic high level (Default from OTP memory)

GPO0 signal type: 0 - Push-pull output (VANA level) 1 - Open-drain output (Default from OTP memory)

Control for GPO0 output: 0x0 - only GPO0_OUT bit controls GPO0 0x1 - GPO0_OUT bit AND EN1 pin control GPO0 0x2 - GPO0_OUT bit AND EN2 pin control GPO0 0x3 - GPO0_OUT bit AND EN3 pin control GPO0 (Default from OTP memory)

Control for GPO0 signal: 0 - Logic low level 1 - Logic high level (Default from OTP memory)

7.6.1.1.17 GPO_CONTROL_2 Register (Offset = 10h) [reset = Ah]

GPO_CONTROL_2 is shown in Figure 43 and described in Table 27. Return to Summary Table.

Figure 43. GPO_CONTROL_2 Register

7 6 5 4 3 2 1 0

RESERVED GPO2_SEL GPO1_SEL GPO2_OD GPO2_EN_PIN_CTRL GPO2_OUT

R/W-0h R/W-0h R/W-0h R/W-1h R/W-1h R/W-0h

Table 27. GPO_CONTROL_2 Register Field Descriptions

Bit Field Type Reset Description

7-6 RESERVED R/W 0h

5 GPO2_SEL R/W 0h

4 GPO1_SEL R/W 0h

3 GPO2_OD R/W 1h

CLKIN/GPO2 pin function: 0 - CLKIN 1 - GPO2 (Default from OTP memory)

PG1/GPO1 pin function: 0 - PG1 1 - GPO1 (Default from OTP memory)

GPO2 signal type (when configured to GPO2): 0 - Push-pull output (VANA level) 1 - Open-drain output (Default from OTP memory)

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Table 27. GPO_CONTROL_2 Register Field Descriptions (continued)

Bit Field Type Reset Description

2-1 GPO2_EN_PIN_CTRL R/W 1h

0 GPO2_OUT R/W 0h

Control for GPO2 output: 0x0 - only GPO2_OUT bit controls GPO2 0x1 - GPO2_OUT bit AND EN1 pin control GPO2 0x2 - GPO2_OUT bit AND EN2 pin control GPO2 0x3 - GPO2_OUT bit AND EN3 pin control GPO2 (Default from OTP memory)

Control for GPO2 signal (when configured to GPO2): 0 - Logic low level 1 - Logic high level (Default from OTP memory)

7.6.1.1.18 CONFIG Register (Offset = 11h) [reset = 3Ch]

CONFIG is shown in Figure 44 and described in Table 28. Return to Summary Table.

Figure 44. CONFIG Register

7 6 5 4 3 2 1 0

STARTUP_DE

LAY_SEL

R/W-0h R/W-0h R/W-1h R/W-1h R/W-1h R/W-1h R/W-0h R/W-0h

SHUTDOWN_

DELAY_SEL

CLKIN_PD EN3_PD EN2_PD EN1_PD TDIE_WARN_L

EVEL

LP87702-Q1

EN_SPREAD_

SPEC

Table 28. CONFIG Register Field Descriptions

Bit Field Type Reset Description

7 STARTUP_DELAY_SEL R/W 0h

6 SHUTDOWN_DELAY_SELR/W 0h

5 CLKIN_PD R/W 1h

4 EN3_PD R/W 1h

3 EN2_PD R/W 1h

2 EN1_PD R/W 1h

1 TDIE_WARN_LEVEL R/W 0h

Startup delays from control signal: 0 - 0ms - 7.5ms with 0.5ms steps 1 - 0ms - 15ms with 1ms steps (Default from OTP memory)

Shutdown delays from from signal: 0 - 0ms - 7.5ms with 0.5ms steps 1 - 0ms - 15ms with 1ms steps (Default from OTP memory)

Selects the pull down resistor on the CLKIN input pin. 0 - Pull-down resistor is disabled. 1 - Pull-down resistor is enabled. (Default from OTP memory)

Selects the pull down resistor on the EN3 pin: 0 - Pull-down resistor is disabled 1 - Pull-down resistor is enabled (Default from OTP memory)

Selects the pull down resistor on the EN2 pin: 0 - Pull-down resistor is disabled 1 - Pull-down resistor is enabled (Default from OTP memory)

Selects the pull down resistor on the EN1 pin: 0 - Pull-down resistor is disabled 1 - Pull-down resistor is enabled (Default from OTP memory)

Thermal warning threshold level. 0 - 125C 1 - 140C. (Default from OTP memory)

Product Folder Links: LP87702-Q1

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Table 28. CONFIG Register Field Descriptions (continued)

Bit Field Type Reset Description

0 EN_SPREAD_SPEC R/W 0h

Enable spread spectrum feature for Buck and Boost converters. 0 - Disabled 1 - Enabled (Default from OTP memory)

7.6.1.1.19 PLL_CTRL Register (Offset = 12h) [reset = 2h]

PLL_CTRL is shown in Figure 45 and described in Table 29. Return to Summary Table.

Figure 45. PLL_CTRL Register

7 6 5 4 3 2 1 0

RESERVED EN_PLL EN_FRAC_DIV EXT_CLK_FREQ

R/W-0h R/W-0h R/W-0h R/W-2h

Table 29. PLL_CTRL Register Field Descriptions

Bit Field Type Reset Description

7 RESERVED R/W 0h 6 EN_PLL R/W 0h

5 EN_FRAC_DIV R/W 0h

4-0 EXT_CLK_FREQ R/W 2h

Selection of external clock and PLL operation: 0 - Forced to internal RC oscillator. PLL disabled. 1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic

external clock use when available, interrupt generated if external clock appears or disappears.

(Default from OTP memory) This bit must be set to '0'. Frequency of the external clock (CLKIN):

0x00 - 1 MHz 0x01 - 2 MHz 0x02 - 3 MHz ... 0x16 - 23 MHz 0x17 - 24 MHz 0x18...0x1F - Reserved See electrical specification for input clock frequency tolerance. (Default from OTP memory) Note: To ensure proper operation of

PLL, EXT_CLK_FREQ value must not be changed when PLL is enabled.

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7.6.1.1.20 PGOOD_CTRL Register (Offset = 13h) [reset = 0h]

PGOOD_CTRL is shown in Figure 46 and described in Table 30. Return to Summary Table.

Figure 46. PGOOD_CTRL Register

7 6 5 4 3 2 1 0

RESERVED PGOOD_WINDOWEN_PGOOD_V

R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

ANA

EN_PGOOD_V

MON2

Product Folder Links: LP87702-Q1

EN_PGOOD_V

MON1

EN_PGOOD_B

OOST

EN_PGOOD_B

UCK1

EN_PGOOD_B

UCK0

Page 59

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Table 30. PGOOD_CTRL Register Field Descriptions

Bit Field Type Reset Description

7 RESERVED R/W 0h 6 PGOOD_WINDOW R/W 0h

5 EN_PGOOD_VANA R/W 0h

4 EN_PGOOD_VMON2 R/W 0h

3 EN_PGOOD_VMON1 R/W 0h

2 EN_PGOOD_BOOST R/W 0h

1 EN_PGOOD_BUCK1 R/W 0h

0 EN_PGOOD_BUCK0 R/W 0h

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Voltage monitoring method for PG0 and PG1 signals: 0 - Only undervoltage monitoring. 1 - Overvoltage and undervoltage monitoring. (Default from OTP memory) Note: Changing this value during

operation may cause interrupt. Enable powergood diagnostics for VANA

0 - Disabled 1 - Enabled (Default from OTP memory) Note: Changing this value during

operation may cause interrupt. Enable powergood diagnostics for VMON2

0 - Disabled 1 - Enabled (Default from OTP memory) Note: Changing this value during

operation may cause interrupt. Enable powergood diagnostics for VMON1

0 - Disabled 1 - Enabled (Default from OTP memory) Note: Changing this value during

operation may cause interrupt. Enable powergood diagnostics for Boost

0 - Disabled 1 - Enabled (Default from OTP memory) Note: Changing this value during

operation may cause interrupt. Enable powergood diagnostics for Buck1

0 - Disabled 1 - Enabled (Default from OTP memory) Note: Changing this value during

operation may cause interrupt. Enable powergood diagnostics for Buck0

0 - Disabled 1 - Enabled (Default from OTP memory) Note: Changing this value during

operation may cause interrupt.

7.6.1.1.21 PGOOD_LEVEL_1 Register (Offset = 14h) [reset = 0h]

PGOOD_LEVEL_1 is shown in Figure 47 and described in Table 31. Return to Summary Table.

Figure 47. PGOOD_LEVEL_1 Register

7 6 5 4 3 2 1 0

RESERVED VMON1_WINDOW VMON1_THRESHOLD

R/W-0h R/W-0h R/W-0h

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Table 31. PGOOD_LEVEL_1 Register Field Descriptions

Bit Field Type Reset Description

7-5 RESERVED R/W 0h 4-3 VMON1_WINDOW R/W 0h

2-0 VMON1_THRESHOLD R/W 0h

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Overvoltage and undervoltage threshold levels for VMON1: 0x0 - +/-2% 0x1 - +/-3% 0x2 - +/-4% 0x3 - +/-6% (Default from OTP memory)

Threshold voltage for VMON1 input: 0x0 - 0.65V (high impedance input, external resistive divider can be

used) 0x1 - 0.80V 0x2 - 1.00V 0x3 - 1.10V 0x4 - 1.20V 0x5 - 1.30V 0x6 - 1.80V 0x7 - 1.80V To monitor any other voltage level, select 0x0 and use an external

resistive divider to scale down to 0.65V. For other than 0x0 VMONx input is low impedance (internal resistive divider enabled).

(Default from OTP memory)

7.6.1.1.22 PGOOD_LEVEL_2 Register (Offset = 15h) [reset = 0h]

PGOOD_LEVEL_2 is shown in Figure 48 and described in Table 32. Return to Summary Table.

Figure 48. PGOOD_LEVEL_2 Register

7 6 5 4 3 2 1 0

VANA_WINDOW VANA_THRES

HOLD

R/W-0h R/W-0h R/W-0h R/W-0h

VMON2_WINDOW VMON2_THRESHOLD

Table 32. PGOOD_LEVEL_2 Register Field Descriptions

Bit Field Type Reset Description

7-6 VANA_WINDOW R/W 0h

5 VANA_THRESHOLD R/W 0h

4-3 VMON2_WINDOW R/W 0h

Overvoltage and undervoltage threshold levels for VANA: 0x0 - +/-4% 0x1 - +/-5% 0x2 - +/-10% 0x3 - +/-10% (Default from OTP memory)

Threshold voltage for VANA input: 0 - 3.3V 1 - 5.0V (Default from OTP memory)

Overvoltage and undervoltage threshold levels for VMON2: 0x0 - +/-2% 0x1 - +/-3% 0x2 - +/-4% 0x3 - +/-6% (Default from OTP memory)

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Table 32. PGOOD_LEVEL_2 Register Field Descriptions (continued)

Bit Field Type Reset Description

2-0 VMON2_THRESHOLD R/W 0h

Threshold voltage for VMON2 input: 0x0 - 0.65V (high impedance input, external resistive divider can be

used) 0x1 - 0.80V 0x2 - 1.00V 0x3 - 1.10V 0x4 - 1.20V 0x5 - 1.30V 0x6 - 1.80V 0x7 - 1.80V To monitor any other voltage level, select 0x0 and use an external

resistive divider to scale down to 0.65V. For other than 0x0 VMONx input is low impedance (internal resistive divider enabled).

(Default from OTP memory)

7.6.1.1.23 PGOOD_LEVEL_3 Register (Offset = 16h) [reset = 0h]

PGOOD_LEVEL_3 is shown in Figure 49 and described in Table 33. Return to Summary Table.

Figure 49. PGOOD_LEVEL_3 Register

7 6 5 4 3 2 1 0 BOOST_WINDOW BOOST_THRESHOLD BUCK1_WINDOW BUCK0_WINDOW

R/W-0h R/W-0h R/W-0h R/W-0h

LP87702-Q1

Table 33. PGOOD_LEVEL_3 Register Field Descriptions

Bit Field Type Reset Description

7-6 BOOST_WINDOW R/W 0h

5-4 BOOST_THRESHOLD R/W 0h 3-2 BUCK1_WINDOW R/W 0h

1-0 BUCK0_WINDOW R/W 0h

Undervoltage/overvoltage threshold levels for Boost: 0x0 - +/-2% 0x1 - +/-4% 0x2 - +/-6% 0x3 - +/-8% (Default from OTP memory)

(Default from OTP memory) Overvoltage and undervoltage threshold levels for Buck1:

0x0 - +/-30 mV 0x1 - +/-50 mV 0x2 - +/-70 mV 0x3 - +/-90 mV (Default from OTP memory)

Overvoltage and undervoltage threshold levels for Buck0: 0x0 - +/-30 mV 0x1 - +/-50 mV 0x2 - +/-70 mV 0x3 - +/-90 mV (Default from OTP memory)

7.6.1.1.24 PG_CTRL Register (Offset = 17h) [reset = 2h]

PG_CTRL is shown in Figure 50 and described in Table 34. Return to Summary Table.

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Figure 50. PG_CTRL Register

7 6 5 4 3 2 1 0

PG1_MODE PGOOD_FAUL

T_GATES_PG1

R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h

RESERVED PG1_POL PG0_MODE PGOOD_FAUL

T_GATES_PG0

PG0_OD PG0_POL

Table 34. PG_CTRL Register Field Descriptions

Bit Field Type Reset Description

7 PG1_MODE R/W 0h

6 PGOOD_FAULT_GATES

_PG1

5 RESERVED R/W 0h 4 PG1_POL R/W 0h

3 PG0_MODE R/W 0h

2 PGOOD_FAULT_GATES

_PG0

1 PG0_OD R/W 1h

0 PG0_POL R/W 0h

R/W 0h

Operating mode for PG1 signal: 0 - Detecting unusual situations 1 - Showing when requested outputs are not valid. (Default from OTP memory)

Type of operation for PG1 signal: 0 - Indicates live status of monitored voltage outputs. 1 - Indicates status of PG1_FAULT register, inactive if at least one of

PG1_FAULT_x bit is inactive. (Default from OTP memory)

PG1 signal polarity. 0 - PG1 signal high when monitored outputs are valid 1 - PG1 signal low when monitored outputs are valid (Default from OTP memory)

Operating mode for PG0 signal: 0 - Detecting unusual situations 1 - Showing when requested outputs are not valid. (Default from OTP memory)

Type of operation for PG0 signal: 0 - Indicates live status of monitored voltage outputs. 1 - Indicates status of PG0_FAULT register, inactive if at least one of

PG0_FAULT_x bit is inactive. (Default from OTP memory)

PG0 signal type: 0 - Push-pull output (VANA level) 1 - Open-drain output (Default from OTP memory)

PG0 signal polarity. 0 - PG0 signal high when monitored outputs are valid 1 - PG0 signal low when monitored outputs are valid (Default from OTP memory)

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7.6.1.1.25 PG0_CTRL Register (Offset = 18h) [reset = 0h]

PG0_CTRL is shown in Figure 51 and described in Table 35. Return to Summary Table.

Figure 51. PG0_CTRL Register

7 6 5 4 3 2 1 0

PG0_RISE_DE

LAY

R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

SEL_PG0_TW

ARN

SEL_PG0_VANASEL_PG0_VM

ON2

Product Folder Links: LP87702-Q1

SEL_PG0_VM

ON1

SEL_PG0_BO

OST

SEL_PG0_BUCK1SEL_PG0_BUC

Page 63

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Table 35. PG0_CTRL Register Field Descriptions

Bit Field Type Reset Description

7 PG0_RISE_DELAY R/W 0h 6 SEL_PG0_TWARN R/W 0h

5 SEL_PG0_VANA R/W 0h

4 SEL_PG0_VMON2 R/W 0h

3 SEL_PG0_VMON1 R/W 0h

2 SEL_PG0_BOOST R/W 0h

1 SEL_PG0_BUCK1 R/W 0h

0 SEL_PG0_BUCK0 R/W 0h

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

0 - PG0 rise is not delayed 1 - PG0 rise is delayed 11ms PG0 control from thermal warning:

0 - Masked 1 - Affecting PGOOD (Default from OTP memory)

PG0 signal source control from VANA 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

PG0 signal source control from VMON2 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

PG0 signal source control from VMON1 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

PG0 signal source control from Boost 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

PG0 signal source control from Buck1 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

PG0 signal source control from Buck0 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

7.6.1.1.26 PG0_FAULT Register (Offset = 19h) [reset = 0h]

PG0_FAULT is shown in Figure 52 and described in Table 36. Return to Summary Table.

Figure 52. PG0_FAULT Register

7 6 5 4 3 2 1 0

RESERVED PG0_FAULT_T

WARN

R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

PG0_FAULT_V

ANA

PG0_FAULT_V

MON2

PG0_FAULT_V

MON1

PG0_FAULT_B

OOST

PG0_FAULT_B

UCK1

Table 36. PG0_FAULT Register Field Descriptions

Bit Field Type Reset Description

7 RESERVED R 0h 6 PG0_FAULT_TWARN R 0h

Product Folder Links: LP87702-Q1

Source for PG0 inactive signal: 0 - TWARN has not set PG0 signal inactive. 1 - TWARN is selected for PG0 signal and it has set PG0 signal

inactive. This bit can be cleared by writing '1' to this bit when TWARN is valid.

PG0_FAULT_B

UCK0

Page 64

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Table 36. PG0_FAULT Register Field Descriptions (continued)

Bit Field Type Reset Description

5 PG0_FAULT_VANA R 0h

4 PG0_FAULT_VMON2 R 0h

3 PG0_FAULT_VMON1 R 0h

2 PG0_FAULT_BOOST R 0h

1 PG0_FAULT_BUCK1 R 0h

0 PG0_FAULT_BUCK0 R 0h

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Source for PG0 inactive signal: 0 - VANA has not set PG0 signal inactive. 1 - VANA is selected for PG0 signal and it has set PG0 signal

inactive. This bit can be cleared by writing '1' to this bit when VANA input is valid.

Source for PG0 inactive signal: 0 - VMON2 has not set PG0 signal inactive. 1 - VMON2 is selected for PG0 signal and it has set PG0 signal

inactive. This bit can be cleared by writing '1' to this bit when VMON2 input is valid.

Source for PG0 inactive signal: 0 - VMON1 has not set PG0 signal inactive. 1 - VMON1 is selected for PG0 signal and it has set PG0 signal

inactive. This bit can be cleared by writing '1' to this bit when VMON1 input is valid.

Source for PG0 inactive signal: 0 - Boost has not set PG0 signal inactive. 1 - Boost is selected for PG0 signal and it has set PG0 signal

inactive. This bit can be cleared by writing '1' to this bit when Boost output is valid.

Source for PG0 inactive signal: 0 - Buck1 has not set PG0 signal inactive. 1 - Buck1 is selected for PG0 signal and it has set PG0 signal

inactive. This bit can be cleared by writing '1' to this bit when Buck1 output is valid.

Source for PG0 inactive signal: 0 - Buck0 has not set PG0 signal inactive. 1 - Buck0 is selected for PG0 signal and it has set PG0 signal

inactive. This bit can be cleared by writing '1' to this bit when Buck0 output is valid.

7.6.1.1.27 PG1_CTRL Register (Offset = 1Ah) [reset = 0h]

PG1_CTRL is shown in Figure 53 and described in Table 37. Return to Summary Table.

Figure 53. PG1_CTRL Register

7 6 5 4 3 2 1 0

PG1_RISE_DE

LAY

R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

SEL_PG1_TW

ARN

SEL_PG1_VANASEL_PG1_VM

ON2

SEL_PG1_VM

ON1

SEL_PG1_BO

OST

SEL_PG1_BUCK1SEL_PG1_BUC

Table 37. PG1_CTRL Register Field Descriptions

Bit Field Type Reset Description

7 PG1_RISE_DELAY R/W 0h 6 SEL_PG1_TWARN R/W 0h

5 SEL_PG1_VANA R/W 0h

0 - PG1 rise is not delayed 1 - PG1 rise is delayed 11ms PG1 control from thermal warning:

0 - Masked 1 - Affecting PGOOD (Default from OTP memory)

PG1 signal source control from VANA 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

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Table 37. PG1_CTRL Register Field Descriptions (continued)

Bit Field Type Reset Description

4 SEL_PG1_VMON2 R/W 0h

3 SEL_PG1_VMON1 R/W 0h

2 SEL_PG1_BOOST R/W 0h

1 SEL_PG1_BUCK1 R/W 0h

0 SEL_PG1_BUCK0 R/W 0h

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

PG1 signal source control from VMON2 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

PG1 signal source control from VMON1 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

PG1 signal source control from Boost 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

PG1 signal source control from Buck1 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

PG1 signal source control from Buck0 0 - Masked 1 - Powergood threshold voltage (Default from OTP memory)

7.6.1.1.28 PG1_FAULT Register (Offset = 1Bh) [reset = 0h]

PG1_FAULT is shown in Figure 54 and described in Table 38. Return to Summary Table.

Figure 54. PG1_FAULT Register

7 6 5 4 3 2 1 0

RESERVED PG1_FAULT_T

WARN

R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

PG1_FAULT_V

ANA

PG1_FAULT_V

MON2

PG1_FAULT_V

MON1

PG1_FAULT_B

OOST

PG1_FAULT_B

UCK1

Table 38. PG1_FAULT Register Field Descriptions

Bit Field Type Reset Description

7 RESERVED R 0h 6 PG1_FAULT_TWARN R 0h

5 PG1_FAULT_VANA R 0h

4 PG1_FAULT_VMON2 R 0h

Source for PG1 inactive signal: 0 - TWARN has not set PG1 signal inactive. 1 - TWARN is selected for PG1 signal and it has set PG1 signal

inactive. This bit can be cleared by writing '1' to this bit when TWARN is valid.

Source for PG1 inactive signal: 0 - VANA has not set PG1 signal inactive. 1 - VANA is selected for PG1 signal and it has set PG1 signal

inactive. This bit can be cleared by writing '1' to this bit when VANA input is valid.

Source for PG1 inactive signal: 0 - VMON2 has not set PG1 signal inactive. 1 - VMON2 is selected for PG1 signal and it has set PG1 signal

inactive. This bit can be cleared by writing '1' to this bit when VMON2 input is valid.

PG1_FAULT_B

UCK0

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Table 38. PG1_FAULT Register Field Descriptions (continued)

Bit Field Type Reset Description

3 PG1_FAULT_VMON1 R 0h

2 PG1_FAULT_BOOST R 0h

1 PG1_FAULT_BUCK1 R 0h

0 PG1_FAULT_BUCK0 R 0h

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Source for PG1 inactive signal: 0 - VMON1 has not set PG1 signal inactive. 1 - VMON1 is selected for PG1 signal and it has set PG1 signal

inactive. This bit can be cleared by writing '1' to this bit when VMON1 input is valid.

Source for PG1 inactive signal: 0 - Boost has not set PG1 signal inactive. 1 - Boost is selected for PG1 signal and it has set PG1 signal

inactive. This bit can be cleared by writing '1' to this bit when Boost output is valid.

Source for PG1 inactive signal: 0 - Buck1 has not set PG1 signal inactive. 1 - Buck1 is selected for PG1 signal and it has set PG1 signal

inactive. This bit can be cleared by writing '1' to this bit when Buck1 output is valid.

Source for PG1 inactive signal: 0 - Buck0 has not set PG1 signal inactive. 1 - Buck0 is selected for PG1 signal and it has set PG1 signal

inactive. This bit can be cleared by writing '1' to this bit when Buck0 output is valid.

7.6.1.1.29 WD_CTRL_1 Register (Offset = 1Ch) [reset = 0h]

WD_CTRL_1 is shown in Figure 55 and described in Table 39. Return to Summary Table.

Figure 55. WD_CTRL_1 Register

7 6 5 4 3 2 1 0 WD_CLOSE_TIME WD_OPEN_TIME WD_LONG_OPEN_TIME WD_RESET_CNTR_SEL

R/W-0h R/W-0h R/W-0h R/W-0h

Table 39. WD_CTRL_1 Register Field Descriptions

Bit Field Type Reset Description

7-6 WD_CLOSE_TIME R/W 0h

5-4 WD_OPEN_TIME R/W 0h

3-2 WD_LONG_OPEN_TIME R/W 0h

Watchdog close window time select. 00 - 10ms 01 - 20ms 10 - 50ms 11 - 100ms (Default from OTP memory)

Watchdog open window time select. 00 - 20ms 01 - 100ms 10 - 200ms 11 - 600ms (Default from OTP memory)

Watchdog long open window time select. 00 - 200ms 01 - 600ms 10 - 2000ms 11 - 5000ms (Default from OTP memory)

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Table 39. WD_CTRL_1 Register Field Descriptions (continued)

Bit Field Type Reset Description

1-0 WD_RESET_CNTR_SEL R/W 0h

Watchdog reset counter threshold select. After the selected number of reset (WDR) pulses system restart sequence is initiated.

00 - system restart disabled 01 - 1 10 - 2 11 - 4 (Default from OTP memory)

7.6.1.1.30 WD_CTRL_2 Register (Offset = 1Dh) [reset = 1h]

WD_CTRL_2 is shown in Figure 56 and described in Table 40. Return to Summary Table.

Figure 56. WD_CTRL_2 Register

7 6 5 4 3 2 1 0

WD_LOCK RESERVED WD_SYS_RES

TART_FLAG_

MODE

R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h

WD_EN_OTP_

READ

WDI_PD WDR_POL WDR_OD

LP87702-Q1

Table 40. WD_CTRL_2 Register Field Descriptions

Bit Field Type Reset Description

7 WD_LOCK R 0h

6-5 RESERVED R/W 0h

4 WD_SYS_RESTART_FLA

G_MODE

3 WD_EN_OTP_READ R/W 0h

2 WDI_PD R/W 0h

1 WDR_POL R/W 0h

0 WDR_OD R/W 1h

R/W 0h

Lock bit for watchdog controls. Locks all controls to watchdog in registers WD_CTRL_1, WD_CTRL_2. Lock bit also locks itself. Once lock bit is written 1 it cannot be written 0. Only reset can clear it. 0 Not locked 1 - Locked WD_STATUS register is not affected by WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK=1.

WD_SYSTEM_RESTART_FLAG mode select. 0 WD_SYSTEM_RESTART_FLAG is only a status bit. 1 WD_SYSTEM_RESTART_FLAG prevents further system restarts until it is cleared. (Default from OTP memory)

Read OTP during system restart sequence 0 - OTP read not enabled during system restart sequence 1 - OTP read enabled during system restart sequence (Default from OTP memory)

Selects the pull down resistor on the WDI pin: 0 - Pull-down resistor is disabled 1 - Pull-down resistor is enabled (Default from OTP memory)

Watchdog reset output (WDR) polarity select 0 - Active high 1 Active low (Default from OTP memory)

Watchdog reset output (WDR) signal type 0 - Push-pull output (VANA level) 1 - Open-drain output (Default from OTP memory)

7.6.1.1.31 WD_STATUS Register (Offset = 1Eh) [reset = 0h]

WD_STATUS is shown in Figure 57 and described in Table 41. Return to Summary Table.

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Figure 57. WD_STATUS Register

7 6 5 4 3 2 1 0

RESERVED WD_CLR_SYS

TEM_RESTAR

T_FLAG

R/W-0h R-0h R-0h R-0h R-0h

WD_SYSTEM_ RESTART_FLA

WD_CLR_RES

ET_CNTR

WD_RESET_CNTR_STATUS

Table 41. WD_STATUS Register Field Descriptions

Bit Field Type Reset Description

7-5 RESERVED R/W 0h

4 WD_CLR_SYSTEM_RES

TART_FLAG

3 WD_SYSTEM_RESTART

_FLAG

2 WD_CLR_RESET_CNTR R 0h

1-0 WD_RESET_CNTR_STA

TUS

R 0h

Clear bit for WD_SYSTEM_RESTART_FLAG. Write 1 to generate a clear pulse. Reg bit value returns to 0 after clearing is finished.

Watchdog requested system restart has occurred. Can be cleared by writing WD_CLR_SYSTEM_RESTART_FLAG bit 1.

Watchdog reset counter clear. Write 1 to generate a clear pulse. Current status of watchdog reset counter.

7.6.1.1.32 RESET Register (Offset = 1Fh) [reset = 0h]

RESET is shown in Figure 58 and described in Table 42. Return to Summary Table.

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Figure 58. RESET Register

7 6 5 4 3 2 1 0

RESERVED SW_RESET

R/W-0h R-0h

Table 42. RESET Register Field Descriptions

Bit Field Type Reset Description

7-1 RESERVED R/W 0h

0 SW_RESET R 0h

Software commanded reset. When written to 1, the registers will be reset to default values and OTP memory is read.

The bit is automatically cleared.

7.6.1.1.33 INT_TOP_1 Register (Offset = 20h) [reset = 0h]

INT_TOP_1 is shown in Figure 59 and described in Table 43. Return to Summary Table.

Figure 59. INT_TOP_1 Register

7 6 5 4 3 2 1 0

I_MEAS_INT DIAG_INT BOOST_INT BUCK_INT SYNC_CLK_INTTDIE_SD_INT TDIE_WARN_INTOVP_INT

R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 43. INT_TOP_1 Register Field Descriptions

Bit Field Type Reset Description

7 I_MEAS_INT R 0h

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Latched status bit indicating that the load current measurement result is available in I_LOAD_1 and I_LOAD_2 registers.

Write 1 to clear interrupt.

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Table 43. INT_TOP_1 Register Field Descriptions (continued)

Bit Field Type Reset Description

6 DIAG_INT R 0h

5 BOOST_INT R 0h

4 BUCK_INT R 0h

3 SYNC_CLK_INT R 0h

2 TDIE_SD_INT R 0h

1 TDIE_WARN_INT R 0h

0 OVP_INT R 0h

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Interrupt indicating that INT_DIAG register has a pending interrupt. The reason for the interrupt is indicated in INT_DIAG register.

This bit is cleared automatically when INT_DIAG register is cleared to 0x00.

Interrupt indicating that BOOST have a pending interrupt. The reason for the interrupt is indicated in INT_BOOST register.

This bit is cleared automatically when INT_BOOST register is cleared to 0x00.

Interrupt indicating that BUCK0 and/or BUCK1 have a pending interrupt. The reason for the interrupt is indicated in INT_BUCK register.

This bit is cleared automatically when INT_BUCK register is cleared to 0x00.

Latched status bit indicating that the external clock frequency became valid or invalid.

Write 1 to clear interrupt. Latched status bit indicating that the die junction temperature has

exceeded the thermal shutdown level. The converters have been disabled if they were enabled. The converters cannot be enabled if this bit is active. The actual status of the thermal warning is indicated by TDIE_SD_STAT bit in TOP_STATUS register.

Write 1 to clear interrupt. Clearing TSD interrupt automatically reenables converters. Clearing this interrupt will also clear thermal warning status.

Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TDIE_WARN_STAT bit in TOP_STATUS register.

Write 1 to clear interrupt. Latched status bit indicating that the input voltage has exceeded the

over-voltage detection level. The actual status of the over-voltage is indicated by OVP bit in TOP_STATUS register.

Write 1 to clear interrupt.

7.6.1.1.34 INT_TOP_2 Register (Offset = 21h) [reset = 0h]

INT_TOP_2 is shown in Figure 60 and described in Table 44. Return to Summary Table.

Figure 60. INT_TOP_2 Register

7 6 5 4 3 2 1 0

RESERVED RESET_REG_I

R/W-0h R-0h

Table 44. INT_TOP_2 Register Field Descriptions

Bit Field Type Reset Description

7-1 RESERVED R/W 0h

0 RESET_REG_INT R 0h

Product Folder Links: LP87702-Q1

Latched status bit indicating that either VANA supply voltage has been below undervoltage threshold level or the host has requested a reset (SW_RESET bit in RESET register). The converters have been disabled, and registers are reset to default values and the normal startup procedure is done.

Write 1 to clear interrupt.

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

7.6.1.1.35 INT_BUCK Register (Offset = 22h) [reset = 0h]

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INT_BUCK is shown in Figure 61 and described in Table 45. Return to Summary Table.

Figure 61. INT_BUCK Register

7 6 5 4 3 2 1 0

RESERVED BUCK1_PG_INTBUCK1_SC_INTBUCK1_ILIM_INTRESERVED BUCK0_PG_INTBUCK0_SC_INTBUCK0_ILIM_I

R/W-0h R-0h R-0h R-0h R/W-0h R-0h R-0h R-0h

Table 45. INT_BUCK Register Field Descriptions

Bit Field Type Reset Description

7 RESERVED R/W 0h 6 BUCK1_PG_INT R 0h

5 BUCK1_SC_INT R 0h

4 BUCK1_ILIM_INT R 0h

3 RESERVED R/W 0h 2 BUCK0_PG_INT R 0h

1 BUCK0_SC_INT R 0h

0 BUCK0_ILIM_INT R 0h

Latched status bit indicating that BUCK1 powergood event has been detected.

Write 1 to clear. Latched status bit indicating that the BUCK1 output voltage has

fallen below 0.35 V level during operation or BUCK1 output didn't reach 0.35 V level in 1 ms from enable.

Write 1 to clear. Latched status bit indicating that BUCK1 output current limit has

been triggered. Write 1 to clear.

Latched status bit indicating that BUCK0 powergood event has been detected.

Write 1 to clear. Latched status bit indicating that the BUCK0 output voltage has

fallen below 0.35 V level during operation or BUCK0 output didn't reach 0.35 V level in 1 ms from enable.

Write 1 to clear. Latched status bit indicating that BUCK0 output current limit has

been triggered. Write 1 to clear.

7.6.1.1.36 INT_BOOST Register (Offset = 23h) [reset = 0h]

INT_BOOST is shown in Figure 62 and described in Table 46. Return to Summary Table.

Figure 62. INT_BOOST Register

7 6 5 4 3 2 1 0

RESERVED BOOST_PG_INTBOOST_SC_INTBOOST_ILIM_I

R/W-0h R-0h R-0h R-0h

Table 46. INT_BOOST Register Field Descriptions

Bit Field Type Reset Description

7-3 RESERVED R/W 0h

2 BOOST_PG_INT R 0h

Product Folder Links: LP87702-Q1

Latched status bit indicating that Boost powergood event has been detected.

Write 1 to clear.

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Table 46. INT_BOOST Register Field Descriptions (continued)

Bit Field Type Reset Description

1 BOOST_SC_INT R 0h

0 BOOST_ILIM_INT R 0h

Latched status bit indicating that the Boost output voltage has fallen to input voltage level or below 2.5 V level during operation or BOOST output didn't reach 2.5 V level in 1 ms from enable.

Write 1 to clear. Latched status bit indicating that Boost output current limit has been

triggered. Write 1 to clear.

7.6.1.1.37 INT_DIAG Register (Offset = 24h) [reset = 0h]

INT_DIAG is shown in Figure 63 and described in Table 47. Return to Summary Table.

Figure 63. INT_DIAG Register

7 6 5 4 3 2 1 0

RESERVED VMON2_PG_INTRESERVED VMON1_PG_INTRESERVED VANA_PG_INT

R/W-0h R-0h R/W-0h R-0h R/W-0h R-0h

Table 47. INT_DIAG Register Field Descriptions

Bit Field Type Reset Description

7-5 RESERVED R/W 0h

4 VMON2_PG_INT R 0h

3 RESERVED R/W 0h 2 VMON1_PG_INT R 0h

1 RESERVED R/W 0h 0 VANA_PG_INT R 0h

Latched status bit indicating that VMON2 powergood event has been detected.

Write 1 to clear.

Latched status bit indicating that VMON1 powergood event has been detected.

Write 1 to clear.

Latched status bit indicating that VANA powergood event has been detected.

Write 1 to clear.

LP87702-Q1

7.6.1.1.38 TOP_STATUS Register (Offset = 25h) [reset = 0h]

TOP_STATUS is shown in Figure 64 and described in Table 48. Return to Summary Table.

Figure 64. TOP_STATUS Register

7 6 5 4 3 2 1 0

RESERVED SYNC_CLK_STATTDIE_SD_STATTDIE_WARN_S

R-0h R-0h R-0h R-0h R-0h

TAT

Table 48. TOP_STATUS Register Field Descriptions

Bit Field Type Reset Description

7-4 RESERVED R 0h

3 SYNC_CLK_STAT R 0h

Product Folder Links: LP87702-Q1

Status bit indicating the status of external clock (CLKIN): 0 - External clock frequency is valid 1 - External clock frequency is not valid.

OVP_STAT

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Table 48. TOP_STATUS Register Field Descriptions (continued)

Bit Field Type Reset Description

2 TDIE_SD_STAT R 0h

1 TDIE_WARN_STAT R 0h

0 OVP_STAT R 0h

Status bit indicating the status of thermal shutdown: 0 - Die temperature below thermal shutdown level 1 - Die temperature above thermal shutdown level.

Status bit indicating the status of thermal warning: 0 - Die temperature below thermal warning level 1 - Die temperature above thermal warning level.

Status bit indicating the status of input overvoltage monitoring: 0 - Input voltage below overvoltage threshold level 1 - Input voltage above overvoltage threshold level.

7.6.1.1.39 BUCK_STATUS Register (Offset = 26h) [reset = 0h]

BUCK_STATUS is shown in Figure 65 and described in Table 49. Return to Summary Table.

Figure 65. BUCK_STATUS Register

7 6 5 4 3 2 1 0

BUCK1_STAT BUCK1_PG_S

TAT

R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

RESERVED BUCK1_ILIM_S

TAT

BUCK0_STAT BUCK0_PG_S

TAT

RESERVED BUCK0_ILIM_S

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TAT

Table 49. BUCK_STATUS Register Field Descriptions

Bit Field Type Reset Description

7 BUCK1_STAT R 0h

6 BUCK1_PG_STAT R 0h

5 RESERVED R 0h Reserved 4 BUCK1_ILIM_STAT R 0h

3 BUCK0_STAT R 0h

2 BUCK0_PG_STAT R 0h

1 RESERVED R 0h Reserved 0 BUCK0_ILIM_STAT R 0h

Status bit indicating the enable/disable status of BUCK1: 0 - BUCK1 converter is disabled 1 - BUCK1 converter is enabled.

Status bit indicating BUCK1 output voltage validity (raw status) 0 - BUCK1 output is not valid 1 - BUCK1 output is valid.

Status bit indicating BUCK1 current limit status (raw status) 0 - BUCK1 output current is below current limit threshold level 1 - BUCK1 output current is at current limit threshold level.

Status bit indicating the enable/disable status of BUCK0: 0 - BUCK0 converter is disabled 1 - BUCK0 converter is enabled.

Status bit indicating BUCK0 output voltage validity (raw status) 0 - BUCK0 output is not valid 1 - BUCK0 output is valid.

Status bit indicating BUCK0 current limit status (raw status) 0 - BUCK0 output current is below current limit threshold level 1 - BUCK0 output current is at current limit threshold level.

7.6.1.1.40 BOOST_STATUS Register (Offset = 27h) [reset = 0h]

BOOST_STATUS is shown in Figure 66 and described in Table 50. Return to Summary Table.

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Figure 66. BOOST_STATUS Register

7 6 5 4 3 2 1 0

RESERVED BOOST_STAT BOOST_PG_S

TAT

R-0h R-0h R-0h R-0h R-0h

RESERVED BOOST_ILIM_

Table 50. BOOST_STATUS Register Field Descriptions

Bit Field Type Reset Description

7-4 RESERVED R 0h

3 BOOST_STAT R 0h

2 BOOST_PG_STAT R 0h

1 RESERVED R 0h Reserved 0 BOOST_ILIM_STAT R 0h

Status bit indicating the enable/disable status of Boost: 0 - Boost converter is disabled 1 - Boost converter is enabled.

Status bit indicating Boost output voltage validity (raw status) 0 - Boost output is not valid 1 - Boost output is valid.

Status bit indicating Boost current limit status (raw status) 0 - Boost output current is below current limit threshold level 1 - Boost output current is at current limit threshold level.

7.6.1.1.41 DIAG_STATUS Register (Offset = 28h) [reset = 0h]

DIAG_STATUS is shown in Figure 67 and described in Table 51. Return to Summary Table.

LP87702-Q1

STAT

Figure 67. DIAG_STATUS Register

7 6 5 4 3 2 1 0

RESERVED VMON2_PG_S

TAT

R-0h R-0h R-0h R-0h R-0h R-0h

RESERVED VMON1_PG_S

TAT

RESERVED VANA_PG_ST

Table 51. DIAG_STATUS Register Field Descriptions

Bit Field Type Reset Description

7-5 RESERVED R 0h

4 VMON2_PG_STAT R 0h

3 RESERVED R 0h 2 VMON1_PG_STAT R 0h

1 RESERVED R 0h 0 VANA_PG_STAT R 0h

Status bit indicating VMON2 input voltage validity (raw status) 0 - VMON2 voltage is not valid 1 - VMON2 voltage is valid.

Status bit indicating VMON1 input voltage validity (raw status) 0 - VMON1 voltage is not valid 1 - VMON1 voltage is valid.

Status bit indicating VANA input voltage validity (raw status) 0 - VANA voltage is not valid 1 - VANA voltage is valid.

7.6.1.1.42 TOP_MASK_1 Register (Offset = 29h) [reset = 0h]

TOP_MASK_1 is shown in Figure 68 and described in Table 52. Return to Summary Table.

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Figure 68. TOP_MASK_1 Register

7 6 5 4 3 2 1 0

I_MEAS_MASK RESERVED SYNC_CLK_M

ASK

R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

RESERVED TDIE_WARN_

MASK

Table 52. TOP_MASK_1 Register Field Descriptions

Bit Field Type Reset Description

7 I_MEAS_MASK R/W 0h

6-4 RESERVED R/W 0h

3 SYNC_CLK_MASK R/W 0h

2 RESERVED R/W 0h 1 TDIE_WARN_MASK R/W 0h

0 RESERVED R/W 0h

Masking for load current measurement ready interrupt I_MEAS_INT in INT_TOP_1 register.

0 - Interrupt generated 1 - Interrupt not generated. (Default from OTP memory)

Masking for external clock detection interrupt SYNC_CLK_INT in INT_TOP_1 register:

0 - Interrupt generated 1 - Interrupt not generated. (Default from OTP memory)

Masking for thermal warning interrupt TDIE_WARN_INT in INT_TOP_1 register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect TDIE_WARN_STAT status bit in

TOP_STATUS register. (Default from OTP memory)

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RESERVED

7.6.1.1.43 TOP_MASK_2 Register (Offset = 2Ah) [reset = 1h]

TOP_MASK_2 is shown in Figure 69 and described in Table 53. Return to Summary Table.

Figure 69. TOP_MASK_2 Register

7 6 5 4 3 2 1 0

RESERVED RESET_REG_

R/W-0h R/W-1h

Table 53. TOP_MASK_2 Register Field Descriptions

Bit Field Type Reset Description

7-1 RESERVED R/W 0h

0 RESET_REG_MASK R/W 1h

Masking for register reset interrupt RESET_REG_INT in INT_TOP_2 register:

0 - Interrupt generated 1 - Interrupt not generated. (Default from OTP memory)

7.6.1.1.44 BUCK_MASK Register (Offset = 2Bh) [reset = 0h]

BUCK_MASK is shown in Figure 70 and described in Table 54. Return to Summary Table.

MASK

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Figure 70. BUCK_MASK Register

7 6 5 4 3 2 1 0

BUCK1_PGF_

MASK

R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

BUCK1_PGR_

MASK

RESERVED BUCK1_ILIM_

MASK

BUCK0_PGF_

MASK

BUCK0_PGR_

MASK

RESERVED BUCK0_ILIM_

Table 54. BUCK_MASK Register Field Descriptions

Bit Field Type Reset Description

7 BUCK1_PGF_MASK R/W 0h

6 BUCK1_PGR_MASK R/W 0h

5 RESERVED R/W 0h 4 BUCK1_ILIM_MASK R/W 0h

3 BUCK0_PGF_MASK R/W 0h

2 BUCK0_PGR_MASK R/W 0h

1 RESERVED R/W 0h 0 BUCK0_ILIM_MASK R/W 0h

Masking of powergood invalid detection for BUCK1 power good interrupt BUCK1_PG_INT in INT_BUCK register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_PG_STAT status bit in

BUCK_STATUS register. (Default from OTP memory)

Masking of powergood valid detection for BUCK1 power good interrupt BUCK1_PG_INT in INT_BUCK register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_PG_STAT status bit in

BUCK_STATUS register. (Default from OTP memory)

Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT in INT_BUCK register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_ILIM_STAT status bit in

BUCK_STATUS register. (Default from OTP memory)

Masking of powergood invalid detection for BUCK0 power good interrupt BUCK0_PG_INT in INT_BUCK register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK0_PG_STAT status bit in

BUCK_STATUS register. (Default from OTP memory)

Masking of powergood valid detection for BUCK0 power good interrupt BUCK0_PG_INT in INT_BUCK register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK0_PG_STAT status bit in

BUCK_STATUS register. (Default from OTP memory)

Masking for BUCK0 current monitoring interrupt BUCK0_ILIM_INT in INT_BUCK register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK0_ILIM_STAT status bit in

BUCK_STATUS register. (Default from OTP memory)

LP87702-Q1

MASK

7.6.1.1.45 BOOST_MASK Register (Offset = 2Ch) [reset = 0h]

BOOST_MASK is shown in Figure 71 and described in Table 55. Return to Summary Table.

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Figure 71. BOOST_MASK Register

7 6 5 4 3 2 1 0

RESERVED BOOST_PGF_

MASK

R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

BOOST_PGR_

MASK

RESERVED BOOST_ILIM_

Table 55. BOOST_MASK Register Field Descriptions

Bit Field Type Reset Description

7-4 RESERVED R/W 0h

3 BOOST_PGF_MASK R/W 0h

2 BOOST_PGR_MASK R/W 0h

1 RESERVED R/W 0h 0 BOOST_ILIM_MASK R/W 0h

Masking of powergood invalid detection for Boost power good interrupt BOOST_PG_INT in INT_BOOST register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BOOST_PG_STAT status bit in

BOOST_STATUS register. (Default from OTP memory)

Masking of powergood valid detection for Boost power good interrupt BOOST_PG_INT in INT_BOOST register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BOOST_PG_STAT status bit in

BOOST_STATUS register. (Default from OTP memory)

Masking for Boost current monitoring interrupt BOOST_ILIM_INT in INT_BOOST register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BOOST_ILIM_STAT status bit in

BOOST_STATUS register. (Default from OTP memory)

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MASK

7.6.1.1.46 DIAG_MASK Register (Offset = 2Dh) [reset = 0h]

DIAG_MASK is shown in Figure 72 and described in Table 56. Return to Summary Table.

Figure 72. DIAG_MASK Register

7 6 5 4 3 2 1 0

RESERVED VMON2_PGF_

MASK

R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

VMON2_PGR_

MASK

VMON1_PGF_

MASK

VMON1_PGR_

MASK

VANA_PGF_M

ASK

Table 56. DIAG_MASK Register Field Descriptions

Bit Field Type Reset Description

7-6 RESERVED R/W 0h

5 VMON2_PGF_MASK R/W 0h

Masking of VMON2 invalid detection for powergood interrupt VMON2_PG_INT in INT_DIAG register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect VMON2_PG_STAT status bit in

DIAG_STATUS register. (Default from OTP memory)

VANA_PGR_M

ASK

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Table 56. DIAG_MASK Register Field Descriptions (continued)

Bit Field Type Reset Description

4 VMON2_PGR_MASK R/W 0h

3 VMON1_PGF_MASK R/W 0h

2 VMON1_PGR_MASK R/W 0h

1 VANA_PGF_MASK R/W 0h

0 VANA_PGR_MASK R/W 0h

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Masking of VMON2 valid detection for powergood interrupt VMON2_PG_INT in INT_DIAG register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect VMON2_PG_STAT status bit in

DIAG_STATUS register. (Default from OTP memory)

Masking of VMON1 invalid detection for powergood interrupt VMON1_PG_INT in INT_DIAG register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect VMON1_PG_STAT status bit in

DIAG_STATUS register. (Default from OTP memory)

Masking of VMON1 valid detection for powergood interrupt VMON1_PG_INT in INT_DIAG register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect VMON1_PG_STAT status bit in

DIAG_STATUS register. (Default from OTP memory)

Masking of VANA invalid detection for powergood interrupt VANA_PG_INT in INT_DIAG register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect VANA_PG_STAT status bit in

DIAG_STATUS register. (Default from OTP memory)

Masking of VANA valid detection for powergood interrupt VANA_PG_INT in INT_DIAG register:

0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect VANA_PG_STAT status bit in

DIAG_STATUS register. (Default from OTP memory)

7.6.1.1.47 SEL_I_LOAD Register (Offset = 2Eh) [reset = 0h]

SEL_I_LOAD is shown in Figure 73 and described in Table 57. Return to Summary Table.

Figure 73. SEL_I_LOAD Register

7 6 5 4 3 2 1 0

RESERVED LOAD_CURRENT_BUCK_SELE

R/W-0h R/W-0h

Table 57. SEL_I_LOAD Register Field Descriptions

Bit Field Type Reset Description

7-2 RESERVED R/W 0h 1-0 LOAD_CURRENT_BUCK

_SELECT

R/W 0h

Product Folder Links: LP87702-Q1

Start the current measurement on the selected Buck converter: 0 - BUCK0 1 - BUCK1 2 - BUCK0 3 - BUCK1 The measurement is started when register is written.

Page 78

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

7.6.1.1.48 I_LOAD_2 Register (Offset = 2Fh) [reset = 0h]

I_LOAD_2 is shown in Figure 74 and described in Table 58. Return to Summary Table.

Figure 74. I_LOAD_2 Register

7 6 5 4 3 2 1 0

RESERVED BUCK_LOAD_

R-0h R-0h

Table 58. I_LOAD_2 Register Field Descriptions

Bit Field Type Reset Description

7-1 RESERVED R 0h

0 BUCK_LOAD_CURRENT_8R 0h

This register describes the MSB bit of the average load current on selected converter with a resolution of 20 mA per LSB and max 10 A current.

7.6.1.1.49 I_LOAD_1 Register (Offset = 30h) [reset = 0h]

I_LOAD_1 is shown in Figure 75 and described in Table 59. Return to Summary Table.

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CURRENT_8

Figure 75. I_LOAD_1 Register

7 6 5 4 3 2 1 0

BUCK_LOAD_CURRENT_7_0

R-0h

Table 59. I_LOAD_1 Register Field Descriptions

Bit Field Type Reset Description

7-0 BUCK_LOAD_CURRENT

_7_0

R 0h

This register describes 8 LSB bits of the average load current on selected converter with a resolution of 20 mA per LSB and max 10 A current.

7.6.1.1.50 FREQ_SEL Register (Offset = 31h) [reset = 0h]

FREQ_SEL is shown in Figure 76 and described in Table 60. Return to Summary Table.

Figure 76. FREQ_SEL Register

7 6 5 4 3 2 1 0

RESERVED BOOST_FREQ

_SEL

R/W-0h R/W-0h R/W-0h

BUCK_FREQ_SEL

Table 60. FREQ_SEL Register Field Descriptions

Bit Field Type Reset Description

7-3 RESERVED R/W 0h

2 BOOST_FREQ_SEL R/W 0h

Boost switching frequency: 0 - 2 MHz 1 - 4 MHz (Default from OTP memory)

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Table 60. FREQ_SEL Register Field Descriptions (continued)

Bit Field Type Reset Description

1-0 BUCK_FREQ_SEL R/W 0h

Buck0 and Buck1 switching frequency: 0x0 - 2 MHz 0x1 - 3 MHz 0x2 - 4 MHz 0x3 - 4 MHz (Default from OTP memory)

7.6.1.1.51 BOOST_ILIM_CTRL Register (Offset = 32h) [reset = 0h]

BOOST_ILIM_CTRL is shown in Figure 77 and described in Table 61. Return to Summary Table.

Figure 77. BOOST_ILIM_CTRL Register

7 6 5 4 3 2 1 0

RESERVED BOOST_ILIM

R/W-0h R/W-0h

Table 61. BOOST_ILIM_CTRL Register Field Descriptions

Bit Field Type Reset Description

7-2 RESERVED R/W 0h 1-0 BOOST_ILIM R/W 0h

Sets the current limit of Boost. 00 - 1.0 A 01 - 1.4 A 10 - 1.9 A 11 - 2.8 A (Default from OTP memory)

LP87702-Q1

7.6.1.1.52 ECC_STATUS Register (Offset = 33h) [reset = 0h]

ECC_STATUS is shown in Figure 78 and described in Table 62. Return to Summary Table.

Figure 78. ECC_STATUS Register

7 6 5 4 3 2 1 0

RESERVED DED SED

R-0h R-0h R-0h

Table 62. ECC_STATUS Register Field Descriptions

Bit Field Type Reset Description

7-2 RESERVED R 0h

1 DED R 0h

0 SED R 0h

OTP error correction status: 0 - No dual errors detected 1 - Dual errors detected and not corrected

OTP error correction status: 0 - No single errors detected 1 - Single errors detected and corrected

7.6.1.1.53 WD_DIS_CTRL_CODE Register (Offset = 34h) [reset = 0h]

WD_DIS_CTRL_CODE is shown in Figure 79 and described in Table 63. Return to Summary Table.

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Figure 79. WD_DIS_CTRL_CODE Register

7 6 5 4 3 2 1 0

WD_DIS_UNLOCK_CODE

R-0h

Table 63. WD_DIS_CTRL_CODE Register Field Descriptions

Bit Field Type Reset Description

7-0 WD_DIS_UNLOCK_CODER 0h

Unlocking WD_DIS_CTRL bit: Set WD_DIS_CTRL_LOCK=0 by writing 0x87, 0x65, 0x1B by 3 consecutive I2C write sequences to WD_DIS_CTRL_CODE register.

Locking WD_DIS_CTRL bit: Set WD_DIS_CTRL_LOCK=1 by writing anything to WD_DIS_CTRL_CODE register or write WD_LOCK=1.

Reading this address returns always 0x00. WD_DIS_CTRL can be unlocked only if WD_LOCK=0.

7.6.1.1.54 WD_DIS_CONTROL Register (Offset = 35h) [reset = 0h]

WD_DIS_CONTROL is shown in Figure 80 and described in Table 64. Return to Summary Table.

Figure 80. WD_DIS_CONTROL Register

7 6 5 4 3 2 1 0

RESERVED WD_DIS_CTRL

R/W-0h R-0h R/W-0h

_LOCK

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WD_DIS_CTRL

Table 64. WD_DIS_CONTROL Register Field Descriptions

Bit Field Type Reset Description

7-2 RESERVED R/W 0h

1 WD_DIS_CTRL_LOCK R 0h

0 WD_DIS_CTRL R/W 0h

Lock status for WD_DIS_CTRL bit. 0 - Not locked, WD_DIS_CTRL bit can be written. 1 - Locked, WD_DIS_CTRL bit is forced to 0 and it cannot be

written. Lock can be opened by writing 0x87, 0x65, 0x1B by 3 consecutive

I2C write sequences to WD_DIS_CTRL_CODE register if WD_LOCK=0. Lock can be closed by writing anything to WD_DIS_CTRL_CODE register or writing WD_LOCK=1.

Watchdog disable pin control. 0 - Watchdog cannot be disabled by WD_DIS pin. 1 - Watchdog can be disabled by WD_DIS pin. (Default from OTP memory) This bit can be written 1 only if WD_LOCK=0 and

WD_DIS_CTRL_LOCK=0.

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Page 81

SW_B0

VIN_B0

VIN_B1

VANA

FB_B0

VOUT0

LOAD

SDA (EN3)

SCL (EN2)

nINT

CLKIN (GPO2)

GNDs

EN1

SW_B1

FB_B1

VOUT1

PG0

VMON1

VMON2

PG1 (GPO1)

WDI WD_RESET

SW_BST

VOUT_BST

VOUT2

LOAD

GPO0

NRST

OUT0

OUT1

OUT2

IN0

IN1

ANA

LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP87702-Q1 is a power-management unit including a boost converter, two step-down converters, and three general-purpose digital output signals.

8.2 Typical Application

8.2.1 Design Requirements

Figure 81. LP87702-Q1 Typical Application

DESIGN PARAMETER EXAMPLE VALUE

Input voltage 3.3 V

Output voltages 1.8 V, 1.24 V, 5 V

Switching frequency 4 MHz

Table 65. Design Parameters

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8.2.2 Detailed Design Procedure

The performance of the LP87702-Q1 device depends greatly on the care taken in designing the printed circuit board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention should be given to decoupling the power supplies. Decoupling capacitors must be connected close to the device and between the power and ground pins to support high peak currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and output traces as short as possible, because trace inductance, resistance, and capacitance can easily become the performance limiting items. The separate buck converter power pins VIN_Bx are not connected together internally. The VIN_Bx power connections shall be connected together outside the package using power plane construction.

8.2.2.1 Application Components

8.2.2.1.1 Inductor Selection

The inductors are L0, L1, and L2are shown in the Typical Application. The inductance and DCR of the inductor affects the control loop of the buck and boost converter. It is recommended to use inductors or similar ones listed in Table 66. Pay attention to the saturation current and temperature rise current of the inductor. Check that the saturation current is higher than the peak current limit and the temperature rise current is higher than the maximum expected rms output current. For minimum effective inductance to ensure good performance refer to

Specifications. DC resistance of the inductor should be less than 0.05 Ω for good efficiency at high-current

condition. The inductor AC loss (resistance) also affects conversion efficiency. Higher Q factor at switching frequency usually gives better efficiency at light load to middle load. Shielded inductors are preferred as they radiate less noise.

Table 66. Recommended Inductors for Buck Converters

MANUFACTURER PART NUMBER VALUE DIMENSIONS

L × W x× H (mm)

MURATA DFE252012PD-R47M 0.47 µH (20%) 2.5 × 2 × 1.2 5.2 / 4.0

TDK TFM252012ALMAR47MTAA 0.47 µH (20%) 2.5 × 2 × 1.2 5.8 / 4.9

(1) Operating temperature range is up to 125°C including self temperature rise.

RATED DC CURRENT,

SAT

max / I

TEMP

max (A)

(1) (1)

DCR typ / max

(mΩ)

– / 27

19 / 24

Table 67. Recommended Inductor for Boost Converters

MANUFACTURER PART NUMBER VALUE DIMENSIONS

MURATA DFE252012PD-1R0M 1 µH (20%) 2.5 × 2 × 1.2 3.8 / 3.2

TDK TFM25201ALMA1R0MTAA 1 µH (20%) 2.5 × 2 × 1.2 4.2 / 3.7

(1) Operating temperature range is up to 125°C including self temperature rise.

L × W x× H (mm)

8.2.2.1.2 Buck Input Capacitor Selection

The input capacitors C

IN0

and C

are shown in the Typical Application. A ceramic input bypass capacitor of 10

IN1

RATED DC CURRENT,

SAT

max / I

TEMP

max (A)

(1) (1)

DCR typ / max

(mΩ)

_ / 42

35 / 42

μF is required for both converters. Place the input capacitor as close as possible to the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating improves the input voltage filtering. Use X7R type of capacitors, not Y5V or F. DC bias characteristics of the capacitors must also be considered. Minimum effective input capacitance to ensure good performance is 1.9 μF per buck input at maximum input voltage including tolerances and ambient temperature range. In addition there must be at least 22 μF of additional capacitance common for all the power input pins on the system power rail. See Table 68.

The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI.

Table 68. Recommended Buck Input Capacitors (X7R Dielectric)

MANUFACTURER PART NUMBER VALUE CASE SIZE DIMENSIONS LxWxH

Murata GCM21BR71A106KE22 10 µF (10%) 0805 2 × 1.25 × 1.25 10 V

Product Folder Links: LP87702-Q1

(mm)

VOLTAGE RATING

Page 83

LP87702-Q1

www.ti.com

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Table 68. Recommended Buck Input Capacitors (X7R Dielectric) (continued)

MANUFACTURER PART NUMBER VALUE CASE SIZE DIMENSIONS LxWxH

TDK CGA4J3X7S1A106K125AB 10 µF (10%) 0805 2 × 1.25 × 1.25 10 V

8.2.2.1.3 Buck Output Capacitor Selection

The output capacitor C

OUT0

and C

are shown in Typical Application. A ceramic local output capacitor of 22

OUT1

(mm)

VOLTAGE RATING

μF is required for both outputs. Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance for good performance is 15 μF per including the DC voltage roll-off, tolerances, aging and temperature effects.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. See Table 69.

POL capacitors can be used to improve load transient performance and to decrease the ripple voltage. A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as decreases the PFM switching frequency. Note that the output capacitor may be the limiting factor in the output voltage ramp, especially for very large (100-μF range) output capacitors. For large output capacitors, the output voltage might be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be longer. At shutdown the output voltage is discharged to 0.6 V level using forced-PWM operation. This can increase the input voltage if the load current is small and the output capacitor is large compared to input capacitor. Below 0.6 V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant.

Table 69. Recommended Buck Output Capacitors (X7R or X7T Dielectric)

MANUFACTURER PART NUMBER VALUE CASE SIZE DIMENSIONS LxWxH (mm) VOLTAGE RATING

Murata GCM31CR71A226KE02 22 µF (10%) 1206 3.2 × 1.6 × 1.6 10 V

TDK CGA5L1X7S1A226M160AC 22 µF (20%) 1206 3.2 × 1.6 × 1.6 10 V

8.2.2.1.4 Boost Input Capacitor Selection

A ceramic input capacitor of 10 μF is sufficient for most applications. Place the input capacitor close to the SW_BST pin of the device. Use X7R types, do not use Y5V or F. See Table 70.

Table 70. Recommended Boost Input Capacitors (X7R Dielectric)

MANUFACTURER PART NUMBER VALUE CASE SIZE DIMENSIONS LxWxH

(mm)

Murata GCM21BR71A106KE22 10 µF (10%) 0805 2.0 x 1.25 x 1.25 10 V

8.2.2.1.5 Boost Output Capacitor Selection

VOLTAGE

RATING

Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. Place the output capacitor as close as possible to the VOUT_BST pin and PGND_BST pin of the device. DC bias voltage characteristics of ceramic capacitors must be considered. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should be requested from them as part of the capacitor selection process. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to support load transients. See Table 71.

Table 71. Recommended Boost Output Capacitors (X7R or X7T Dielectric)

MANUFACTURER PART NUMBER VALUE CASE SIZE DIMENSIONS LxWxH (mm) VOLTAGE RATING

Murata GCM31CR71A226KE02 22 µF (10%) 1206 3.2 x 1.6 x 1.6 10 V

Product Folder Links: LP87702-Q1

Page 84

LIM_FWD_SET_OTP

(1.5...4.5 A, 0.5-A step)

Inductor current =

Forward current

L_AVG

= I

OUT

LIM_FWD_TYP

(+7.5%)

LIM_FWD_MAX

(+20%)

LIM_FWD_MIN

(-5%)

1 / f

OUT_MAX

< I

LIM_FWD_SET_OTP

± 1 A

to take current ripple,

inductor inductance

variation into account

IN(max) OUT

(V V ) D

f L

 u

OUT

IN(max)

V u K

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

8.2.2.1.6 Supply Filtering Components

www.ti.com

The VANA input is used to supply analog and digital circuits in the device. See Table 72 recommended components from for VANA input supply filtering.

Table 72. Recommended Supply Filtering Components

MANUFACTURER PART NUMBER VALUE CASE SIZE DIMENSIONS LxWxH

(mm)

Murata GCM188R71C104KA37D 100 nF (10%) 0603 1.6 x 0.8 x 0.8 16 V Murata GCM155R71C104KA55D 100 nF (10%) 0402 1.0 x 0.5 x 0.5 16 V

VOLTAGE RATING

8.2.3 Current Limit vs Maximum Output Current

For both the buck converters and the boost the current limit must be set high enough to account for inductor ripple current on top of the maximum output current. Forward current limit for the buck converters is set by BUCK0_ILIM, BUCK1_ILIM and for boost by BOOST_ILIM.

For the buck converter the inductor current ripple can be calculated using Equation 1 and Equation 2:

(1)

(2)

Example using Equation 1 and Equation 2:

V V

IN(max) OUT

= 5.5 V

= 1 V η = 0.75 fSW= 1.8 MHz L = 0.38 µH then D = 0.242 and ΔIL= 1.59 A

Peak current is half of the current ripple. If I

LIM_FWD_SET_OTP

is 3 A, the minimum forward current limit would be

2.85 A when taking the –5% tolerance into account. In this case the difference between set peak current and maximum load current = 0.795 A + 0.15 A = 0.945 A.

Figure 82. Current Limit vs Maximum Output Current

Product Folder Links: LP87702-Q1

Page 85

Output Current (A)

Output Voltage (V)

0 0.5 1 1.5 2 2.5 3 3.5

0.98

0.985

0.99

0.995

1.005

1.01

1.015

1.02

D005

Vin=3.3V, AUTO Vin=5.0V, AUTO

Input Voltage (V)

Output Voltage (V)

2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7

0.98

0.985

0.99

0.995

1.005

1.01

1.015

1.02

D009

Vout=1.0V; ILOAD=2.0A

Output Current (A)

Efficiency (%)

0.01 0.1 1 55

100

D003

Vout=1.0V, Vin=5.0V Vout=1.2V, Vin=5.0V Vout=1.8V, Vin=5.0V

Output Current (A)

Output Voltage (V)

0 0.5 1 1.5 2 2.5 3 3.5

0.98

0.985

0.99

0.995

1.005

1.01

1.015

1.02

D004

Vin=3.3V, FPWM Vin=5.0V, FPWM

Output Current (A)

Efficiency (%)

0.001 0.01 0.1 1 55

100

D001

Vin=3.3V, Vout=1.2V Vin=3.3V, Vout=1.8V Vin=5.0V, Vout=1.2V Vin=5.0V, Vout=1.8V

Output Current (A)

Efficiency (%)

0.01 0.1 1 55

100

D002

Vout=1.0V, Vin=3.3V Vout=1.2V, Vin=3.3V Vout=1.8V, Vin=3.3V

www.ti.com

8.2.4 Application Curves

Unless otherwise specified: VIN= 3.3 V, V

OUT_BUCK

(TOKO DFE252012PD-R47M), L2 = 1 µH (TFM252012ALMA1R0), C Measurements are done using connections in Figure 81.

= 1 V, V

OUT_BOOST

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

= 5 V, TA= 25°C, ƒSW-setting 4 MHz, L0 = L1 = 0.47 µH

OUT_BUCK

VIN= 3.3 V

, C

POL_BUCK

, and C

OUT_BOOST

= 22 µF.

Figure 83. Buck Efficiency in AUTO (PFM/PWM) Mode

VIN= 5 V

Figure 85. Buck Efficiency in Forced PWM Mode

Figure 84. Buck Efficiency in Forced PWM Mode

= 1 V

OUT

Figure 86. Buck Output Voltage vs Load Current in Forced

PWM Mode

= 1 V

OUT

Figure 87. Buck Output Voltage vs Load Current in AUTO

Mode

Figure 88. Buck Output Voltage vs Input Voltage in PWM

Product Folder Links: LP87702-Q1

Mode

Page 86

Temperature (C)

Output Voltage (V)

-40 -20 0 20 40 60 80 100 120 140

0.98

0.985

0.99

0.995

1.005

1.01

1.015

1.02

D010

Vin=3.3V; Vout=1.0V

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

www.ti.com

Unless otherwise specified: VIN= 3.3 V, V

OUT_BUCK

= 1 V, V

OUT_BOOST

(TOKO DFE252012PD-R47M), L2 = 1 µH (TFM252012ALMA1R0), C Measurements are done using connections in Figure 81.

Figure 89. Buck Output Voltage vs Temperature

= 5 V, TA= 25°C, ƒSW-setting 4 MHz, L0 = L1 = 0.47 µH

OUT

, C

POL_BUCK

= 0 A

OUT_BUCK

Figure 90. Buck Start-up with EN1, Forced-PWM

, and C

OUT_BOOST

= 22 µF.

= 1 Ω

LOAD

Figure 91. Buck Start-up with EN1, Forced-PWM

= 1.2 V I

OUT

Figure 93. Buck Output Voltage Ripple, Forced-PWM Mode

OUT

= 500 mA

LOAD

Figure 92. Buck Shutdown with EN1, Forced-PWM

OUT

Figure 94. Buck Output Voltage Ripple, PFM Mode

Product Folder Links: LP87702-Q1

= 1 Ω

= 1.2 V I

OUT

= 10 mA

Page 87

www.ti.com

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Unless otherwise specified: VIN= 3.3 V, V

OUT_BUCK

= 1 V, V

OUT_BOOST

(TOKO DFE252012PD-R47M), L2 = 1 µH (TFM252012ALMA1R0), C Measurements are done using connections in Figure 81.

= 1.2 V

OUT

Figure 95. Buck Transient from PFM-to-PWM Mode

= 5 V, TA= 25°C, ƒSW-setting 4 MHz, L0 = L1 = 0.47 µH

, C

OUT

POL_BUCK

= 1.2 V

OUT_BUCK

Figure 96. Buck Transient from PWM-to-PFM Mode

, and C

OUT_BOOST

= 22 µF.

= 0 A → 3 A → 0 A TR= TF= 1 µs V

OUT

Figure 97. Buck Transient Load Step Response, Forced-

PWM Mode

= 0 A → 3 A → 0 A TR= TF= 1 µs V

OUT

Figure 99. Buck Transient Load Step Response, Auto

Mode

Product Folder Links: LP87702-Q1

OUT

= 1 V

= 0 A → 3 A → 0 A TR= TF= 1 µs V

OUT

Figure 98. Buck Transient Load Step Response, Forced-

PWM Mode

= 1.2 V

OUT

Figure 100. Buck Transient Load Step Response, Auto

Mode

OUT

= 1.2 V

Page 88

Input Voltage (V)

Output Voltage (V)

2.8 3 3.2 3.4 3.6 3.8 4

4.97

4.98

4.99

5.01

5.02

5.03

5.04

D008

Vout=5.0V, ILoad=0.1A

Output Current (A)

Efficiency (%)

0.001 0.01 0.1 1

100

D006

Vout=5.0V, Vin=3.3V

Output Current (A)

Output Voltage (V)

0 0.1 0.2 0.3 0.4 0.5 0.6

4.85

4.9

4.95

5.05

5.1

5.15

5.2

D007

Vout=5.0V, Vin=3.3V

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

www.ti.com

Unless otherwise specified: VIN= 3.3 V, V

OUT_BUCK

= 1 V, V

OUT_BOOST

(TOKO DFE252012PD-R47M), L2 = 1 µH (TFM252012ALMA1R0), C Measurements are done using connections in Figure 81.

Figure 101. Boost Efficiency Figure 102. Boost Output Voltage vs Load Current

= 5 V, TA= 25°C, ƒSW-setting 4 MHz, L0 = L1 = 0.47 µH

OUT_BUCK

, C

POL_BUCK

, and C

OUT_BOOST

= 22 µF.

= 0.1 A

OUT

Figure 103. Boost Output Voltage vs Input Voltage

= 50 Ω

LOAD

Figure 105. Boost Start-up With EN1, Forced-PWM

OUT

Figure 104. Boost Start-up With EN1, Forced-PWM

LOAD

Figure 106. Boost Shutdown With EN1, Forced-PWM

Product Folder Links: LP87702-Q1

= 0 A

= 50 Ω

Page 89

www.ti.com

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Unless otherwise specified: VIN= 3.3 V, V

OUT_BUCK

= 1 V, V

OUT_BOOST

(TOKO DFE252012PD-R47M), L2 = 1 µH (TFM252012ALMA1R0), C Measurements are done using connections in Figure 81.

= 0.1 A

OUT

Figure 107. Boost Output Voltage Ripple

OUT

= 5 V, TA= 25°C, ƒSW-setting 4 MHz, L0 = L1 = 0.47 µH

OUT_BUCK

, C

POL_BUCK

= 0 A → 0.25 A → 0 A TR= TF= 1 µs

Figure 108. Boost Transient Load Step Response

, and C

OUT_BOOST

= 22 µF.

Product Folder Links: LP87702-Q1

Page 90

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

www.ti.com

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.8 V and 5.5 V. This input supply must be well regulated and able to withstand maximum input current and maintain stable voltage without voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the input current transient does not cause too high drop in the LP87702-Q1 supply voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the LP87702-Q1 additional bulk capacitance may be required in addition to the ceramic bypass capacitors.

10 Layout

10.1 Layout Guidelines

The high frequency and large switching currents of the LP87702-Q1 make the choice of layout important. Good power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and current regulation across its intended operating voltage and current range.

1. Place CINas close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the VINtrace wide and thick

to avoid IR drops. The trace between the positive node of the input capacitor and device VIN_Bx pin(s) as well as the trace between the negative node of the input capacitor and power PGND_Bx pin(s) must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor parasitic inductance on these traces must be kept as tiny as possible for proper device operation.

2. The output filter, consisting of L and C

voltage. It should be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Route the traces between the LP87702-Q1's output capacitors and the load's input capacitors direct and wide to avoid losses due to the IR drop.

3. Input for analog blocks (VANA and AGND) should be isolated from noisy signals. Connect VANA directly to a

quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VANA pin.

4. If remote voltage sensing can be used for the load, connect the device feedback pins FB_Bx to the

respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid both capacitive as well as inductive coupling by keeping the sense lines short and direct. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible.

5. PGND_Bx, VIN_Bx and SW_Bx should be routed on thick layers. They must not surround inner signal layers

which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.

Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (R (R

) thermal resistances and thereby reduces the device junction temperature, TJ. TI strongly recommends

θJB

performing a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software.

, converts the switching signal at SW_Bx to the noiseless output

OUT

) and junction-to-board

θJA

Product Folder Links: LP87702-Q1

Page 91

GND

nINT

FB_B0

FB_B1

WDI

AGND

VANA

WD_RESET

PGND_B1

EN1

SCL (EN2)

PGND_B0

SDA (EN3)

CLKIN (GPO2)

PGND_B0

SW_B0

VIN_B0

VMON2

VIN_B0

PG0

VMON1

PGDN_BST

NRST

GPO0

SW_B1

VIN_B1

SW_B1

AGND

GND

VOUT0 VOUT1

VIN

GND

VIN GND

IN0

IN1

OUT2

OUT0

OUT1

GND

PG1 (GPO1)

PGND_B1

SW_BST

VOUT_BST

VIN

GND

www.ti.com

10.2 Layout Example

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Figure 109. LP87702-Q1 Board Layout Example

Product Folder Links: LP87702-Q1

Page 92

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

www.ti.com

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, go to the device product folder on ti.com. In the upper right corner, click Alert me to register for a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LP87702-Q1

Page 93

PACKAGE OPTION ADDENDUM

www.ti.com

16-Apr-2021

PACKAGING INFORMATION

Orderable Device Status

LP877020RHBRQ1 ACTIVE VQFN RHB 32 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LP8770Q

LP87702DRHBRQ1 ACTIVE VQFN RHB 32 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LP8770Q

LP87702DRHBTQ1 ACTIVE VQFN RHB 32 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LP8770Q

LP87702KRHBRQ1 ACTIVE VQFN RHB 32 3000 RoHS & Green SN Level--- -40 to 125 LP8770Q

LP87702KRHBTQ1 ACTIVE VQFN RHB 32 250 RoHS & Green SN Level--- -40 to 125 LP8770Q

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

20 RHB

2D RHB

2K RHB

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Samples

Addendum-Page 1

Page 94

PACKAGE OPTION ADDENDUM

www.ti.com

16-Apr-2021

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LP87702-Q1 :

Catalog : LP87702

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

Page 95

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

LP877020RHBRQ1 VQFN RHB 32 3000 330.0 12.4 5.25 5.25 1.1 8.0 12.0 Q2 LP87702DRHBRQ1 VQFN RHB 32 3000 330.0 12.4 5.25 5.25 1.1 8.0 12.0 Q2 LP87702DRHBTQ1 VQFN RHB 32 250 180.0 12.4 5.25 5.25 1.1 8.0 12.0 Q2 LP87702KRHBRQ1 VQFN RHB 32 3000 330.0 12.4 5.25 5.25 1.1 8.0 12.0 Q2 LP87702KRHBTQ1 VQFN RHB 32 250 180.0 12.4 5.25 5.25 1.1 8.0 12.0 Q2

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 96

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP877020RHBRQ1 VQFN RHB 32 3000 367.0 367.0 38.0

LP87702DRHBRQ1 VQFN RHB 32 3000 367.0 367.0 38.0

LP87702DRHBTQ1 VQFN RHB 32 250 213.0 191.0 35.0

LP87702KRHBRQ1 VQFN RHB 32 3000 367.0 367.0 38.0

LP87702KRHBTQ1 VQFN RHB 32 250 213.0 191.0 35.0

Pack Materials-Page 2

Page 97

GENERIC PACKAGE VIEW

VQFN - 1 mm max heightRHB 32

5 x 5, 0.5 mm pitch

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details.

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4224745/A

Page 98

PACKAGE OUTLINE

PIN 1 INDEX AREA

0.9 MAX

0.05

0.00

28X 0.5

SCALE 3.000

VQFN - 0.9 mm max heightRHB0032N

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

2X 3.5

3.45 0.1 16

5.1

4.9

EXPOSED THERMAL PAD

(0.05)

SEATING PLANE

0.08 C

SECTION A-A

A-A 30.000

TYPICAL

0.1 MIN

(0.2) TYP

SYMM

0.3

32X

0.2

0.1 C A B

0.05

4222893/B 02/2018

3.5

PIN 1 ID

(OPTIONAL)

SYMM

32X

0.5

0.3

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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Page 99

32X (0.6)

EXAMPLE BOARD LAYOUT

VQFN - 0.9 mm max heightRHB0032N

PLASTIC QUAD FLATPACK - NO LEAD

( 3.45)

SYMM

32X (0.25)

28X (0.5)

( 0.2) TYP

(R0.05)

TYP

VIA

0.07 MAX

ALL AROUND

(1.475)

(4.8)

(1.475)

SYMM

(4.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

METAL EDGE

SOLDER MASK OPENING

EXPOSED METAL

SOLDER MASK OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED

METAL

METAL UNDER SOLDER MASK

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222893/B 02/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

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Page 100

(R0.05) TYP

32X (0.6)

EXAMPLE STENCIL DESIGN

VQFN - 0.9 mm max heightRHB0032N

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

32X (0.25)

28X (0.5)

METAL TYP

SYMM

(0.845)

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

SCALE:20X

4222893/B 02/2018

www.ti.com

Datasheet LP87702-Q1 Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 I2C Serial Bus Timing Parameters

6.7 Typical Characteristics

7 Detailed Description

7.1 Overview

7.2 Functional Block Diagram

7.3 Feature Descriptions

7.3.1 Step-Down DC/DC Converters

7.3.1.1 Overview

7.3.1.2 Transition Between PWM and PFM Modes

7.3.1.3 Buck Converter Load Current Measurement

7.3.2 Boost Converter

7.3.3 Spread-Spectrum Mode

7.3.4 Sync Clock Functionality

7.3.5 Power-Up

7.3.6 Buck and Boost Control

7.3.6.1 Enabling and Disabling Converters

7.3.6.2 Changing Buck Output Voltage

7.3.7 Enable and Disable Sequences

7.3.8 Window Watchdog

7.3.9 Device Reset Scenarios

7.3.10 Diagnostics and Protection Features

7.3.10.1 Voltage Monitorings

7.3.10.2 Interrupts

7.3.10.3 Power-Good Information to Interrupt and PG0 and PG1 Pins

7.3.10.4 Warning Interrupts for System Level Diagnostics

7.3.10.5 Protections Causing Converter Disable

7.3.10.6 Protections Causing Device Power Down

7.3.11 OTP Error Correction

7.3.12 Operation of GPO Signals

7.3.13 Digital Signal Filtering

7.4 Device Functional Modes

7.4.1 Modes of Operation

7.5 Programming

7.5.1 I2C-Compatible Interface

7.5.1.1 Data Validity

7.5.1.2 Start and Stop Conditions

7.5.1.3 Transferring Data

7.5.1.4 I2C-Compatible Chip Address

7.5.1.5 Auto Increment Feature

7.6 Register Maps

7.6.1 Register Descriptions

7.6.1.1 LP8770_map Registers

8 Application and Implementation

8.1 Application Information

8.2 Typical Application

8.2.1 Design Requirements

8.2.2 Detailed Design Procedure

8.2.2.1 Application Components

8.2.3 Current Limit vs Maximum Output Current

8.2.4 Application Curves

9 Power Supply Recommendations

10 Layout

10.1 Layout Guidelines

10.2 Layout Example

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

11.2 Receiving Notification of Documentation Updates

11.3 Community Resources

11.4 Trademarks

11.5 Electrostatic Discharge Caution

11.6 Glossary

12 Mechanical, Packaging, and Orderable Information