Datasheet LP62S4096EX-70LLI, LP62S4096EX-55LLI, LP62S4096EV-70LLI, LP62S4096EU-70LLI, LP62S4096EU-55LLI Datasheet (AMIC)
...Page 1
LP62S4096E-I Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Document Title
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History Issue Date Remark
2.0 Change VCCmax from 3.3V to 3.6V January 25, 2002
Add product family and 55ns specification
(January, 2002, Version 2.0) 1 AMIC Technology, Inc.
Page 2
LP62S4096E-I Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.7V to 3.6V
n Access times: 55ns / 70ns (max.)
n Current:
Very low power version: Operating: 30mA (max.)
Standby: 10µA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 32-pin TSOP/TSSOP 36-ball CSP package
General Description
The LP62S4096E-I is a low operating current 4,194,304-bit
static random access memory organized as 524,288
words by 8 bits and operates on a low power supply range:
2.7V to 3.3V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2V.
n CE2 pin for CSP package only
Product Family
Product Family
LP62S4096E-I
Operating
Temperature
-40°C ~ +85°C
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
VCC
Range
Speed
2.7V~3.6V 55ns / 70ns
Data Retention
(ICCDR, Typ.)
0.08µA 0.3µA
Power Dissipation
Standby
(ISB1, Typ.)
Operating
(ICC2, Typ.)
5mA
Package
Type
32L TSOP
32L TSSOP
36B CSP
Pin Configurations
nn TSOP/(TSSOP) nn CSP (Chip Size Package)
36-pin Top View
16
(LP62S4096EX-I)
17 32
Pin No.
1 2A93 4 5 6 7 8 9 10 11 12 13 14
Pin
Name
Pin No.
Pin
Name
A8 A13 A17 A15 VCC A18
A11 WE
A3 A2 A1 A0 I/O1 I/O2 GND I/O4 I/O5 I/O6 I/O7
I/O
(January, 2002, Version 2.0) 2 AMIC Technology, Inc.
1
LP62S4096EV-I
A16 A14 A12 A7 A6
3
654321
A7
A15
A8
I/O1
I/O2
VCC
GND
I/O3
I/O4
A0
A
B
C
D
E
F
G
H
15 16
A5 A4
302928272625242219 2120 231817
31 32
I/O8
CE1
A10 OE
A1A2CE2
I/O5
I/O6
GND
VCC
I/O7
I/O8
A9 A10OEA11
A3 A6
WE
A4
NC A5
A18 A17
CE1
A16
A12 A13 A14
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LP62S4096E-I Series
Block Diagram
A0
A16
A17
A18
I/O1
I/O8
CE1
CE2
OE
WE
Pin Description
Symbol Description
A0 - A18
Address Inputs
CONTROL
CIRCUIT
ROW
DECODER
INPUT DATA
CIRCUIT
VCC
GND
1024 X 4096
MEMORY ARRAY
COLUMN I/O
Recommended DC Operating Conditions
(TA = -40°C to + 85°C)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 2.7 3.0 3.6 V
I/O1 - I/O8 Data Input/Outputs
GND Ground 0 0 0 V
GND Ground
VIH Input High Voltage 2.2 -
CE1, CE2
OE
WE
Chip Enable
Output Enable
Write Enable
VIL Input Low Voltage -0.3 0 +0.6 V
CL Output Load - - 30 pF
TTL Output Load - - 1 -
VCC Power Supply
(January, 2002, Version 2.0) 3 AMIC Technology, Inc.
VCC +
0.3
V
Page 4
LP62S4096E-I Series
Absolute Maximum Ratings*
VCC to GND ------------------------------------- -0.5V to + 4.0V
IN, IN/OUT Volt to GND--------------- -0.5V to VCC + 0.5V
Operating Temperature, Topr -------------- -40°C to + 85°C
Storage Temperature, Tstg --------------- -55°C to + 125°C
Temperature Under Bias, Tbias ----------- -10°C to + 85°C
Power Dissipation, PT ---------------------------------------0.7W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol Parameter
Min. Typ. Max.
ILI
ILO
ICC Active Power Supply Current - - 5 mA
Input Leakage Current - - 1
Output Leakage Current
LP62S4096E-55LLI / 70LLI
-
-
1
Unit Conditions
µA
µA
VIN = GND to VCC
CE1= VIH , CE2= VIL or
OE = VIH WE =VIL
VI/O = GND to VCC
CE1= VIL, CE2= VIH II/O = 0mA
ICC1 Dynamic Operating Current - 20 30 mA
ICC2 Dynamic Operating Current
ISB Standby Power - - 1 mA
ISB1 Supply Current - 0.3 10
VOL Output Low Voltage - - 0.4 V IOL = 2.1mA
VOH Output High Voltage 2.2 - - V IOH = -1.0mA
-
5 15
mA
Min. Cycle, Duty = 100%,
CE1 = VIL CE2= VIH, II/O = 0mA
CE1= VIL, CE2= VIH, VIH = VCC
VIL = 0V, f = 1MHZ
II/O = 0mA
VCC ≤ 3.3V
CE1= VIH, CE2= VIL
VCC ≤ 3.3V
µA
CE1≥ VCC - 0.2V, or CE2 ≤ 0.2V
VIN ≤ 0.2V
(January, 2002, Version 2.0) 4 AMIC Technology, Inc.
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LP62S4096E-I Series
WE
Truth Table
Mode
Standby H X X X High Z ISB, ISB1
Standby X L X X High Z ISB, ISB1
Output Disable L H H H High Z ICC, ICC1, ICC2
Read L H L H DOUT ICC, ICC1, ICC2
Write L H X L DIN ICC, ICC1, ICC2
Note: X = H or L
CE1
CE2
OE
I/O Operation Supply Current
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance 6 pF VIN = 0V
CI/O* Input/Output Capacitance 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V)
Symbol Parameter LP62S4096E-55LLI LP62S4096E-70LLI Unit
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 - 70 - ns
tAA Address Access Time - 55 - 70 ns
tACE1, tACE2 Chip Enable Access Time - 55 - 70 ns
tOE Output Enable to Output Valid - 30 - 35 ns
tCLZ1, tCLZ2 Chip Enable to Output in Low Z 10 - 10 - ns
tOLZ Output Enable to Output in Low Z 5 - 5 - ns
tCHZ1, tCHZ2 Chip Disable to Output in High Z 0 20 0 25 ns
tOHZ Output Disable to Output in High Z 0 20 0 25 ns
tOH Output Hold from Address Change 5 - 5 - ns
(January, 2002, Version 2.0) 5 AMIC Technology, Inc.
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LP62S4096E-I Series
AC Characteristics (continued)
Symbol Parameter
LP62S4096E-55LLI LP62S4096E-70LLI
Min. Max. Min. Max.
Write Cycle
tWC Write Cycle Time 55 - 70 - ns
tCW1 Chip Enable to End of Write 50 - 60 - ns
tAS Address Setup Time 0 - 0 - ns
tAW Address Valid to End of Write 50 - 60 - ns
tWP Write Pulse Width 40 - 50 - ns
tWR Write Recovery Time 0 - 0 - ns
tWHZ Write to Output in High Z 0 25 0 25 ns
tDW Data to Write Time Overlap 25 - 30 - ns
tDH Data Hold from Write Time 0 - 0 - ns
tOW Output Active from End of Write 5 - 5 - ns
Unit
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
Timing Waveforms Read Cycle 1
Address
OE
CE1
CE2
DOUT
(1)
tRC
tAA
tOH
tOHZ
tCHZ1 , tCHZ2
5
tACE1 , tACE2
tCLZ1 , tCLZ2
tOLZ
tOE
5
(January, 2002, Version 2.0) 6 AMIC Technology, Inc.
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LP62S4096E-I Series
Timing Waveforms (continued)
Read Cycle 2
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
Read Cycle 3
CS1
CS2
DOUT
(1, 3, 4)
tCLZ1 , tCLZ2
tACS1 , tACS2
tCHZ1 , tCHZ2
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE1 = VIL or CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low or CE2 transition high.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(January, 2002, Version 2.0) 7 AMIC Technology, Inc.
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LP62S4096E-I Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
Address
(6)
tWC
CE1
CE2
DOUT
WE
DIN
tAW
tcw1 ,tcw2
(4)
1
tAS
7
tWHZ
tWP
2
tDW
tWR
3
tDH
7
tOW
(January, 2002, Version 2.0) 8 AMIC Technology, Inc.
Page 9
LP62S4096E-I Series
Write Cycle 2
(6)
(Chip Enable Controlled)
tWC
Address
CE1
CE2
WE
DOUT
DIN
1
t
AS
(4)
tAW
tWHZ
tCW1 , tCW2
t
WP
7
2
tDW
tWR
3
t
DH
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1 or high CE2 , and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low WE going high to the end of the
Write cycle.
4. If the CE1 low or CE2 high transition occurs simultaneously with the WE low transition or after the WE transition
, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE level is high or low.
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(January, 2002, Version 2.0) 9 AMIC Technology, Inc.
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LP62S4096E-I Series
AC Test Conditions
Input Pulse Levels 0.4V to 2.4V
Input Rise and Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
TTL
CL
30pF
* Including scope and jig. * Including scope and jig.
CL
TTL
5pF
Figure 1. Output Load Figure 2. Output Load for tCLZ,
tOHZ, tOL, tCHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -40°C to 85°C)
Symbol Parameter Min. Typ. Max. Unit Conditions
VDR VCC for Data Retention 2.0 - 3.6 V
ICCDR Data Retention Current LL-Version - 0.08 3*
CE1≥ VCC - 0.2V, or
CE2 ≤ 0.2V
VCC = 2.0V,
CE1≥ VCC - 0.2V, or
µA
CE2 ≤ 0.2V
VIN ≤ 0V
tCDR Chip Disable to Data Retention Time 0 - - ns
tR Operation Recovery Time tRC - - ns See Retention Waveform
tVR VCC Rising Time from Data Retention Voltage to
5 - - ms
Operating Voltage
* LP62S4096E-55LLI / 70LLI ICCDR: max. 1µA at TA = 0°C to + 40°C
(January, 2002, Version 2.0) 10 AMIC Technology, Inc.
Page 11
LP62S4096E-I Series
CE1
Low VCC Data Retention Waveform (1) (
Controlled)
DATA RETENTION MODE
VCC
CE1
2.7V
t
CDR
V
IH
CE1
VDR ≥ 2V
≥
VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
2.7V
tCDR
VIL
VDR ≥ 2V
0.2VCE2≤
2.7V
t
R
tVR
V
IH
2.7V
tR
tVR
VIL
Ordering Information
Part No. Access Time(ns)
Operating Current
Max.(mA)
LP62S4096EV-55LLI 55 30 10 32L TSOP
LP62S4096EX-55LLI 55 30 10 32L TSSOP
LP62S4096EU-55LLI 55 30 10 36L CSP
LP62S4096EV-70LLI 70 30 10 32L TSOP
LP62S4096EX-70LLI 70 30 10 32L TSSOP
LP62S4096EU-70LLI 70 30 10 36L CSP
Standby Current
Max.(uA)
Package
(January, 2002, Version 2.0) 11 AMIC Technology, Inc.
Page 12
LP62S4096E-I Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm
D
e
0.25
BSC
Detail "A"
°12.0
LE
b
A
θ
L
0.10(0.004) M
A2
E
HD
Detail "A"
y
D
c
GAUGE PLANE
A1
S
Symbol Dimensions in inches Dimensions in mm
A 0.047 Max. 1.20 Max.
A1 0.004±0.002 0.10±0.05
A2 0.039±0.002 1.00±0.05
b 0.008±0.001 0.20±0.03
c 0.006±0.001 0.15±0.02
D 0.724±0.004 18.40±0.10
E 0.315±0.004 8.00±0.10
e 0.020 TYP. 0.50 TYP.
HD 0.787±0.007 20.00±0.20
L 0.020±0.004 0.50±0.10
LE 0.031 TYP. 0.80 TYP.
S 0.0167 TYP. 0.425 TYP.
Y 0.004 Max. 0.10 Max.
θ 0° ~ 6° 0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
(January, 2002, Version 2.0) 12 AMIC Technology, Inc.
Page 13
LP62S4096E-I Series
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm
e
0.25
BSC
Detail "A"
Detail "A"
°12.0
A
θ
L
LE
b
E
0.10MM
D
SEATING PLANE
A2
c
GAUGE PLANE
A1
D1
D
Detail "A"
S
Symbol Dimensions in inches Dimensions in mm
A 0.049 Max. 1.25 Max.
A1 0.002 Min. 0.05 Min.
A2 0.039±0.002 1.00±0.05
b 0.008±0.001 0.20±0.03
c 0.006±0.0003 0.15±0.008
E 0.315±0.004 8.00±0.10
e 0.020 TYP. 0.50 TYP.
D 0.528±0.008 13.40±0.20
D1 0.465±0.004 11.80±0.10
L 0.02±0.008 0.50±0.20
LE 0.0266 Min. 0.675 Min.
S 0.0109 TYP. 0.278 TYP.
y 0.004 Max. 0.10 Max.
θ 0° ~ 6° 0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
(January, 2002, Version 2.0) 13 AMIC Technology, Inc.
Page 14
LP62S4096E-I Series
Package Information
36LD CSP (6 x 8 mm) Outline Dimensions unit: mm
TOP VIEW
Ball*A1 CORNER
1 2 3 4 5 6
A
B
C
D
E
F
G
H
SIDE VIEW
A2
// 0.25 C
C
SEATING PLANE
(0.36)
Symbol
0.10 C
A
A1
Dimensions in mm
MIN.
NOM. MAX.
e
1
E
E
B e
A
0.20(4X)
BOTTOM VIEW
Ball#A1 CORNER
S
0.10 C
C
0.25SA B
b (36X)
D1
D
123456
A
B
C
D
E
F
G
H
A 1.00 1.10 1.20
A1 0.16 0.21 0.26
A2 0.48 0.53 0.58
D 5.80 6.00 6.20
E 7.80 8.00 8.20
D1 --- 3.75 ---
E1 --- 5.25 ---
e --- 0.75 ---
b 0.25 0.30 0.35
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.25mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.25mm (NSMD)
(January, 2002, Version 2.0) 14 AMIC Technology, Inc.
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