n Power supply range: 2.7V to 3.3V
n Access times: 70/100 ns (max.)
n Current:
Low power version: Operating: 30mA (max.)
Standby: 50µA (max.)
Very low power version: Operating: 30mA (max.)
Standby: 10µA (max.)
n Full static operation, no clock or refreshing required
General Description
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
n Data retention voltage: 2V (min.)
n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm)
and 36-pin CSP packages
The LP62S2048-I is a low operating current 2,097,152-bit
static random access memory organized as 262,144
words by 8 bits and operates on a low power supply
range: 2.7V to 3.3V. It is built using AMIC's high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
structures.
Pin Configurations
nn SOP nn TSOP/(TSSOP) nn CSP (Chip Size Package)
36-pin Top View
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O
I/O3
2
1
2
3
4
5
LP62S2048M-I
6
7
8
9
10
11
12
13
14
15
1617
VCC
32
A15
31
CE2
30
WE
29
A13
28
A8
27
A9
26
A11
25
OE
24
A10
23
22
CE1
8
I/O
21
I/O7
20
I/O6
19
I/O5
18
I/O4GND
16
(LP62S2048X-I)
17
1
LP62S2048V-I
32
A0
A
I/O5
B
I/O6
C
GND
D
VCC
E
I/O7
F
I/O8
G
A9A10OEA11
H
A1A2CE2
WE
NCA5
NCA17
CE1
A7
A15
A8
I/O1
I/O2
VCC
GND
I/O3
I/O4
A3A6
A4
A16
A12 A13 A14
654321
Pin No.
1 2A93 4 5 6 7 8 9 10 11 12 13 14
Pin
Name
Pin No.
Pin
Name
A8 A13CE2 A15 VCC A17
A11WE
3
A3 A2 A1 A0 I/O1I/O2GND I/O4I/O5I/O6I/O
I/O
A16 A14 A12 A7 A6
7
15 16
A5 A4
3029282726252422192120231817
31 32
I/O
8
CE1
A10 OE
(August, 2001, Version 1.0) 1 AMIC Technology, Inc.
Page 2
LP62S2048-I Series
Block Diagram
A0
A15
A16
A17
I/O1
I/O8
CE2
CE1
OE
WE
Pin Description - SOP
CONTROL
CIRCUIT
ROW
DECODER
INPUT DATA
CIRCUIT
VCC
GND
1024 X 2048
MEMORY ARRAY
COLUMN I/O
Pin Descriptions - TSOP/TSSOP
Pin No. Symbol Description
1 - 12, 23,
25 - 28, 31
13 - 15,
17 - 21
A0 - A17 Address Inputs
I/O1- I/O8Data Input/Outputs
16 GND Ground
22
24
29
CE1
OE
WE
Chip Enable
Output Enable
Write Enable
30 CE2 Chip Enable
32 VCC Power Supply
Pin No. Symbol Description
1 - 4, 7,
9 - 20, 31
5
A0 - A17 Address Inputs
WE
Write Enable
6 CE2 Chip Enable
8 VCC Power Supply
9 NC No Connection
21 - 23,
25 - 29
I/O1- I/O8Data Input/Outputs
24 GND Ground
30
32
CE1
OE
Chip Enable
Output Enable
(August, 2001, Version 1.0) 2 AMIC Technology, Inc.
Page 3
LP62S2048-I Series
Pin Description - CSP
Symbol Description Symbol Description
A0 - A17 Address Inputs NC No Connection
WE
OE
CE1
CE2 Chip Enable -- --
Write Enable I/O1- I/O8Data Input/Output
Output Enable VCC Power Supply
Chip Enable GND Ground
Recommended DC Operating Conditions
(TA = -40°C to + 85°C)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 2.7 3.0 3.3 V
GND Ground 0 0 0 V
VIHInput High Voltage 2.0 - VCC + 0.3 V
VILInput Low Voltage -0.3 - +0.6 V
CLOutput Load - - 30 pF
TTL Output Load - - 1 -
(August, 2001, Version 1.0) 3 AMIC Technology, Inc.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.3V, GND = 0V)
Symbol Parameter
Min. Max. Min. Max.
ILI
ILO
ICC
Input Leakage
Current
Output Leakage
Current
Active Power
Supply Current
LP62S2048-70LI/10LI LP62S2048-70LLI/10LLI
- 1 - 1
- 1 - 1
- 3 - 3 mA
Unit Conditions
VIN = GND to VCC
µA
µA
or OE = VIH or WE = VIL
VI/O = GND to VCC
II/O = 0mA
CE1 = VIH or CE2 = VIL
CE1 = VIL, CE2 = VIH
ICC1
ICC2
Dynamic
Operating
Current
- 30 - 30 mA
- 5 - 5 mA
Min. Cycle, Duty = 100%
CE1 = VIL, CE2 = VIH
II/O = 0mA
CE1 = VIL, CE2 = VIH
VIH = VCC, VIL = 0V
f = 1 MHZ, II/O = 0mA
(August, 2001, Version 1.0) 4 AMIC Technology, Inc.
Page 5
LP62S2048-I Series
CE1
OE WE
DC Electrical Characteristics (continued)
Symbol Parameter
Min. Max. Min. Max.
ISB- 0.5 - 0.5 mA
ISB1
ISB2- 50 - 10
VOL
VOH
Standby Power
Supply Current
Output Low
Voltage
Output High
Voltage
LP62S2048-70LI/10LI LP62S2048-70LLI/10LLI
- 50 - 10
- 0.4 - 0.4 V IOL = 2.1mA
2.2 - 2.2 - V IOH = -1.0mA
Unit Conditions
µA
µA
Truth Table
Mode
Standby
H X X X High Z ISB, ISB1
CE2
I/O Operation Supply Current
CE1 = VIH or CE2 =VIL
CE1 ≥ VCC - 0.2V
VIN≥ 0V
CE2 ≤ 0.2V
VIN≥ 0V
X L X X High Z ISB, ISB2
Output Disable L H H H High Z ICC, ICC1, ICC2
Read L H L H DOUTICC, ICC1, ICC2
Write L H X L DINICC, ICC1, ICC2
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance 6 pF VIN = 0V
CI/O* Input/Output Capacitance 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
(August, 2001, Version 1.0) 5 AMIC Technology, Inc.
Page 6
LP62S2048-I Series
AC Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.3V)
Symbol Parameter
Min. Max. Min. Max.
Read Cycle
tRCRead Cycle Time 70 - 100 - ns
tAAAddress Access Time - 70 - 100 ns
tACE1
tACE2CE2 - 70 - 100 ns
tOEOutput Enable to Output Valid - 35 - 50 ns
tCLZ1
tCLZ2CE2 10 - 10 - ns
tOLZOutput Enable to Output in Low Z 5 - 5 - ns
tCHZ1
tCHZ2CE2 0 25 0 35 ns
tOHZOutput Disable to Output in High Z 0 25 0 35 ns
Chip Enable Access Time
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
CE1
CE1
CE1
LP62S2048-70LI/LLI LP62S2048-10LI/LLI
- 70 - 100 ns
10 - 10 - ns
0 25 0 35 ns
Unit
tOHOutput Hold from Address Change 10 - 10 - ns
Write Cycle
tWCWrite Cycle Time 70 - 100 - ns
tCWChip Enable to End of Write 60 - 80 - ns
tASAddress Setup Time 0 - 0 - ns
tAWAddress Valid to End of Write 60 - 80 - ns
tWPWrite Pulse Width 50 - 60 - ns
tWRWrite Recovery Time 0 - 0 - ns
tWHZWrite to Output in High Z 0 25 0 35 ns
tDWData to Write Time Overlap 30 - 40 - ns
tDHData Hold from Write Time 0 - 0 - ns
tOWOutput Active from End of Write 5 - 5 - ns
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
(August, 2001, Version 1.0) 6 AMIC Technology, Inc.
Page 7
LP62S2048-I Series
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
Read Cycle 2
CE1
DOUT
Read Cycle 3
CE2
(1, 3, 4, 6)
(1, 4, 7, 8)
tACE1
5
tCLZ1
tCHZ1
5
tACE2
5
tCLZ2
5
tCHZ2
DOUT
(August, 2001, Version 1.0) 7 AMIC Technology, Inc.
Page 8
LP62S2048-I Series
Timing Waveforms (continued)
Read Cycle 4
Address
(1)
tRC
tAA
OE
CE2
DOUT
CE1
tCLZ1
tCLZ2
tOE
5
tOLZ
tACE1
5
tACE2
5
tCHZ2
tOH
tCHZ1
5
5
tOHZ
5
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
(August, 2001, Version 1.0) 8 AMIC Technology, Inc.
Page 9
LP62S2048-I Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
Address
(6)
tWC
CE1
CE2
WE
DOUT
DIN
tAW
5
tCW
(4)
(4)
1
tAS
tWHZ
tWP
2
tDW
tWR
tDH
3
tOW
(August, 2001, Version 1.0) 9 AMIC Technology, Inc.
Page 10
LP62S2048-I Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
3
CE1
tAWtWR
5
tCW
(4)
1
tAS
CE2
WE
DIN
DOUT
(4)
5
tCW
2
tWP
tWHZ
tDW
7
tDH
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE.
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(August, 2001, Version 1.0) 10 AMIC Technology, Inc.
Page 11
LP62S2048-I Series
AC Test Conditions
Input Pulse Levels 0.4V to 2.4V
Input Rise and Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
TTL
CL
30pF
* Including scope and jig.* Including scope and jig.
CL
TTL
5pF
Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = -40°C to 85°C)
Symbol Parameter Min. Max. Unit Conditions
VDR12.0 3.3 V
VDR2VCC for Data Retention 2.0 3.3 V
ICCDR1
Data Retention Current
L-Version - 20*
LL-Version - 5**
µA
CE1 ≥ VCC - 0.2V
CE2 ≤ 0.2V,
VCC = 2.0V,
CE1 ≥ VCC - 0.2V,
VIN ≥ 0V
ICCDR2
LL-Version - 5**
L-Version - 20*
µA
VCC = 2.0V,
CE2≤ 0.2V,
VIN ≥ 0V
tCDRChip Disable to Data Retention Time 0 - ns
tROperation Recovery Time tRC- ns
tVRVCC Rising Time from Data Retention Voltage
5 - ms
See Retention Waveform
to Operating Voltage
** LP62S2048-70LLI/10LLI ICCDR: max. 1µA at TA = 0°C to + 40°C
* LP62S2048-70LI/10LI ICCDR: max. 5µA at TA = 0°C to + 40°C
(August, 2001, Version 1.0) 11 AMIC Technology, Inc.
Page 12
LP62S2048-I Series
CE1
Low VCC Data Retention Waveform (1) (
Controlled)
DATA RETENTION MODE
VCC
CE1
2.7V
tCDR
VIH
VDR ≥ 2V
CE1 ≥ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
2.7V
tCDR
VIL
VDR ≥ 2V
0.2VCE2 ≤
2.7V
tR
tVR
VIH
2.7V
tR
tVR
VIL
(August, 2001, Version 1.0) 12 AMIC Technology, Inc.