Datasheet LP62S2048AX-70LLT, LP62S2048AX-55LLT, LP62S2048AV-70LLT, LP62S2048AM-55LLT, LP62S2048AU-55LLT Datasheet (AMIC)

LP62S2048A-T Series

Preliminary 256K X 8 BIT LOW VOLTAGE CMOS SRAM

Document Title
256K X 8 BIT LOW VOLTAGE CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue June 24, 2002 Preliminary

PRELIMINARY (June, 2002, Version 0.0) 1 AMIC Technology, Inc.

LP62S2048A-T Series

Preliminary 256K X 8 BIT LOW VOLTAGE CMOS SRAM

Features

n Power supply range: 2.7V to 3.3V
n Access times: 55/70 ns (max.)
n Current:

Very low power version: Operating: 55ns: 25mA (max.)
70ns: 20mA (max.)
Standby: 10µA (max.)

n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy

application

n Data retention voltage: 2V (min.)
n Available in 32-pin SOP, TSOP, TSSOP (8X13.4mm)

and 36-pin CSP packages

Product Family

Product Family

LP62S2048A

Operating

Temperature

-25°C ~ +85°C

VCC

Range

2.7V~3.3V 55ns / 70ns

Speed

General Description

The LP62S2048A-T is a low operating current 2,097,152-bit
static random access memory organized as 262,144 words
by 8 bits and operates on a low power supply range: 2.7V to

3.3V. It is built using AMIC's high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included for
easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2V.

Power Dissipation

Data Retention

(ICCDR, Typ.)

0.5µA 0.5µA

Standby

(ISB1, Typ.)

Operating
(ICC2, Typ.)

3mA

Package

Type

32L SOP

32L TSOP

32L TSSOP

36L CSP

1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.

2. Data retention current VCC = 2.0V.

PRELIMINARY (June, 2002, Version 0.0) 2 AMIC Technology, Inc.

LP62S2048A-T Series

Pin Configurations

nn SOP nn TSOP/(TSSOP) nn CSP (Chip Size Package)
36-pin Top View

1

A17
A16

2

A14

3

A12

4

A7

5

A6
A5
A4
A3
A2
A1

A0
I/O1
I/O2
I/O3

LP62S2048AM-T

6
7
8
9

10
11
12
13
14
15
16 17

Block Diagram

VCC

32

A15

31

CE2

30

WE

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23
22

CE1
I/O8

21

I/O7

20

I/O6

19

I/O5

18

I/O4GND

Pin No.

1 2A93 4 5 6 7 8 9 10 11 12 13 14

Pin

A11 WE

Name

Pin No.

Pin

A3 A2 A1 A0 I/O1 I/O2 GND I/O4 I/O5 I/O6 I/O7

Name

16

(LP62S2048AX-T)

LP62S2048AV-T

17

A8 A13 CE2 A15 VCC A17

I/O3

1

32

A16 A14 A12 A7 A6

654321

A7

A15

A8
I/O1
I/O2

VCC
GND

I/O3
I/O4

A0

A
B

C
D
E
F
G
H

15 16

A5 A4

302928272625242219 2120 231817

31 32

I/O8

CE1

A10 OE

A1A2CE2
I/O5
I/O6

GND
VCC

I/O7
I/O8

A9 A10OEA11

A3 A6

WE

A4

NC A5

NC A17

CE1

A16
A12 A13 A14

A15

A16

A17

I/O1

I/O8

CE2
CE1

WE

OE

A0

CONTROL

CIRCUIT

ROW

DECODER

INPUT DATA

CIRCUIT

1024 X 2048

MEMORY ARRAY

COLUMN I/O

VCC
GND

PRELIMINARY (June, 2002, Version 0.0) 3 AMIC Technology, Inc.

LP62S2048A-T Series

Pin Description - SOP

Pin No. Symbol Description

1 - 12, 23,

25 - 28, 31

13 - 15,

17 - 21

16 GND Ground

22

24

29

30 CE2 Chip Enable

32 VCC Power Supply

A0 - A17 Address Inputs

I/O1 - I/O8 Data Input/Outputs

CE1

OE

WE

Chip Enable

Output Enable

Write Enable

Pin Description - CSP

Pin Descriptions - TSOP/TSSOP

Pin No. Symbol Description

1 - 4, 7,

9 - 20, 31

5

6 CE2 Chip Enable
8 VCC Power Supply
9 NC No Connection

21 - 23,

25 - 29

24 GND Ground
30

32

A0 - A17 Address Inputs

WE

I/O1 - I/O8 Data Input/Outputs

CE1

OE

Write Enable

Chip Enable

Output Enable

Symbol Description Symbol Description

A0 - A17 Address Inputs NC No Connection

WE

OE

CE1
CE2 Chip Enable -- --

Write Enable I/O1 - I/O8 Data Input/Output

Output Enable VCC Power Supply

Chip Enable GND Ground

Recommended DC Operating Conditions

(TA = -25°C to + 85°C)

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 2.7 3.0 3.3 V
GND Ground 0 0 0 V

VIH Input High Voltage 2.0 - VCC + 0.3 V
VIL Input Low Voltage -0.3 - +0.6 V

CL Output Load - - 30 pF

TTL Output Load - - 1 -

PRELIMINARY (June, 2002, Version 0.0) 4 AMIC Technology, Inc.

LP62S2048A-T Series

Absolute Maximum Ratings*

VCC to GND . . . . . . . .. . . . . . . . . . . . . -0.5V to + 4.6V

IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V

Operating Temperature, Topr . . . . . . . . -25°C to + 85°C

Storage Temperature, Tstg . . .. . . . . . . -55°C to + 125°C

Temperature Under Bias, Tbias .. . . . . . -10°C to + 85°C

Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . 0.7W

Soldering Temp. & Time . . . . . . . . . . . . . 260°C, 10 sec

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.3V, GND = 0V)

Symbol Parameter

Min. Max. Min. Max.

ILI

ILO

ICC

Input Leakage Current - 1 - 1

Output Leakage Current - 1 - 1

Active Power Supply
Current

LP62S2048A-55LLT LP62S2048A-70LLT

- 3 - 3 mA

Unit Conditions

VIN = GND to VCC

µA

µA

or OE = VIH or WE = VIL

VI/O = GND to VCC

II/O = 0mA

CE1 = VIH or CE2 = VIL

CE1 = VIL, CE2 = VIH

Min. Cycle, Duty = 100%

ICC1

Dynamic Operating
Current

ICC2

ISB - 0.5 - 0.5 mA

ISB1

ISB2 - 10 - 10

VOL Output Low Voltage - 0.4 - 0.4 V IOL = 2.1mA

VOH Output High Voltage 2.2 - 2.2 - V IOH = -1.0mA

Standby Power Supply
Current

- 25 - 20 mA

- 5 - 5 mA

- 10 - 10

µA

µA

CE1 = VIL, CE2 = VIH

II/O = 0mA

CE1 = VIL, CE2 = VIH
VIH = VCC, VIL = 0V
f = 1 MHZ, II/O = 0mA

CE1 = VIH or CE2 =VIL

CE1 ≥ VCC - 0.2V

VIN ≥ 0V

CE2 ≤ 0.2V
VIN ≥ 0V

PRELIMINARY (June, 2002, Version 0.0) 5 AMIC Technology, Inc.

LP62S2048A-T Series

CE1

OE WE

Truth Table

Mode

Standby
X L X X High Z ISB, ISB2

Output Disable L H H H High Z ICC, ICC1, ICC2

Read L H L H DOUT ICC, ICC1, ICC2

Write L H X L DIN ICC, ICC1, ICC2

Note: X = H or L

H X X X High Z ISB, ISB1

CE2

I/O Operation Supply Current

Capacitance (TA = 25°C, f = 1.0MHz)

Symbol Parameter Min. Max. Unit Conditions

CIN* Input Capacitance 6 pF VIN = 0V

CI/O* Input/Output Capacitance 8 pF VI/O = 0V

* These parameters are sampled and not 100% tested.

PRELIMINARY (June, 2002, Version 0.0) 6 AMIC Technology, Inc.

LP62S2048A-T Series

AC Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.3V)

Symbol Parameter

Min. Max. Min. Max.

Read Cycle

tRC Read Cycle Time 55 - 70 - ns
tAA Address Access Time - 55 - 70 ns

tACE1

tACE2 CE2 - 55 - 70 ns

tOE Output Enable to Output Valid - 25 - 35 ns

tCLZ1

tCLZ2 CE2 10 - 10 - ns

tOLZ Output Enable to Output in Low Z 5 - 5 - ns

tCHZ1

tCHZ2 CE2 0 20 0 25 ns

tOHZ Output Disable to Output in High Z 0 20 0 25 ns

Chip Enable Access Time

Chip Enable to Output in Low Z

Chip Disable to Output in High Z

CE1

CE1

CE1

LP62S2048A-55LLT LP62S2048A-70LLT

- 55 - 70 ns

10 - 10 - ns

0 20 0 25 ns

Unit

tOH Output Hold from Address Change 5 - 10 - ns

Write Cycle

tWC Write Cycle Time 55 - 70 - ns
tCW Chip Enable to End of Write 50 - 60 - ns
tAS Address Setup Time 0 - 0 - ns
tAW Address Valid to End of Write 50 - 60 - ns
tWP Write Pulse Width 40 - 50 - ns
tWR Write Recovery Time 0 - 0 - ns

tWHZ Write to Output in High Z 0 25 0 25 ns

tDW Data to Write Time Overlap 25 - 30 - ns
tDH Data Hold from Write Time 0 - 0 - ns

tOW Output Active from End of Write 5 - 5 - ns

Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.

PRELIMINARY (June, 2002, Version 0.0) 7 AMIC Technology, Inc.

LP62S2048A-T Series

Timing Waveforms

Read Cycle 1

Address

DOUT

(1, 2, 4)

tRC

tAA

tOH

tOH

Read Cycle 2

CE1

DOUT

Read Cycle 3

CE2

(1, 3, 4, 6)

(1, 4, 7, 8)

tACE1

5

tCLZ1

tCHZ1

5

tACE2

5

tCLZ2

5

tCHZ2

DOUT

PRELIMINARY (June, 2002, Version 0.0) 8 AMIC Technology, Inc.

LP62S2048A-T Series

Timing Waveforms (continued)

Read Cycle 4

Address

(1)

tRC

tAA

OE

CE2

DOUT

CE1

tCLZ1

tCLZ2

tOE

5

tOLZ

tACE1

5

tACE2

5

tCHZ2

tOH

tCHZ1

5

5

tOHZ

5

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled CE1 = VIL and CE2 = VIH.

3. Address valid prior to or coincident with CE1 transition low.

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

6. CE2 is high.

7. CE1 is low.

8. Address valid prior to or coincident with CE2 transition high.

PRELIMINARY (June, 2002, Version 0.0) 9 AMIC Technology, Inc.

LP62S2048A-T Series

Timing Waveforms (continued)

Write Cycle 1
(Write Enable Controlled)

Address

(6)

tWC

CE1

CE2

WE

DOUT

DIN

tAW

5

tCW

(4)

(4)

1

tAS

tWHZ

tWP

2

tDW

tWR

tDH

3

tOW

PRELIMINARY (June, 2002, Version 0.0) 10 AMIC Technology, Inc.

LP62S2048A-T Series

Timing Waveforms (continued)

Write Cycle 2
(Chip Enable Controlled)

tWC

Address

3

CE1

tAW tWR

5

tCW

(4)

1

tAS

CE2

WE

DIN

DOUT

(4)

5

tCW

2

tWP

tWHZ

tDW

7

tDH

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE.

3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.

4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.

5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.

6. OE is continuously low. ( OE = VIL)

7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (June, 2002, Version 0.0) 11 AMIC Technology, Inc.

LP62S2048A-T Series

AC Test Conditions

Input Pulse Levels 0.4V to 2.4V

Input Rise and Fall Time 5 ns

Input and Output Timing Reference Levels 1.5V

Output Load See Figures 1 and 2

TTL

CL

30pF

* Including scope and jig. * Including scope and jig.

CL

TTL

5pF

Figure 1. Output Load Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW

Data Retention Characteristics (TA = -25°C to 85°C)

Symbol Parameter Min. Max. Unit Conditions

VDR1 2.0 3.3 V

VDR2 VCC for Data Retention 2.0 3.3 V

ICCDR1 - 5**

Data Retention Current

ICCDR2

- 5**

µA

µA

CE1 ≥ VCC - 0.2V

CE2 ≤ 0.2V,

VCC = 2.0V,
CE1 ≥ VCC - 0.2V,

VIN ≥ 0V

VCC = 2.0V,
CE2 ≤ 0.2V,
VIN ≥ 0V

tCDR Chip Disable to Data Retention Time 0 - ns

tR Operation Recovery Time tRC - ns

tVR VCC Rising Time from Data Retention Voltage

5 - ms

See Retention Waveform

to Operating Voltage

** LP62S2048A-55LLT/70LLT ICCDR: max. 1µA at TA = 0°C to + 40°C

PRELIMINARY (June, 2002, Version 0.0) 12 AMIC Technology, Inc.

LP62S2048A-T Series

CE1

Low VCC Data Retention Waveform (1) (

Controlled)

DATA RETENTION MODE

VCC

CE1

2.7V

tCDR

VIH

VDR ≥ 2V

CE1 ≥ VDR - 0.2V

Low VCC Data Retention Waveform (2) (CE2 Controlled)

DATA RETENTION MODE

VCC

CE2

2.7V

tCDR

VIL

VDR ≥ 2V

0.2VCE2 ≤

2.7V
tR

tVR

VIH

2.7V
tR

tVR

VIL

Ordering Information

Part No. Access Time (ns) Operating Current

Max. (mA)

LP62S2048AM-55LLT 25 10 32L SOP
LP62S2048AV-55LLT

55

25 10 32L TSOP
LP62S2048AX-55LLT 25 10 32L TSSOP
LP62S2048AU-55LLT 25 10 36L CSP
LP62S2048AM-70LLT 20 10 32L SOP
LP62S2048AV-70LLT

70

20 10 32L TSOP
LP62S2048AX-70LLT 20 10 32L TSSOP
LP62S2048AU-70LLT 20 10 36L CSP

Standby Current

Max. (µµA)

Package

PRELIMINARY (June, 2002, Version 0.0) 13 AMIC Technology, Inc.

LP62S2048A-T Series

Package Information

SOP (W.B.) 32L Outline Dimensions unit: inches/mm

1

s

Seating Plane

1732

E

HE

16

b

D

A

y

e

D

A1 A2

See Detail F

Detail F

e1

L

e1

~

~

c

LE

Symbol Dimensions in inches Dimensions in mm

A 0.118 Max. 3.00 Max.
A1 0.004 Min. 0.10 Min.
A2 0.106±0.005 2.69±0.13

b 0.016 +0.004 0.41 +0.10

-0.002

-0.05

c 0.008 +0.004 0.20 +0.10

-0.002 -0.05
D 0.805 Typ. (0.820 Max.) 20.45 Typ. (20.83 Max.)
E 0.445±0.010 11.30±0.25
e 0.050 ±0.006 1.27±0.15
e1 0.525 NOM. 13.34 NOM.

HE 0.556±0.010 14.12±0.25

L 0.031±0.008 0.79±0.20

LE 0.055±0.008 1.40±0.20

S 0.044 Max. 1.12 Max.

y 0.004 Max. 0.10 Max.

θ 0° ~ 10° 0° ~ 10°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.

4. Dimension S includes end flash.

PRELIMINARY (June, 2002, Version 0.0) 14 AMIC Technology, Inc.

LP62S2048A-T Series

Package Information

TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm

D

e

0.25

BSC

Detail "A"

°12.0

LE

b

A

θ

L

0.10(0.004) M

A2

E

HD

Detail "A"

y

D

c

GAUGE PLANE

A1

S

Symbol Dimensions in inches Dimensions in mm

A 0.047 Max. 1.20 Max.

A1 0.004±0.002 0.10±0.05
A2 0.039±0.002 1.00±0.05

b 0.008±0.001 0.20±0.03
c 0.006±0.001 0.15±0.02
D 0.724±0.004 18.40±0.10
E 0.315±0.004 8.00±0.10
e 0.020 TYP. 0.50 TYP.

HD 0.787±0.007 20.00±0.20

L 0.020±0.004 0.50±0.10

LE 0.031 TYP. 0.80 TYP.

S 0.0167 TYP. 0.425 TYP.
Y 0.004 Max. 0.10 Max.
θ 0° ~ 6° 0° ~ 6°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.

4. Dimension S includes end flash.

PRELIMINARY (June, 2002, Version 0.0) 15 AMIC Technology, Inc.

LP62S2048A-T Series

Package Information

TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm

E

0.10MM

D

SEATING PLANE

e

A2

c

GAUGE PLANE

A1

D1

D

Detail "A"

S

0.25

BSC

Detail "A"

Detail "A"

°12.0

A

θ

L

LE

b

Symbol Dimensions in inches Dimensions in mm

A 0.049 Max. 1.25 Max.

A1 0.002 Min. 0.05 Min.
A2 0.039±0.002 1.00±0.05

b 0.008±0.001 0.20±0.03
c 0.006±0.0003 0.15±0.008
E 0.315±0.004 8.00±0.10
e 0.020 TYP. 0.50 TYP.
D 0.528±0.008 13.40±0.20

D1 0.465±0.004 11.80±0.10

L 0.02±0.008 0.50±0.20

LE 0.0266 Min. 0.675 Min.

S 0.0109 TYP. 0.278 TYP.

y 0.004 Max. 0.10 Max.

θ 0° ~ 6° 0° ~ 6°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.

4. Dimension S includes end flash.

PRELIMINARY (June, 2002, Version 0.0) 16 AMIC Technology, Inc.

LP62S2048A-T Series

Package Information
36LD CSP (6 x 8 mm) Outline Dimensions unit: mm

TOP VIEW

Ball*A1 CORNER

1 2 3 4 5 6

A
B
C
D
E
F
G
H

SIDE VIEW

A2

// 0.25 C

C

SEATING PLANE

(0.36)

0.10 C

A

A1

e

E

E1

B e

A

0.20(4X)

BOTTOM VIEW

Ball#A1 CORNER

S

0.10 C
C

0.25SA B

b (36X)

D1

D

123456

A

B
C
D

E

F
G
H

Symbol

Dimensions in mm

MIN.

NOM. MAX.

A 1.00 1.10 1.20
A1 0.16 0.21 0.26
A2 0.48 0.53 0.58

D 5.80 6.00 6.20

E 7.80 8.00 8.20

D1 --- 3.75 ---

E1 --- 5.25 ---

e --- 0.75 ---

b 0.25 0.30 0.35

Note:

1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).

2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.

3. DIMENSION b IS MEASURED AT THE MAXIMUM.

4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.

PRELIMINARY (June, 2002, Version 0.0) 17 AMIC Technology, Inc.