Datasheet LP62S1664CV-70LLT, LP62S1664CV-70LLI, LP62S1664CV-55LLT, LP62S1664CV-55LLI, LP62S1664CU-70LLI Datasheet (AMIC)
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LP62S1664C Series
Preliminary 64K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
64K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue February 19, 2002 Preliminary
PRELIMINARY (February, 2002, Version 0.0) AMIC Technology, Inc.
Page 2
LP62S1664C Series
HB
LP62S1664CU
Preliminary 64K X 16 BIT LOW VOLTAGE CMOS SRAM
Features General Description
n Operating voltage: 2.7V to 3.6V
n Access times: 55/70 ns (max.)
n Current:
LP62S1664C-55 series: Operating: 50mA (max.)
Standby: 5µA (max.)
LP62S1664C-70 series: Operating: 40mA (max.)
Standby: 5µA (max.)
n Extended operating temperature range : -40°C to 85°C
for -LLI series
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 44-pin TSOP and 48-ball Mini BGA (6X8)
packages.
Product Family
The LP62S1664C is a low operating current 1,048,576bit static random access memory organized as 65,536
words by 16 bits and operates on low power supply
voltage from 2.7V to 3.6V. It is built using AMIC’s high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Product
Family
LP62S1664C
Operating
Temperature
-40°C ~ +85°C
VCC
Range
Speed
2.7V~3.6V 55ns / 70ns
Data Retention
(ICCDR, Typ.)
Power Dissipation
Standby
(ISB1, Typ.)
0.2µA 0.3µA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configuration
n TSOP (Type II) n Mini BGA (6X8) Top View
1 2 3 4 5 6
A
B I/O8
LB OE
C I/O9 I/O10 A5 A6 I/O1 I/O2
D VSS I/O11 NC A7 I/O3 VCC
E VCC I/O12 NC NC I/O4 VSS
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 NC A12 A13
H NC A8 A9 A10 A11 NC
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1A4
A3
2
A2
3
4
A1
A0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
A5
43
A6
42
A7
41
OE
40
HB
39
LB
38
I/O15
37
LP62S1664CV
I/O14
36
I/O13
35
I/O12
34
GND
33
VCC
32
I/O11
31
I/O10
30
I/O9
I/O8
29
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
Operating
Package
(ICC2, Typ.)
3mA
44L TSOP
48B MBGA
A0 A1 A2 NC
A3 A4
CS
WE
I/O0
I/O7
Type
PRELIMINARY (February, 2002, Version 0.0) 1 AMIC Technology, Inc.
Page 3
LP62S1664C Series
Block Diagram
A0
A14
A15
I/O
I/O
VCC
GND
DECODER
0
INPUT
DATA
CIRCUIT
7
512 X 2048
MEMORY ARRAY
COLUMN I/O
INPUT
DATA
CIRCUIT
I/O
I/O
8
15
CE
LB
HB
OE
WE
CONTROL
CIRCUIT
PRELIMINARY (February, 2002, Version 0.0) 2 AMIC Technology, Inc.
Page 4
LP62S1664C Series
Pin Description - TSOP
Pin No. Symbol Description
1 - 5, 18 - 21,
24 - 27,42 - 44
6
7 - 10, 13 - 16,
29 - 32, 35 - 38
17
39
40
41
11, 33 VCC Power
12, 34 GND Ground
22 , 23, 28 NC No Connection
A0 - A15 Address Inputs
CE
I/O0 - I/O15 Data Input/Outputs
WE
LB
HB
OE
Chip Enable Input
Write Enable Input
Byte Enable Input (I/O0 to I/O7)
Byte Enable Input (I/O8 to I/O15)
Output Enable Input
Recommended DC Operating Conditions
(TA = -25°C to + 85°C for –LLT or -40°C to 85°C for -LLI)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 2.7 3.0 3.6 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.2 - VCC + 0.3 V
VIL Input Low Voltage -0.3 - +0.6 V
CL Output Load - - 30 pF
TTL Output Load - - 1 -
PRELIMINARY (February, 2002, Version 0.0) 3 AMIC Technology, Inc.
Page 5
LP62S1664C Series
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . -40°C to +85°C
Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics
(TA = -25°C to + 85°C for -LLT or -40°C to + 85°C for -LLI, VCC = 2.7V to 3.6V, GND = 0V)
Symbol Parameter
ILI
ILO
ICC
Input Leakage
Current
Output Leakage
Current
Active Power
Supply Current
LP62S1664C-55LLT/LLI LP62S1664C-70LLT/LLI
Min. Max. Min. Max.
- 1 - 1
- 1 - 1
- 5 - 5 mA
Unit Conditions
VIN = GND to VCC
µA
CE = VIH or OE = VIH or
µA
LB = HB = VIH or
WE = VIL
VI/O = GND to VCC
CE = VIL, II/O = 0mA
ICC1
Dynamic
Operating
ICC2
ISB
ISB1
VOL
VOH
Current
Standby Power
Supply Current
Output Low
Voltage
Output High
Voltage
- 50 - 40
- 5 - 5 mA
- 0.3 - 0.3 mA
- 5 - 5
- 0.4 - 0.4 V IOL = 2.1mA
2.2 - 2.2 - V IOH = -1.0mA
mA
Min. Cycle, Duty = 100%
CE = VIL, II/O = 0mA
CE = VIL, VIH = VCC,
VIL = 0V, f = 1MHz,
II/O = 0 mA
CE = VIH
µA
CE ≥ VCC - 0.2V
VIN ≥ 0V
PRELIMINARY (February, 2002, Version 0.0) 4 AMIC Technology, Inc.
Page 6
LP62S1664C Series
CE OE WE LB HB
Truth Table
I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current
H X X X X Not selected Not selected ISB1, ISB
L L Read Read ICC1, ICC2, ICC
L L H L H Read High - Z ICC1, ICC2, ICC
H L High - Z Read ICC1, ICC2, ICC
L L Write Write ICC1, ICC2, ICC
L X L L H Write Not Write/Hi - Z ICC1, ICC2, ICC
H L Not Write/Hi - Z Write ICC1, ICC2, ICC
L X High - Z High - Z ICC1, ICC2, ICC
L H H
X L High - Z High - Z ICC1, ICC2, ICC
X X X H H Not selected Not selected ISB1, ISB
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance - 6 pF VIN = 0V
CI/O* Input/Output Capacitance - 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY (February, 2002, Version 0.0) 5 AMIC Technology, Inc.
Page 7
LP62S1664C Series
AC Characteristics (TA = -25°C to +85°C for -LLT or -40°C to +85°C for -LLI, VCC = 2.7V to 3.6V)
Symbol Parameter
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 - 70 - ns
tAA Address Access Time - 55 - 70 ns
tACE Chip Enable Access Time - 55 - 70 ns
tBE Byte Enable Access Time - 55 - 70 ns
tOE Output Enable to Output Valid - 30 - 35 ns
tCLZ Chip Enable to Output in Low Z 10 - 10 - ns
tBLZ Byte Enable to Output in Low Z 5 - 5 - ns
tOLZ Output Enable to Output in Low Z 5 - 5 - ns
tCHZ Chip Disable to Output in High Z - 20 - 25 ns
tBHZ Byte Disable to Output in High Z - 20 - 25 ns
tOHZ Output Disable to Output in High Z - 20 - 25 ns
tOH Output Hold from Address Change 5 - 10 - ns
Write Cycle
LP62S1664C-55LLT/LLI LP62S1664C-70LLT/LLI
Unit
tWC Write Cycle Time 55 - 70 - ns
tCW Chip Enable to End of Write 50 - 60 - ns
tBW Byte Enable to End of Write 50 - 60 - ns
tAS Address Setup Time 0 - 0 - ns
tAW Address Valid to End of Write 50 - 60 - ns
tWP Write Pulse Width 40 - 50 - ns
tWR Write Recovery Time 0 - 0 - ns
tWHZ Write to Output in High Z - 25 - 30 ns
tDW Data to Write Time Overlap 25 - 30 - ns
tDH Data Hold from Write Time 0 - 0 - ns
tOW Output Active from End of Write 5 - 5 - ns
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY (February, 2002, Version 0.0) 6 AMIC Technology, Inc.
Page 8
LP62S1664C Series
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
Read Cycle 2
Address
CE
HB, LB
OE
DOUT
(1, 2, 3)
tRC
tAA
tCLZ
tACE
5
tBE
5
tBLZ
tOE
5
tOLZ
tOHZ
tBHZ
5
tCHZ
5
5
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and (HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (February, 2002, Version 0.0) 7 AMIC Technology, Inc.
Page 9
LP62S1664C Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
tWC
Address
3
tAW
tCW
CE
tBW
HB, LB
tWR
WE
DATA IN
DATA OUT
1
tAS
4
tWHZ
tWP
2
tDW
tDH
tOW
PRELIMINARY (February, 2002, Version 0.0) 8 AMIC Technology, Inc.
Page 10
LP62S1664C Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
CE
HB, LB
WE
DATA IN
DATA OUT
tAW
tWP
tCW
2
tBW
tDW
1
tAS
4
tWHZ
tWR
3
tDH
tOW
PRELIMINARY (February, 2002, Version 0.0) 9 AMIC Technology, Inc.
Page 11
LP62S1664C Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
tWC
Address
tAW
tCW
CE
3
tWR
HB, LB
WE
tWP
tBW
2
1
tAS
tDH
tOW
DATA IN
DATA OUT
tWHZ
tDW
4
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and, or LB ).
3. tWR is measured from the earliest of CE or WE or (HB and, or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (February, 2002, Version 0.0) 10 AMIC Technology, Inc.
Page 12
LP62S1664C Series
AC Test Conditions
Input Pulse Levels 0V to 2.4V
Input Rise And Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
TTL
CL
30pF
* Including scope and jig. * Including scope and jig.
CL
TTL
5pF
Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -25°C to 85°C for –LLT or -40°C to 85°C for -LLI)
Symbol Parameter Min. Max. Unit Conditions
VDR VCC for Data Retention 2.0 3.6 V
ICCDR Data Retention Current - 3*
tCDR Chip Disable to Data Retention Time 0 - ns
CE ≥ VCC - 0.2V
VCC = 2.0V,
µA
CE ≥ VCC - 0.2V
VIN ≥ 0V
tR Operation Recovery Time tRC - ns
tVR VCC Rise Time from Data Retention
5 - ms
See Retention Waveform
Voltage to Operating Voltage
* LP62S1664C-55/70(LLT/LLI) ICCDR: max. 1µA at TA = 0°C to + 40°C
PRELIMINARY (February, 2002, Version 0.0) 11 AMIC Technology, Inc.
Page 13
LP62S1664C Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
CE
2.7V
tCDR
VIH
VDR ≥ 2V
CE ≥ VDR - 0.2V
2.7V
tR
tVR
VIH
Ordering Information
Part No. Access Time (ns)
Operating Current
Max. (mA)
LP62S1664CV-55LLT 44L TSOP
LP62S1664CV-55LLI 44L TSOP
55 50 5
LP62S1664CU-55LLT 48B Mini BGA
LP62S1664CU-55LLI
LP62S1664CV-70LLT 44L TSOP
LP62S1664CV-70LLI 44L TSOP
70 40 5
LP62S1664CU-70LLT 48B Mini BGA
Standby Current
Max. (µµA)
Package
48B Mini BGA
LP62S1664CU-70LLI
48B Mini BGA
LLT : for -25°C ~ 85°C
LLI : for -40°C ~ 85°C
PRELIMINARY (February, 2002, Version 0.0) 12 AMIC Technology, Inc.
Page 14
LP62S1664C Series
Package Information
TSOP 44L (Type II) Outline Dimensions unit: inches/mm
44
E
E1
θ
L
1
D
A
L1
c
L1
ZD
b
e
y
D
A1 A2
L
Symbol
A - - 0.047 - - 1.20
A1 0.002 - 0.006 0.05 - 0.15
A2 0.037 0.039 0.041 0.95 1.00 1.05
b 0.012 - 0.018 0.30 - 0.45
c 0.005 - 0.008 0.12 - 0.21
D 0.720 0.725 0.730 18.28 18.41 18.54
ZD 0.032 REF 0.805 REF
E 0.455 0.463 0.471 11.56 11.76 11.96
E1 0.395 0.400 0.405 10.03 10.16 10.29
L 0.019 0.023 0.027 0.49 0.59 0.69
L1 0.031 REF 0.80 REF
e 0.031 BSC 0.80 BSC
y - - 0.004 - - 0.10
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension ZD includes end flash.
Dimensions in inches Dimensions in mm
Min Nom Max Min Nom Max
0° - 5° 0° - 5°
PRELIMINARY (February, 2002, Version 0.0) 13 AMIC Technology, Inc.
Page 15
LP62S1664C Series
Symbol
Min
Typ
Max
Package Information
Mini BGA 6X8 (48 BALLS) Outline Dimensions unit : millimeter(mm)
C1
Bottom View
Pin A1 Index
123456
A
B
C
D
E
A
A
B1
D
0.10
E1
F
G
H
Diameter D
Solder Ball
Pin A1 Index
Top View
C
B
E2
E
A - 0.75 B 5.90 6.00 6.10
B1 - 3.75 -
C 7.90 8.00 8.10
C1 - 5.25 -
D 0.30 0.35 0.40
E 1.00 1.10 1.20
E1 - 0.36 E2 - 0.25 -
PRELIMINARY (February, 2002, Version 0.0) 14 AMIC Technology, Inc.
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