Page 1
LP62S16256F-T Series
Preliminary 256K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
n Operating voltage: 2.7V to 3.3V
n Access times: 70 ns (max.)
n Current:
Very low power version: Operating: 40mA (max.)
Standby: 10µA (max.)
n Full static operation, no clock or refreshing required
General Description
The LP62S16256F-T is a low operating current
4,194,304-bit static random access memory organized as
262,144 words by 16 bits and operates on low power
voltage from 2.7V to 3.3V. It is built using AMIC's high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
nn TSOP nn CSP (Chip Size Package)
48-pin Top View
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2.0V (min.)
n Available in 44-pin TSOP and 48-ball CSP (6×8mm)
packages
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
1
VCC
GND
A4
2
A3
3
A2
4
A1
5
A0
6
CE
7
I/O1
8
I/O2
9
I/O3
10
I/O4
11
12
13
I/O5
14
I/O6
15
I/O7
16
I/O8
17
WE
18
A17
19
A16
20
A15
21
A14
22
A13
LP62S16256FV-T
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2423A11
A5
A6
A7
OE
HB
LB
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A12
A
LB
I/O9
B
I/O10
C
GND
D
VCC
E
I/O15
F
I/O16
G
NC A8NCA9
H
OE
HB
I/O11
I/O12
I/O13
I/O14
A0
A1 A2 NC
A3
A4
A5 A6
A17NCA7
A16
A14 A15
A12
A13
A10 A11 NC
CE
I/O2
I/O4
I/O5
I/O6
WE
654321
I/O1
I/O3
VCC
GND
I/O7
I/O8
PRELIMINARY (August, 2001, Version 0.2) 1 AMIC Technology, Inc.
Page 2
LP62S16256F-T Series
Block Diagram
INPUT
DATA
CIRCUIT
VCC
GND
I/O
I/O16
9
A0
A16
A17
I/O
1
I/O8
DECODER
INPUT
DATA
CIRCUIT
512 X 8192
MEMORY ARRAY
COLUMN I/O
CE
LB
HB
OE
WE
CONTROL
CIRCUIT
Pin Descriptions -- TSOP
Pin No. Symbol Description
1 - 5, 18 - 27,
42 - 44
6
7 - 10, 13 - 16,
29 - 32, 35 - 38
17
39
40
41
A0 - A17 Address Inputs
CE
Chip Enable Input
I/O1 - I/O16 Data Inputs/Outputs
WE
LB
HB
OE
Write Enable Input
Lower Byte Enable Input (I/O1 to I/O8)
Higher Byte Enable Input (I/O9 to I/O16)
Output Enable Input
11, 33 VCC Power
12, 34 GND Ground
28 NC No Connection
PRELIMINARY (August, 2001, Version 0.2) 2 AMIC Technology, Inc.
Page 3
LP62S16256F-T Series
Pin Description - CSP
Symbol Description Symbol Description
A0 - A17 Address Inputs
CE
I/O1 - I/O16 Data Input/Output VCC Power Supply
WE
LB
Chip Enable
Write Enable Input GND Ground
Byte Enable Input
(I/O1 - I/O8)
HB
OE
NC No Connection
Higher Byte Enable Input
(I/O9 - I/O16)
Output Enable
Recommended DC Operating Conditions
(TA = -25°C to + 85°C)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 2.7 3 3.3 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.2 - VCC + 0.3 V
VIL Input Low Voltage -0.3 - +0.6 V
CL Output Load - - 30 pF
TTL Output Load - - 1 -
PRELIMINARY (August, 2001, Version 0.2) 3 AMIC Technology, Inc.
Page 4
LP62S16256F-T Series
Absolute Maximum Ratings*
VCC to GND ..............................................-0.5V to +4.0V
IN, IN/OUT Volt to GND...................-0.5V to VCC + 0.5V
Operating Temperature, Topr...................-25°C to +85°C
Storage Temperature, Tstg.....................-55°C to +125°C
Power Dissipation, PT......................................................................0.7W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.3V, GND = 0V)
Symbol Parameter
Min. Max.
ILI
ILO
ICC
Input Leakage Current
Output Leakage Current
Active Power Supply
Current
LP62S16256F-70LLT
- 1
-
- 5 mA
1
Unit Conditions
VIN = GND to VCC
µA
CE = VIH
µA
LB = HB = VIH
VI/O = GND to VCC
CE = VIL,
LB = VIL or HB = VIL , II/O = 0mA
ICC1 - 40 mA
Dynamic Operating
Current
ICC2
ISB - 1 mA
Standby Current
ISB1
VOL Output Low Voltage - 0.4 V IOL = 2.1 mA
VOH Output High Voltage 2.2 - V IOH = -1.0 mA
- 15 mA
- 10
Min. Cycle, Duty = 100%
CE = VIL , LB = VIL or HB = VIL , II/O = 0mA
CE ≤ 0.2V
LB ≤ 0.2V or HB ≤ 0.2V
II/O = 0 mA
CE = VIH or LB = HB = VIH
CE ≥ VCC - 0.2V or LB = HB ≥ VCC - 0.2V
µA
VIN ≥ VCC - 0.2V or VIN ≤ 0.2V
PRELIMINARY (August, 2001, Version 0.2) 4 AMIC Technology, Inc.
Page 5
LP62S16256F-T Series
CE OE WE LB HB
Truth Table
I/O1 to I/O8 Mode I/O9 to I/O16 Mode VCC Current
H X X X X Not selected Not selected ISB1, ISB
X X X H H High - Z High - Z ISB1, ISB
L L Read Read ICC1, ICC2, ICC
L L H L H Read High - Z ICC1, ICC2, ICC
H L High - Z Read ICC1, ICC2, ICC
L L Write Write ICC1, ICC2, ICC
L X L L H Write High - Z ICC1, ICC2, ICC
H L High - Z Write ICC1, ICC2, ICC
L H H L X High - Z High - Z ICC1, ICC2, ICC
L H H X L High - Z High - Z ICC1, ICC2, ICC
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance 6 pF VIN = 0V
CI/O* Input/Output Capacitance 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY (August, 2001, Version 0.2) 5 AMIC Technology, Inc.
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LP62S16256F-T Series
AC Characteristics (TA = -25°C to +85°C, VCC = 2.7V to 3.3V)
Symbol Parameter
Min. Max.
Read Cycle
tRC Read Cycle Time 70 - ns
tAA Address Access Time - 70 ns
tACE Chip Enable Access Time - 70 ns
tBE Byte Enable Access Time - 70 ns
tOE Output Enable to Output Valid - 35 ns
tCLZ Chip Enable to Output in Low Z 10 - ns
tBLZ Byte Enable to Output in Low Z 10 - ns
tOLZ Output Enable to Output in Low Z 5 - ns
tCHZ Chip Disable to Output in High Z - 25 ns
tBHZ Byte Disable to Output in High Z - 25 ns
tOHZ Output Disable to Output in High Z - 25 ns
tOH Output Hold from Address Change 5 - ns
Write Cycle
LP62S16256F-70LLT
Unit
tWC Write Cycle Time 70 - ns
tCW Chip Enable to End of Write 60 - ns
tBW Byte Enable to End of Write 60 - ns
tAS Address Setup Time 0 - ns
tAW Address Valid to End of Write 60 - ns
tWP Write Pulse Width 50 - ns
tWR Write Recovery Time 0 - ns
tWHZ Write to Output in High Z - 25 ns
tDW Data to Write Time Overlap 30 - ns
tDH Data Hold from Write Time 0 - ns
tOW Output Active from End of Write 5 - ns
Note: tBLZ, tOLZ, tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
PRELIMINARY (August, 2001, Version 0.2) 6 AMIC Technology, Inc.
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LP62S16256F-T Series
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
Read Cycle 2
Address
CE
HB, LB
OE
DOUT
(1, 2, 3)
tRC
tAA
tCLZ
tACE
5
tBE
5
tBLZ
tOE
5
tOLZ
tOHZ
tBHZ
5
tCHZ
5
5
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and (HB and, or LB) transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (August, 2001, Version 0.2) 7 AMIC Technology, Inc.
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LP62S16256F-T Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
tWC
Address
3
tAW
tCW
CE
tBW
HB, LB
tWR
WE
DATA IN
DATA OUT
1
tAS
4
tWHZ
tWP
2
tDW
tDH
tOW
PRELIMINARY (August, 2001, Version 0.2) 8 AMIC Technology, Inc.
Page 9
LP62S16256F-T Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
CE
HB, LB
WE
DATA IN
DATA OUT
tAW
tWP
tCW
2
tBW
tDW
1
tAS
4
tWHZ
tWR
3
tDH
tOW
PRELIMINARY (August, 2001, Version 0.2) 9 AMIC Technology, Inc.
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LP62S16256F-T Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
tWC
Address
tAW
tCW
CE
3
tWR
HB, LB
WE
tWP
tBW
2
1
tAS
tDH
tOW
DATA IN
DATA OUT
tWHZ
tDW
4
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and , or LB ).
3. tWR is measured from the earliest of CE or WE or (HB and , or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (August, 2001, Version 0.2) 10 AMIC Technology, Inc.
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LP62S16256F-T Series
AC Test Conditions
Input Pulse Levels 0.4V to 2.4V
Input Rise And Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
TTL
CL
30pF
* Including scope and jig. * Including scope and jig.
CL
TTL
5pF
Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -25°C to 85°C)
Symbol Parameter Min. Max. Unit Conditions
VDR VCC for Data Retention 2.0 3.3 V
ICCDR
Data Retention Current
-
5*
µA
CE ≥ VCC - 0.2V
or LB = HB ≥ VCC - 0.2V
VCC = 2.0V,
CE ≥ VCC - 0.2V or
LB = HB ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or VIN ≤ 0.2V
tCDR Chip Disable to Data Retention Time 0 - ns
tR Operation Recovery Time tRC - ns
tVR VCC Rising Time from Data Retention
5 - ms
See Retention Waveform
Voltage to Operating Voltage
* LP62S16256F-70LLT ICCDR: max. 1.5µA at TA = 0°C to + 40°C
PRELIMINARY (August, 2001, Version 0.2) 11 AMIC Technology, Inc.
Page 12
LP62S16256F-T Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
2.0VV
DR
≥
0.2VVCE
−≥ DR
2.7V
tR
tVR
VIH
VCC
CE
2.7V
tCDR
VIH
Ordering Information
Part No. Access Time (ns) Operating Current
Max. (mA)
LP62S16256FV-70LLT
70
40 10 44L TSOP
LP62S16256FU-70LLT 40 10 48L CSP
Standby Current
Max. (µµA)
Package
PRELIMINARY (August, 2001, Version 0.2) 12 AMIC Technology, Inc.
Page 13
LP62S16256F-T Series
Package Information
TSOP 44L TYPE II Outline Dimensions unit: inches/mm
44
23
0.254
L
L1
c
L
L1
1
S B
E
HE
D
e
D
22
A
y
A1 A2
Symbol
A - - 0.047 - - 1.20
A1 0.002 - - 0.05 - A2 0.037 0.039 0.041 0.95 1.00 1.05
B 0.010 0.014 0.018 0.25 0.35 0.45
c - 0.006 - - 0.15 -
D 0.721 0.725 0.729 18.31 18.41 18.51
E 0.396 0.400 0.404 10.06 10.16 10.26
e - 0.031 - - 0.80 HE 0.455 0.463 0.471 11.56 11.76 11.96
L 0.016 0.020 0.024 0.40 0.50 0.60
L1 - 0.031 - - 0.80 -
S - - 0.036 - - 0.93
y - - 0.004 - - 0.10
θ 0°
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
-
5° 0°
-
5°
Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
PRELIMINARY (August, 2001, Version 0.2) 13 AMIC Technology, Inc.
Page 14
LP62S16256F-T Series
Package Information
48LD CSP ( 6 x 8 mm ) Outline Dimensions unit: mm
(48TFBGA)
TOP VIEW
Ball*A1 CORNER
1 2 3 4 5 6
A
B
C
D
E
F
G
H
SIDE VIEW
2
A
// 0.25 C
C
SEATING PLANE
(0.36)
Symbol
0.10 C
1
A
A
Dimensions in mm
MIN.
NOM. MAX.
e
1
E
E
B e
A
0.20(4X)
BOTTOM VIEW
Ball#A1 CORNER
S
0.10 C
C
0.25SA B
b (48X)
D
1
D
123456
A
B
C
D
E
F
G
H
A 1.04 1.14 1.24
A1 0.20 0.25 0.30
A2 0.48 0.53 0.58
D 5.90 6.00 6.10
E 7.90 8.00 8.10
D1 --- 3.75 ---
E1 --- 5.25 ---
e --- 0.75 ---
b 0.30 0.35 0.40
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD)
PRELIMINARY (August, 2001, Version 0.2) 14 AMIC Technology, Inc.
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