Datasheet LP62S1024AX-70LLI, LP62S1024AX-55LLI, LP62S1024AV-70LLI, LP62S1024AV-55LLI Datasheet (AMIC)
Page 1
LP62S1024A-I Series
Preliminary 128K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.7V to 3.6V
n Access times: 55/70 ns (max.)
n Current:
Very low power version: Operating:(70NS)30mA(max.)
(55NS)40mA(max.)
Standby: 5uA (max.)
n Full static operation, no clock or refreshing required
General Description
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
n Data retention voltage: 2V (min.)
n Available in 32-pin TSOP, TSSOP (8X13.4mm)
packages
The LP62S1024A-I is a low operating current 1,048,576bit static random access memory organized as 131,072
words by 8 bits and operates on a low power voltage:
2.7V to 3.6V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
nn TSOP/TSSOP
16
(LP62S1024AX-I)
17
1
LP62S1024AV-I
32
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin No.
1 2A93 4 5 6 7 8 9 10 11 12 13 14
Pin
Name
Pin No.
Pin
Name
A8 A13 CE2 A15 VCC NC
A11 WE
A3 A2 A1 A0 I/O1 I/O2 GND I/O4 I/O5 I/O6 I/O7
I/O3
A16 A14 A12 A7 A6
15 16
A5 A4
302928272625242219 2120 231817
31 32
I/O8
CE1
A10 OE
PRELIMINARY (August, 2001, Version 0.1) 1 AMIC Technology, Inc.
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LP62S1024A-I Series
Block Diagram
A0
A14
A15
A16
I/O1
I/O8
CE2
CE1
OE
WE
CONTROL
CIRCUIT
Pin Description – TSOP/TSSOP
Pin No. Symbol Description
ROW
DECODER
INPUT DATA
CIRCUIT
VCC
GND
512 X 2048
MEMORY ARRAY
COLUMN I/O
1 - 4, 7,
10 - 20, 31
5
A0 - A16 Address Inputs
WE
6 CE2 Chip Enable
8 VCC Power Supply
9 NC No Connection
21 - 23,
25 - 29
I/O1 - I/O8 Data Input/Outputs
24 GND Ground
30
32
CE1
OE
Write Enable
Chip Enable
Output Enable
PRELIMINARY (August, 2001, Version 0.1) 2 AMIC Technology, Inc.
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LP62S1024A-I Series
Recommended DC Operating Conditions
(TA = -40°C to +85°C)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 2.7 3.0 3.6 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.0 - VCC + 0.3 V
VIL Input Low Voltage -0.3 - +0.6 V
CL Output Load - - 30 pF
TTL Output Load - - 1 -
PRELIMINARY (August, 2001, Version 0.1) 3 AMIC Technology, Inc.
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LP62S1024A-I Series
Absolute Maximum Ratings*
VCC to GND .............................................. -0.5V to +4.6V
IN, IN/OUT Volt to GND.....................-0.5V to VCC +0.5V
Operating Temperature, Topr...................-40°C to +85°C
Storage Temperature, Tstg..................... -55°C to +125°C
Temperature Under Bias, Tbias................ -10°C to +85°C
Power Dissipation, PT ...............................................0.7W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -40°C to +85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol Parameter
Min. Max.
ILI
ILO
ICC
Input Leakage
Current
Output Leakage
Current
Active Power Supply
Current
LP62S1024A-55LLI/70LLI
- 1
- 1
- 3 mA
Unit Conditions
µA
µA
VIN = GND to VCC
CE1 = VIH or CE2 = VIL
VI/O = GND to VCC
CE1 = VIL, CE2 = VIH
II/O = 0mA
ICC1
ICC2
Dynamic Operating
Current
- -70NS:30
mA
- -55NS:40
- 5 mA
Min. Cycle, Duty = 100%
CE1 = VIL, CE2 = VIH
II/O = 0mA
CE1 = VIL, CE2 = VIH
f = 1 MHZ, II/O = 0mA
PRELIMINARY (August, 2001, Version 0.1) 4 AMIC Technology, Inc.
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LP62S1024A-I Series
CE1
OE WE
DC Electrical Characteristics (continued)
Symbol Parameter
Min. Max.
ISB - 0.5 mA
ISB1 Standby Power
Supply Current
ISB2 - 5
VOL
VOH
Output Low
Voltage
Output High
Voltage
LP62S1024A-55LLI/70LLI
- 5
- 0.4 V IOL = 2.1mA
2.2 - V IOH = -1.0mA
Truth Table
Mode
Standby
H X X X High Z ISB, ISB1
CE2
Unit Conditions
CE1 = VIH or CE2 =VIL
CE1 ≥ VCC - 0.2V , CE2 ≥ VCC - 0.2V
µA
µA
VIN ≥ VCC - 0.2V or VIN ≤ 0.2V
CE1 ≤ 0.2V , CE2 ≤ 0.2V
VIN ≥ VCC - 0.2V or VIN ≤ 0.2V
I/O Operation Supply Current
X L X X High Z ISB, ISB2
Output Disable L H H H High Z ICC, ICC1, ICC2
Read L H L H DOUT ICC, ICC1, ICC2
Write L H X L DIN ICC, ICC1, ICC2
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance 6 pF VIN = 0V
CI/O* Input/Output Capacitance 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY (August, 2001, Version 0.1) 5 AMIC Technology, Inc.
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LP62S1024A-I Series
AC Characteristics (TA = -40°C to +85°C, VCC = 2.7V to 3.6V)
Symbol Parameter
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 - 70 - ns
tAA Address Access Time - 55 - 70 ns
tACE1
tACE2 CE2 - 55 - 70 ns
tOE Output Enable to Output Valid - 30 - 35 ns
tCLZ1
tCLZ2 CE2 10 - 10 - ns
tOLZ Output Enable to Output in Low Z 5 - 5 - ns
tCHZ1
tCHZ2 CE2 0 20 0 25 ns
tOHZ Output Disable to Output in High Z 0 20 0 25 ns
Chip Enable Access Time
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
CE1
CE1
CE1
LP62S1024A-55LLI LP62S1024A-70LLI
- 55 - 70 ns
10 - 10 - ns
0 20 0 25 ns
Unit
tOH Output Hold from Address Change 5 - 10 - ns
Write Cycle
tWC Write Cycle Time 55 - 70 - ns
tCW Chip Enable to End of Write 50 - 60 - ns
tAS Address Setup Time 0 - 0 - ns
tAW Address Valid to End of Write 50 - 60 - ns
tWP Write Pulse Width 40 - 50 - ns
tWR Write Recovery Time 0 - 0 - ns
tWHZ Write to Output in High Z 0 25 0 25 ns
tDW Data to Write Time Overlap 25 - 30 - ns
tDH Data Hold from Write Time 0 - 0 - ns
tOW Output Active from End of Write 5 - 5 - ns
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY (August, 2001, Version 0.1) 6 AMIC Technology, Inc.
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LP62S1024A-I Series
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
Read Cycle 2
CE1
DOUT
Read Cycle 3
CE2
(1, 3, 4, 6)
(1, 4, 7, 8)
tACE1
5
tCLZ1
tCHZ1
5
tACE2
5
tCLZ2
5
tCHZ2
DOUT
PRELIMINARY (August, 2001, Version 0.1) 7 AMIC Technology, Inc.
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LP62S1024A-I Series
Timing Waveforms (continued)
Read Cycle 4
Address
(1)
tRC
tAA
OE
CE1
CE2
DOUT
tCLZ1
tCLZ2
tOE
5
tOLZ
tACE1
5
tACE2
5
tCHZ2
tOH
tCHZ1
5
5
tOHZ
5
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
PRELIMINARY (August, 2001, Version 0.1) 8 AMIC Technology, Inc.
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LP62S1024A-I Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
Address
(6)
tWC
CE1
CE2
WE
DOUT
DIN
tAW
5
tCW
(4)
(4)
1
tAS
tWHZ
tWP
2
tDW
tWR
tDH
3
tOW
PRELIMINARY (August, 2001, Version 0.1) 9 AMIC Technology, Inc.
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LP62S1024A-I Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
3
CE1
tAW tWR
5
tCW
(4)
1
tAS
CE2
WE
DIN
DOUT
(4)
5
tCW
2
tWP
tWHZ
tDW
7
tDH
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE.
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (August, 2001, Version 0.1) 10 AMIC Technology, Inc.
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LP62S1024A-I Series
AC Test Conditions
Input Pulse Levels 0.4V to 2.4V
Input Rise and Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
TTL
CL
30pF
* Including scope and jig. * Including scope and jig.
CL
TTL
5pF
Figure 1. Output Load Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = -40°C to 85°C)
Symbol Parameter Min. Max. Unit Conditions
VDR1 2.0 3.6 V
VCC for Data Retention
VDR2
ICCDR1
2.0 3.6 V
-
3*
Data Retention Current
ICCDR2
-
3*
µA
µA
CE1 ≥ VCC - 0.2V
CE2 ≤ 0.2V
VCC = 2V,
CE1 ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or VIN ≤ 0.2V
VCC = 2V,
CE2 ≤ 0.2V
VIN ≥ VCC - 0.2V or VIN ≤ 0.2V
tCDR Chip Disable to Data Retention Time 0 - ns
See Retention Waveform
tR Operation Recovery Time 5 - ms
* LP62S1024A-55LLI/70LLI ICCDR: max. IµA at TA = 0°C to + 40°C
PRELIMINARY (August, 2001, Version 0.1) 11 AMIC Technology, Inc.
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LP62S1024A-I Series
CE1
Low VCC Data Retention Waveform (1) (
Controlled)
DATA RETENTION MODE
VCC
CE1
3.0V
tCDR
VIH
VDR ≥ 2V
CE1 ≥ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
3.0V
tCDR
VIL
VDR ≥ 2V
CE2 ≤ 0.2V
3.0V
tR
VIH
3.0V
tR
VIL
PRELIMINARY (August, 2001, Version 0.1) 12 AMIC Technology, Inc.
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LP62S1024A-I Series
Ordering Information
Part No. Access Time (ns)
LP62S1024AV-55LLI 40 5 32L TSOP
LP62S1024AX-55LLI 40 5 32L TSSOP
LP62S1024AV-70LLI 30 5 32L TSOP
LP62S1024AX-70LLI 30 5 32L TSSOP
Operating Current
Max. (mA)
Standby Current
Max. (µµA)
Package
PRELIMINARY (August, 2001, Version 0.1) 13 AMIC Technology, Inc.
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LP62S1024A-I Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm
D
e
0.25
BSC
Detail "A"
°12.0
LE
b
A
θ
L
0.10(0.004) M
A2
E
HD
Detail "A"
y
D
c
GAUGE PLANE
A1
S
Symbol Dimensions in inches Dimensions in mm
A 0.047 Max. 1.20 Max.
A1 0.004±0.002 0.10±0.05
A2 0.039±0.002 1.00±0.05
b 0.008±0.001 0.20±0.03
c 0.006±0.001 0.15±0.02
D 0.724±0.004 18.40±0.10
E 0.315±0.004 8.00±0.10
e 0.020 TYP. 0.50 TYP.
HD 0.787±0.007 20.00±0.20
L 0.020±0.004 0.50±0.10
LE 0.031 TYP. 0.80 TYP.
S 0.0167 TYP. 0.425 TYP.
Y 0.004 Max. 0.10 Max.
θ 0° ~ 6° 0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY (August, 2001, Version 0.1) 14 AMIC Technology, Inc.
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LP62S1024A-I Series
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm
e
0.25
BSC
Detail "A"
Detail "A"
°.012
A
θ
L
LE
b
0.10MM
D
SEATING PLANE
A2
E
D1
D
Detail "A"
c
GAUGE PLANE
A1
S
Symbol Dimensions in inches Dimensions in mm
A 0.049 Max. 1.25 Max.
A1 0.002 Min. 0.05 Min.
A2 0.039±0.002 1.00±0.05
b 0.008±0.001 0.20±0.03
c 0.006±0.0003 0.15±0.008
E 0.315±0.004 8.00±0.10
e 0.020 TYP. 0.50 TYP.
D 0.528±0.008 13.40±0.20
D1 0.465±0.004 11.80±0.10
L 0.02±0.008 0.50±0.20
LE 0.0266 Min. 0.675 Min.
S 0.0109 TYP. 0.278 TYP.
y 0.004 Max. 0.10 Max.
θ 0° ~ 6° 0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY (August, 2001, Version 0.1) 15 AMIC Technology, Inc.
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