Datasheet LP62E16512U-70LLT Datasheet (AMIC)

LP62E16512-T Series

Preliminary 512K X 16 BIT LOW VOLTAGE CMOS SRAM

Document Title
512K X 16 BIT LOW VOLTAGE CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue April 26, 2002 Preliminary

PRELIMINARY (April, 2002, Version 0.0) AMIC Technology, Inc.

LP62E16512-T Series

Preliminary 512K X 16 BIT LOW VOLTAGE CMOS SRAM

Features

n Operating voltage: 1.65V to 2.2V
n Access times: 70 ns (max.)
n Current:

Very low power version: Operating: 40mA (max.)
Standby: 10µA (max.)

n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 1.2V (min.)
n Available in 48-ball CSP (8×10mm) packages

General Description

The LP62E16512-T is a low operating current 8,388,608­bit static random access memory organized as 524,288
words by 16 bits and operates on low power voltage from

1.65V to 2.2V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 1.2V.

Product Family

Product

Family

Operating

Temperature

VCC Range

Speed

Retention

(ICCDR, Typ.)

LP62E16512

-25°C ~ +85°C

1.65V~2.2V 70ns

1. Typical values are measured at VCC = 1.8V, TA = 25°C and not 100% tested.

2. Data retention current VCC = 1.2V.

Power Dissipation

Data

0.1µA 0.5µA

Pin Configurations

nn CSP (Chip Size Package)
48-pin Top View

A0

A

LB

I/O9

B

I/O10

C

GND

D

VCC

E

I/O15

F

I/O16

G

A18 A8NCA9

H

OE

HB
I/O11
I/O12
I/O13
I/O14

A1 A2 CS2

A3

A4

A5 A6

A17NCA7

A16
A14 A15
A12

A13

A10 A11 NC

CS1
I/O2
I/O4
I/O5
I/O6

WE

Standby

(ISB1, Typ.)

654321

I/O1

I/O3
VCC
GND

I/O7

I/O8

Operating

Package

(ICC2, Typ.)

3mA 48 CSP

Type

PRELIMINARY (April, 2002, Version 0.0) 1 AMIC Technology, Inc.

LP62E16512-T Series

Block Diagram

VCC
GND

INPUT

DATA

CIRCUIT

I/O9

I/O

16

A17

A18

I/O1

I/O8

CS1

A0

LB

CS2

LB

HB
OE
WE

CONTROL

CIRCUIT

DECODER

INPUT

DATA

CIRCUIT

1024 X 8192

MEMORY ARRAY

COLUMN I/O

PRELIMINARY (April, 2002, Version 0.0) 2 AMIC Technology, Inc.

LP62E16512-T Series

Pin Description - CSP

Symbol Description Symbol Description

A0 - A18 Address Inputs

1CS , CS2

I/O1 - I/O16 Data Input/Output VCC Power Supply

WE

LB

Chip Enable

Write Enable Input GND Ground

Byte Enable Input
(I/O1 - I/O8)

HB

OE

NC No Connection

Higher Byte Enable Input
(I/O9 - I/O16)

Output Enable

Recommended DC Operating Conditions

(TA = -25°C to + 85°C)

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 1.65 1.8 2.2 V

GND Ground 0 0 0 V

VIH Input High Voltage 1.4 - VCC + 0.3 V

VIL Input Low Voltage -0.3 - +0.4 V

CL Output Load - - 30 pF

TTL Output Load - - 1 -

PRELIMINARY (April, 2002, Version 0.0) 3 AMIC Technology, Inc.

LP62E16512-T Series

Absolute Maximum Ratings*

VCC to GND ..............................................-0.5V to +3.0V

IN, IN/OUT Volt to GND................... -0.5V to VCC + 0.5V

Operating Temperature, Topr...................-25°C to +85°C

Storage Temperature, Tstg.....................-55°C to +125°C

Power Dissipation, PT......................................................................0.7W

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 1.65V to 2.2V, GND = 0V)

Symbol Parameter

Min. Max.

ILI

Input Leakage Current - 1

ILO

ICC

Output Leakage Current

Active Power Supply
Current

LP62E16512-70LLT

-

1

- 5 mA

Unit Conditions

VIN = GND to VCC

µA

µA

1CS = VIH or CS2 = VIL or

LB = HB = VIH
VI/O = GND to VCC

1CS = VIL , CS2 = VIH ,

LB = VIL or HB = VIL , II/O = 0mA

ICC1

- 40 mA
CS2 = VIH , LB = VIL or HB = VIL

Min. Cycle, Duty = 100%, 1CS = VIL ,

ICC2

Dynamic Operating
Current

- 5 mA

II/O = 0mA

1CS ≤ 0.2V, CS2 ≥ VCC-0.2V ,

LB ≤ 0.2V or HB ≤ 0.2V

f = 1MHz , II/O = 0mA

ISB - 1 mA

Standby Current

ISB1

- 10

µA

1CS = VIH or CS2 = VIL or

LB = HB = VIH

1CS ≥ VCC - 0.2V or CS2 ≤ 0.2V or

LB = HB ≥ VCC-0.2V
VIN ≥ VCC-0.2V or VIN ≤ 0.2V

VOL Output Low Voltage - 0.2 V IOL = 0.1 mA

VOH Output High Voltage 1.4 - V IOH = -1.0 mA

PRELIMINARY (April, 2002, Version 0.0) 4 AMIC Technology, Inc.

LP62E16512-T Series

OE WE LB HB

Truth Table

CS2

1CS

H X X X X X High - Z High - Z ISB1, ISB

X L X X X X High - Z High - Z ISB1, ISB

X X X X H H High - Z High - Z ISB1, ISB

L L Read Read ICC1, ICC2, ICC

L H L H L H Read High - Z ICC1, ICC2, ICC

H L High - Z Read ICC1, ICC2, ICC

L L Write Write ICC1, ICC2, ICC

L H X L L H Write High - Z ICC1, ICC2, ICC

H L High - Z Write ICC1, ICC2, ICC

L H H H L X High - Z High - Z ICC1, ICC2, ICC

L H H H X L High - Z High - Z ICC1, ICC2, ICC

Note: X = H or L

I/O1 to I/O8 Mode I/O9 to I/O16 Mode VCC Current

Capacitance (TA = 25°C, f = 1.0MHz)

Symbol Parameter Min. Max. Unit Conditions

CIN* Input Capacitance 6 pF VIN = 0V

CI/O* Input/Output Capacitance 8 pF VI/O = 0V

* These parameters are sampled and not 100% tested.

PRELIMINARY (April, 2002, Version 0.0) 5 AMIC Technology, Inc.

LP62E16512-T Series

AC Characteristics (TA = -25°C to +85°C, VCC = 1.65V to 2.2V)

Symbol Parameter

Min. Max.

Read Cycle

tRC Read Cycle Time 70 - ns
tAA Address Access Time - 70 ns

tAcs1 , tAcs2 Chip Enable Access Time - 70 ns

tBE Byte Enable Access Time - 70 ns
tOE Output Enable to Output Valid - 35 ns

tCLZ1 , tCLZ2 Chip Enable to Output in Low Z 10 - ns

tBLZ Byte Enable to Output in Low Z 10 - ns
tOLZ Output Enable to Output in Low Z 5 - ns

tCHZ1 , tCHZ2 Chip Disable to Output in High Z - 25 ns

tBHZ Byte Disable to Output in High Z - 25 ns
tOHZ Output Disable to Output in High Z - 25 ns

tOH Output Hold from Address Change 5 - ns

Write Cycle

LP62E16512-70LLT

Unit

tWC Write Cycle Time 70 - ns

tCW1 , tCW2 Chip Enable to End of Write 60 - ns

tBW Byte Enable to End of Write 60 - ns

tAS Address Setup Time 0 - ns
tAW Address Valid to End of Write 60 - ns
tWP Write Pulse Width 50 - ns

tWR Write Recovery Time 0 - ns

tWHZ Write to Output in High Z - 25 ns

tDW Data to Write Time Overlap 30 - ns

tDH Data Hold from Write Time 0 - ns

tOW Output Active from End of Write 5 - ns

Note: tCLZ1 , tCLZ2 , tBLZ , tOLZ , tCHZ1, tCHZ2 , tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the

open circuit condition and are not referred to output voltage levels.

PRELIMINARY (April, 2002, Version 0.0) 6 AMIC Technology, Inc.

LP62E16512-T Series

Timing Waveforms

Read Cycle 1

Address

DOUT

(1, 2, 4)

tRC

tAA

tOH

tOH

Read Cycle 2

Address

CS1

CS2

HB, LB

OE

DOUT

(1, 2, 3)

tRC

tAA

tCLZ1 , tCLZ2

tACS1 , tACS2

5

tBLZ

5

tOLZ

tBE

tOE

tOHZ

tCHZ1

tBHZ

5

, tCHZ2

5

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled 1CS = VIL, or CS2 = VIH ,HB = VIL and, or LB = VIL.

3. Address valid prior to or coincident with 1CS and (HB and, or LB ) transition low or CS2 transition High.

4. OE = VIL.

5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (April, 2002, Version 0.0) 7 AMIC Technology, Inc.

LP62E16512-T Series

Timing Waveforms (continued)

Write Cycle 1
(Write Enable Controlled)

tWC

Address

3

tAW

tCW

CS1

CS2

tBW

HB, LB

tWR

WE

DATA IN

DATA OUT

1

tAS

4

tWHZ

tWP

2

tDW

tDH

tOW

PRELIMINARY (April, 2002, Version 0.0) 8 AMIC Technology, Inc.

LP62E16512-T Series

Timing Waveforms (continued)

Write Cycle 2
(Chip Enable Controlled)

tWC

Address

CS1

CS2

HB, LB

WE

DATA IN

DATA OUT

tAW

1

tAS

4

tWHZ

tWP

tCW1 , tCW

tBW

2

tDW

tWR

3

tDH

tOW

PRELIMINARY (April, 2002, Version 0.0) 9 AMIC Technology, Inc.

LP62E16512-T Series

Timing Waveforms (continued)

Write Cycle 3
(Byte Enable Controlled)

tWC

Address

tAW

tCW1 , tCW2

CS1

3

tWR

CS2

HB, LB

1

tAS

tBW

2

tWP

WE

tDH

tOW

DATA IN

DATA OUT

tWHZ

tDW

4

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP, tBW) of a low 1CS , WE and (HB and , or LB ) or a high CS2.

3. tWR is measured from the earliest of 1CS or WE or (HB and , or LB ) going high or CS2 going Low to the end of
the Write cycle.

4. OE level is high or low.

5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (April, 2002, Version 0.0) 10 AMIC Technology, Inc.

LP62E16512-T Series

AC Test Conditions

Input Pulse Levels 0.2V to VCC-0.2V

Input Rise And Fall Time 5 ns

Input and Output Timing Reference Levels 0.8V

Output Load See Figures 1 and 2

TTL

CL

30pF

* Including scope and jig. * Including scope and jig.

CL

TTL

5pF

Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2 , tBHZ , tBLZ ,

tOLZ, tCHZ1, tCHZ2 , tOHZ, tWHZ, and tOW

Data Retention Characteristics (TA = -25°C to 85°C)

Symbol Parameter Min. Max. Unit Conditions

1CS ≥ VCC - 0.2V or

VDR VCC for Data Retention 1.2 2.2 V

ICCDR Data Retention Current

- 0.2*

µA

CS2 ≤ 0.2V or
LB = HB ≥ VCC-0.2V

VCC = 1.2V,

1CS ≥ VCC - 0.2V or

CS2 ≤ 0.2V or
LB = HB ≥ VCC-0.2V

VIN ≥ VCC-0.2V or VIN ≤ 0.2V

tCDR Chip Disable to Data Retention Time 0 - ns

tR Operation Recovery Time tRC - ns

tVR

VCC Rising Time from Data Retention
Voltage to Operating Voltage

5 - ms

See Retention Waveform

* LP62E16512 - 70LLT ICCDR: max. 0.1µA at TA = 25°C
(0.2µA at TA = 0°C to + 40°C )

PRELIMINARY (April, 2002, Version 0.0) 11 AMIC Technology, Inc.

LP62E16512-T Series

Low VCC Data Retention Waveform (1) (CS1 Controlled)

DATA RETENTION MODE

VCC

CS1

VIH

1.65V
tCDR

CS1

VDR ≥ 1.2V

≥

VDR - 0.2V

1.65V
tR

tVR

VIH

Low VCC Data Retention Waveform (2) (CS2 Controlled)

DATA RETENTION MODE

VCC

CS2

VIL

1.65V
tCDR

VDR ≥ 1.2V

0.2VCS2

≤

1.65V
tR

tVR

VIL

Ordering Information

Part No. Access Time(ns)

Operating Current

Max.(mA)

LP62E16512U-70LLT 70 40 10 48L CSP

Standby Current

Max.(uA)

Package

PRELIMINARY (April, 2002, Version 0.0) 12 AMIC Technology, Inc.

LP62E16512-T Series

Package Information
48LD CSP ( 8 x 10 mm ) Outline Dimensions unit: mm

(48TFBGA)

TOP VIEW

Ball*A1 CORNER

1 2 3 4 5 6

BOTTOM VIEW

Ball#A1 CORNER

S

0.10 C
C

0.25SA B

b (48X)

123456

A
B
C
D
E
F
G
H

C

SEATING PLANE

SIDE VIEW

e

1

E

E

B e

A

0.20(4X)

0.10 C

A

A1

D

1

D

A
B
C
D
E
F
G
H

Symbol

Dimensions in mm

MIN.

NOM. MAX.

A --- --- 1.20
A1 0.20 0.25 0.30
A2 0.48 0.53 0.58

D 7.90 8.00 8.10

E 9.90 10.00 10.10

D1 --- 3.75 ---

E1 --- 5.25 ---

e --- 0.75 ---

b 0.30 0.35 0.40

Notes:

1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).

2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.

3. DIMENSION b IS MEASURED AT THE MAXIMUM.

4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.

5. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD)

PRELIMINARY (April, 2002, Version 0.0) 13 AMIC Technology, Inc.