Datasheet LP62E16256CV-70LLT, LP62E16256CU-70LLT, LP62E16256CU-60LLT, LP62E16256CV-60LLT Datasheet (AMIC)

LP62E16256C-T Series

256K X 16 BIT LOW VOLTAGE CMOS SRAM

(August, 2001, Version 1.0) 1 AMIC Technology, Inc.

Features

n Operating voltage: 1.8V to 2.2V
n Access times: 60ns (max) / 70 ns (max.)
n Current:

Very low power version: Operating: 30mA (max.)
Standby: 10µA (max.)

n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 1.2V (min.)
n Available in 44-pin TSOP and 48-ball CSP packages

General Description

The LP62E16256C-T is a low operating current
4,194,304-bit static random access memory organized as
262,144 words by 16 bits and operates on low power
voltage from 1.8V to 2.2V. It is built using AMIC's high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.

The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 1.2V.

Pin Configurations

nn TSOP nn CSP (Chip Size Package)
48-pin Top View

I/O9

I/O10
GND
VCC

I/O15

I/O16

NC A8NCA9

A12

A10 A11 NC

A13

A14 A15

I/O8

I/O7

I/O3

I/O1

GND

VCC

A0
A3
A5 A6

A4

A1 A2 NC

654321

A
B
C
D
E
F
G
H

I/O14

I/O13

I/O12

I/O11

A17NCA7

A16

I/O2
I/O4
I/O5
I/O6

LB

HB

WE

OE

CE

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

A3
A2
A1
A0

CE
I/O1
I/O2
I/O3
I/O4

VCC
GND

I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2423A11

A10

A9

A8

NC

I/O9

I/O10

I/O11

I/O12

VCC

GND

I/O13

I/O14

I/O15

I/O16

LB

HB

OE

A7

A6

LP62E16256CV-T

A13

A5

A4

A12

LP62E16256C-T Series

(August, 2001, Version 1.0) 2 AMIC Technology, Inc.

Block Diagram

DECODER

512 X 8192

MEMORY ARRAY

COLUMN I/O

INPUT

DATA

CIRCUIT

CONTROL

CIRCUIT

VCC
GND

I/O8

I/O

1

A17

A16

A0

WE

HB

INPUT
DATA

CIRCUIT

I/O

9

I/O16

LB

OE

CE

Pin Descriptions -- TSOP

Pin No. Symbol Description

1 - 5, 18 - 27,

42 - 44

A0 - A17 Address Inputs

6

CE

Chip Enable Input

7 - 10, 13 - 16,

29 - 32, 35 - 38

I/O1 - I/O16 Data Inputs/Outputs

17

WE

Write Enable Input

39

LB

Lower Byte Enable Input (I/O1 to I/O8)

40

HB

Higher Byte Enable Input (I/O9 to I/O16)

41

OE

Output Enable Input

11, 33 VCC Power

12, 34 GND Ground

28 NC No Connection

LP62E16256C-T Series

(August, 2001, Version 1.0) 3 AMIC Technology, Inc.

Pin Description - CSP

Symbol Description Symbol Description

A0 - A17 Address Inputs

HB

Higher Byte Enable Input
(I/O9 - I/O16)

CE

Chip Enable

OE

Output Enable

I/O1 - I/O16 Data Input/Output VCC Power Supply

WE

Write Enable Input GND Ground

LB

Byte Enable Input
(I/O1 - I/O8)

NC No Connection

Recommended DC Operating Conditions

(TA = -25°C to + 85°C)

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 1.8 2 2.2 V

GND Ground 0 0 0 V

VIH Input High Voltage 1.4 - VCC + 0.2 V

VIL Input Low Voltage -0.2 - +0.4 V

CL Output Load - - 30 pF

TTL Output Load - - 1 -

LP62E16256C-T Series

(August, 2001, Version 1.0) 4 AMIC Technology, Inc.

Absolute Maximum Ratings*

VCC to GND ..............................................-0.5V to +3.0V

IN, IN/OUT Volt to GND...................-0.5V to VCC + 0.5V

Operating Temperature, Topr...................-25°C to +85°C

Storage Temperature, Tstg.....................-55°C to +125°C

Power Dissipation, PT......................................................................0.7W

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 1.8V to 2.2V, GND = 0V)

Symbol Parameter

LP62E16256C-

60LLT

LP62E16256C-

70LLT

Unit Conditions

Min. Max. Min. Max.

ILI

Input Leakage Current - 1 - 1

µA

VIN = GND to VCC

ILO

Output Leakage Current

-

1

-

1

µA

CE = VIH
HB = VIH or OE = VIH or
WE = VIH

VI/O = GND to VCC

ICC

Active Power Supply
Current

- 5 - 5 mA

CE = VIL, II/O = 0mA

ICC1 - 30 - 30 mA

* Min. Cycle, Duty = 100%

Dynamic Operating

CE = VI, II/O = 0mA

ICC2

Current

- 10 - 10 mA

CE = VIL, VIH = VCC,
VIL = 0V, f = 1MHz,
II/O = 0 mA

ISB - 0.5 - 0.5 mA

CE = VIH

ISB1

Standby Current

- 10 - 10

µA

CE ≥ VCC - 0.2V,
VIN ≥ 0V

VOL Output Low Voltage - 0.2 - 0.2 V IOL = 0.1 mA
VOH Output High Voltage 1.6 - 1.6 - V IOH = -0.1 mA

LP62E16256C-T Series

(August, 2001, Version 1.0) 5 AMIC Technology, Inc.

Truth Table

CE OE WE LB HB

I/O1 to I/O8 Mode I/O9 to I/O16 Mode VCC Current

H X X X X Not selected Not selected ISB1, ISB

X X X H H High - Z High - Z ISB1, ISB

L L Read Read ICC1, ICC2, ICC

L L H L H Read High - Z ICC1, ICC2, ICC

H L High - Z Read ICC1, ICC2, ICC

L L Write Write ICC1, ICC2, ICC

L X L L H Write High - Z ICC1, ICC2, ICC

H L High - Z Write ICC1, ICC2, ICC

L H H L X High - Z High - Z ICC1, ICC2, ICC

L H H X L High - Z High - Z ICC1, ICC2, ICC

Note: X = H or L

Capacitance (TA = 25°C, f = 1.0MHz)

Symbol Parameter Min. Max. Unit Conditions

CIN* Input Capacitance 6 pF VIN = 0V

CI/O* Input/Output Capacitance 8 pF VI/O = 0V

* These parameters are sampled and not 100% tested.

LP62E16256C-T Series

(August, 2001, Version 1.0) 6 AMIC Technology, Inc.

AC Characteristics (TA = -25°C to +85°C, VCC = 1.8V to 2.2V)

Symbol Parameter

LP62E16256C-60LLT LP62E16256C-70LLT

Unit

Min. Max. Min. Max.

Read Cycle

tRC Read Cycle Time 60 - 70 - ns
tAA Address Access Time - 60 - 70 ns

tACE Chip Enable Access Time - 60 - 70 ns

tBE Byte Enable Access Time - 60 - 70 ns

tOE Output Enable to Output Valid - 30 - 35 ns
tCLZ Chip Enable to Output in Low Z 10 - 10 - ns
tBLZ Byte Enable to Output in Low Z 10 - 10 - ns
tOLZ Output Enable to Output in Low Z 5 - 5 - ns
tCHZ Chip Disable to Output in High Z - 25 - 25 ns
tBHZ Byte Disable to Output in High Z - 25 - 25 ns
tOHZ Output Disable to Output in High Z - 25 - 25 ns

tOH Output Hold from Address Change 5 - 5 - ns

Write Cycle

tWC Write Cycle Time 60 - 70 - ns

tCW Chip Enable to End of Write 55 - 60 - ns

tBW Byte Enable to End of Write 55 - 60 - ns

tAS Address Setup Time 0 - 0 - ns

tAW Address Valid to End of Write 55 - 60 - ns

tWP Write Pulse Width 50 - 55 - ns

tWR Write Recovery Time 0 - 0 - ns
tWHZ Write to Output in High Z - 25 - 25 ns

tDW Data to Write Time Overlap 30 - 30 - ns

tDH Data Hold from Write Time 0 - 0 - ns

tOW Output Active from End of Write 5 - 5 - ns

Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.

LP62E16256C-T Series

(August, 2001, Version 1.0) 7 AMIC Technology, Inc.

Timing Waveforms

Read Cycle 1

(1, 2, 4)

tRC

tOH

tAA

tOH

Address

DOUT

Read Cycle 2

(1, 2, 3)

tRC

tAA

Address

tACE

tCHZ

5

CE

HB, LB

tBHZ

5

OE

tCLZ

5

tBE

tBLZ

5

tOE

tOLZ

5

tOHZ

5

DOUT

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled CE = VIL, HB = VIH and, or LB = VIL.

3. Address valid prior to or coincident with CE and (HB and, or LB ) transition low.

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

LP62E16256C-T Series

(August, 2001, Version 1.0) 8 AMIC Technology, Inc.

Timing Waveforms (continued)

Write Cycle 1
(Write Enable Controlled)

tWC

tAW

Address

DATA IN

DATA OUT

WE

HB, LB

CE

tWR

3

tCW

tBW

tAS

1

tWP

2

tDW

tDH

tOW

tWHZ

4

LP62E16256C-T Series

(August, 2001, Version 1.0) 9 AMIC Technology, Inc.

Timing Waveforms (continued)

Write Cycle 2
(Chip Enable Controlled)

tWC

tAW

Address

DATA IN

DATA OUT

WE

HB, LB

CE

tWR

3

tCW

2

tBW

tAS

1

tWP

tDW

tDH

tOW

tWHZ

4

LP62E16256C-T Series

(August, 2001, Version 1.0) 10 AMIC Technology, Inc.

Timing Waveforms (continued)

Write Cycle 3
(Byte Enable Controlled)

tWC

tAW

Address

DATA IN

DATA OUT

WE

HB, LB

CE

tWR

3

tCW

tBW

2

tAS

1

tWP

tDW

tDH

tOW

tWHZ

4

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and , or LB ).

3. tWR is measured from the earliest of CE or WE or (HB and , or LB ) going high to the end of the Write cycle.

4. OE level is high or low.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

LP62E16256C-T Series

(August, 2001, Version 1.0) 11 AMIC Technology, Inc.

AC Test Conditions

Input Pulse Levels 0.2V to Vcc -0.2V

Input Rise And Fall Time 5 ns

Input and Output Timing Reference Levels 0.9V

Output Load See Figures 1 and 2

30pF

* Including scope and jig. * Including scope and jig.

CL

TTL

5pF

CL

TTL

Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW

Data Retention Characteristics (TA = -25°C to 85°C)

Symbol Parameter Min. Max. Unit Conditions

VDR VCC for Data Retention 1.2 2.2 V

CE ≥ VCC - 0.2V

ICCDR

Data Retention Current

-

5*

µA

VCC = 1.2V,

CE ≥ VCC - 0.2V

VIN ≥ 0V

tCDR Chip Disable to Data Retention Time 0 - ns

tR Operation Recovery Time tRC - ns

See Retention Waveform

tVR VCC Rising Time from Data Retention

Voltage to Operating Voltage

5 - ms

* LP62E16256C-70LLT ICCDR: max. 1µA at TA = 0°C to + 40°C
* LP62E16256C-60LLT ICCDR: max. 1µA at TA = 0°C to + 40°C

LP62E16256C-T Series

(August, 2001, Version 1.0) 12 AMIC Technology, Inc.

Low VCC Data Retention Waveform

VCC

CE

tCDR

VIH

1.8V

tR

VIH

1.8V

DATA RETENTION MODE

tVR

VDR ≥ 1.2V

CE ≥ VDR - 0.2V

Ordering Information

Part No. Access Time (ns) Operating Current

Max. (mA)

Standby Current

Max. (µµA)

Package

LP62E16256CV-70LLT

70

30 10 44L TSOP

LP62E16256CU-70LLT 30 10 48L CSP

LP62E16256CV-60LLT

60

30 10 44L TSOP

LP62E16256CU-60LLT 30 10 48L CSP

LP62E16256C-T Series

(August, 2001, Version 1.0) 13 AMIC Technology, Inc.

Package Information
TSOP 44L TYPE II Outline Dimensions unit: inches/mm

44

1

D

E

HE

0.254

L1

L

A1 A2

A

S B

e

D

y

L1

c

L

23

22

Symbol

Dimension in inch Dimension in mm

Min. Nom. Max. Min. Nom. Max.

A - - 0.047 - - 1.20
A1 0.002 - - 0.05 - ­A2 0.037 0.039 0.041 0.95 1.00 1.05

B 0.010 0.014 0.018 0.25 0.35 0.45

c - 0.006 - - 0.15 -

D 0.721 0.725 0.729 18.31 18.41 18.51

E 0.396 0.400 0.404 10.06 10.16 10.26

e - 0.031 - - 0.80 ­HE 0.455 0.463 0.471 11.56 11.76 11.96

L 0.016 0.020 0.024 0.40 0.50 0.60
L1 - 0.031 - - 0.80 -

S - - 0.036 - - 0.93

y - - 0.004 - - 0.10

θ 0°

-

5° 0°

-

5°

Notes:

1. Dimension D&E do not include interlead flash.

2. Dimension B does not include dambar protrusion/intrusion.

3. Dimension S includes end flash.

LP62E16256C-T Series

(August, 2001, Version 1.0) 14 AMIC Technology, Inc.

Package Information
48LD CSP ( 6 x 8 mm ) Outline Dimensions unit: mm

(48TFBGA)

A

1

A

2

A
B
C
D
E

F
G
H

TOP VIEW

Ball#A1 CORNER

SIDE VIEW

C

SEATING PLANE

// 0.25 C

A

(0.36)

A
B
C
D
E

F
G
H

1 2 3 4 5 6

123456

C

0.10 C

S

0.25SA B
b (48X)

BOTTOM VIEW

Ball*A1 CORNER

E

E

1

e

B e

D

1

D

A

0.20(4X)

0.10 C

Dimensions in mm

Symbol

MIN.

NOM. MAX.

A 1.04 1.14 1.24
A1 0.20 0.25 0.30
A2 0.48 0.53 0.58

D 5.90 6.00 6.10

E 7.90 8.00 8.10

D1 --- 3.75 ---

E1 --- 5.25 ---

e --- 0.75 ---

b 0.30 0.35 0.40

Note:

1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).

2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.

3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF

THE SOLDER BALL AND THE BODY EDGE.