Datasheet LP621024DX-55LL, LP621024DV-70LL, LP621024DV-55LL, LP621024DM-55LL, LP621024D-55LL Datasheet (AMIC)

LP621024D Series

128K X 8 BIT CMOS SRAM

Features

n Single +5V power supply
n Access times: 55/70 ns (max.)
n Current:

Very low power version: Operating: 70mA (max.)
Standby: 25µA (max.)

n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible

General Description

The LP621024D is a low operating current 1,048,576-bit
static random access memory organized as 131,072
words by 8 bits and operates on a single 5V power
supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.

n Common I/O using three-state output
n Output enable and two chip enable inputs for easy

application

n Data retention voltage: 2V (min.)
n Available in 32-pin DIP, SOP TSOP and TSSOP

(8 X 13.4mm) packages

Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.

Pin Configurations

nn DIP nn SOP nn TSOP/(TSSOP)

NC
A16
A14

A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O1
I/O2
I/O3

1
2

3
4
5
6

LP621024D

7
8
9
10
11
12
13
14
15
16 17

VCC

32

A15

31

CE2

30

WE

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23
22

CE1
I/O8

21

I/O7

20

I/O6

19

I/O5

18

I/O4GND

NC
A16
A14

A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O1
I/O2
I/O3

1
2

3
4
5
6
7
8
9
10
11
12
13
14
15
16 17

32
31
30
29
28

LP621024DM

27
26
25
24
23

22
21
20
19
18

VCC
A15
CE2
WE
A13
A8
A9
A11
OE

A10
CE1

I/O8
I/O7
I/O6
I/O5
I/O4GND

16

17

Pin No.

1 2A93 4 5 6 7 8 9 10 11 12 13 14

Pin
Name

Pin No.

Pin
Name

A8 A13 CE2 A15 VCC NC

A11 WE

A3 A2 A1 A0 I/O1 I/O2 GND I/O4 I/O5 I/O6 I/O7

(LP621024DX)

LP621024DV

I/O3

1

32

A16 A14 A12 A7 A6

I/O8

15 16

A5 A4

302928272625242219 2120 231817

31 32

CE1

A10 OE

(August, 2001, Version 1.0) 1 AMIC Technology, Inc.

LP621024D Series

Block Diagram

A0

A14

A15

A16

I/O1

I/O8

CE2
CE1

OE

WE

Pin Descriptions - DIP/SOP

CONTROL

CIRCUIT

ROW

DECODER

INPUT DATA

CIRCUIT

VCC
GND

512 X 2048

MEMORY ARRAY

COLUMN I/O

Pin Description - TSOP/TSSOP

Pin No. Symbol Description

1 NC No Connection

2 - 12, 23,

25 - 28, 31

13 - 15,

17 - 21

A0 - A16 Address Inputs

I/O1 - I/O8 Data Input/Outputs

16 GND Ground

22

24

29

CE1

OE

WE

Chip Enable

Output Enable

Write Enable

30 CE2 Chip Enable

32 VCC Power Supply (+5V)

Pin No. Symbol Description

1 - 4, 7,

10 - 20, 31

5

A0 - A16 Address Inputs

WE

Write Enable

6 CE2 Chip Enable

8 VCC Power Supply

9 NC No Connection

21 - 23,

25 - 29

I/O1 - I/O8 Data Input/Outputs

24 GND Ground

30

32

CE1

OE

Chip Enable

Output Enable

(August, 2001, Version 1.0) 2 AMIC Technology, Inc.

LP621024D Series

Recommended DC Operating Conditions

(TA = 0°C to + 70°C)

Symbol Parameter Min. Typ. Max. Unit

Supply Voltage

GND Ground 0 0 0 V

VIH Input High Voltage 2.2 3.5 VCC + 0.3 V
VIL Input Low Voltage -0.3 0 +0.8 V

CL Output Load - - 30 pF

TTL Output Load - - 1 -

4.5

5.0 5.5 V

Absolute Maximum Ratings*

VCC to GND ............................................. -0.5V to + 7.0V

IN, IN/OUT Volt to GND................... -0.5V to VCC + 0.5V

Operating Temperature, Topr.....................0°C to + 70°C

Storage Temperature, Tstg.................... -55°C to + 125°C

Temperature Under Bias, Tbias............... -10°C to + 85°C

Power Dissipation, PT ...............................................0.7W

Soldering Temp. & Time.............................260°C, 10 sec

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics (TA = 0°C to + 70°C, VCC = 5V ± 10%, GND = 0V)

Symbol Parameter

LP621024D-55LL LP621024D-70LL

Unit Conditions

Min. Max. Min. Max.

ILI

ILO

ICC

ICC1

ICC2

(August, 2001, Version 1.0) 3 AMIC Technology, Inc.

Input Leakage
Current

Output Leakage
Current

Active Power
Supply Current

Dynamic
Operating

Current

- 1 - 1

- 1 - 1

- 15 - 15 mA

- 70 - 70 mA

- 15 - 15 mA

µA

µA

VIN = GND to VCC

CE1 = VIH or CE2 = VIL

or OE = VIH or WE = VIL

VI/O = GND to VCC

CE1 = VIL, CE2 = VIH

II/O = 0mA

Min. Cycle, Duty = 100%

CE1 = VIL, CE2 = VIH

II/O = 0mA

CE1 = VIL, CE2 = VIH
VIH = VCC, VIL = 0V
f = 1MHZ, II/O = 0mA

LP621024D Series

CE1

OE WE

DC Electrical Characteristics (continued)

Symbol Parameter

Min. Max. Min. Max.

ISB - 2 - 2 mA

ISB1 Standby Power

Supply Current

ISB2 - 25 - 25

VOL

VOH

Output Low
Voltage

Output High
Voltage

LP621024D-55LL LP621024D-70LL

- 25 - 25

- 0.4 - 0.4 V IOL = 2.1mA

2.4 - 2.4 - V IOH = -1.0mA

Unit Conditions

µA

µA

Truth Table

Mode

Standby

H X X X High Z ISB, ISB1

CE2

I/O Operation Supply Current

CE1 = VIH or CE2 =VIL

CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
VIN ≥ 0V

CE2 ≤ 0.2V
VIN ≥ 0V

X L X X High Z ISB, ISB2

Output Disable L H H H High Z ICC, ICC1, ICC2

Read L H L H DOUT ICC, ICC1, ICC2

Write L H X L DIN ICC, ICC1, ICC2

Note: X = H or L

Capacitance (TA = 25°C, f = 1.0MHz)

Symbol Parameter Min. Max. Unit Conditions

CIN* Input Capacitance 6 pF VIN = 0V

CI/O* Input/Output Capacitance 8 pF VI/O = 0V

These parameters are sampled and not 100% tested.

(August, 2001, Version 1.0) 4 AMIC Technology, Inc.

LP621024D Series

AC Characteristics (TA = 0°C to + 70°C, VCC = 5V ± 10%)

Symbol Parameter

Read Cycle

tRC Read Cycle Time 55 - 70 - ns
tAA Address Access Time - 55 - 70 ns

tACE1

tACE2 CE2 - 55 - 70 ns

tOE Output Enable to Output Valid - 30 - 35 ns

tCLZ1

tCLZ2

tOLZ Output Enable to Output in Low Z 5 - 5 - ns

tCHZ1

tCHZ2 CE2 0 20 0 25 ns

tOHZ Output Disable to Output in High Z 0 20 0 25 ns

Chip Enable Access Time

Chip Enable to Output in Low Z

Chip Disable to Output in High Z

CE1

CE1
CE2 10 - 10 - ns

CE1

LP621024D-55LL LP621024D-70LL

Min. Max. Min. Max.

- 55 - 70 ns

10 - 10 - ns

0 20 0 25 ns

Unit

tOH Output Hold from Address Change 5 - 5 - ns

Write Cycle

tWC Write Cycle Time 55 - 70 - ns
tCW Chip Enable to End of Write 50 - 60 - ns
tAS Address Setup Time 0 - 0 - ns
tAW Address Valid to End of Write 50 - 60 - ns
tWP Write Pulse Width 40 - 50 - ns
tWR Write Recovery Time 0 - 0 - ns

tWHZ Write to Output in High Z 0 25 0 30 ns

tDW Data to Write Time Overlap 25 - 30 - ns
tDH Data Hold from Write Time 0 - 0 - ns

tOW Output Active from End of Write 5 - 5 - ns

Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.

(August, 2001, Version 1.0) 5 AMIC Technology, Inc.

LP621024D Series

Timing Waveforms

Read Cycle 1

Address

DOUT

(1, 2, 4)

tRC

tAA

tOH

tOH

Read Cycle 2

CE1

DOUT

Read Cycle 3

CE2

(1, 3, 4, 6)

(1, 4, 7, 8)

tACE1

5

tCLZ1

tCHZ1

5

tACE2

5

tCLZ2

5

tCHZ2

DOUT

(August, 2001, Version 1.0) 6 AMIC Technology, Inc.

LP621024D Series

Timing Waveforms (continued)

Read Cycle 4

(1)

tRC

Address

tAA

OE

CE1

CE2

DOUT

tCLZ1

tCLZ2

tOE

5

tOLZ

tACE1

5

tACE2

5

tCHZ2

tOH

tCHZ1

5

5

tOHZ

5

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled CE1 = VIL and CE2 = VIH.

3. Address valid prior to or coincident with CE1 transition low.

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

6. CE2 is high.

7. CE1 is low.

8. Address valid prior to or coincident with CE2 transition high.

(August, 2001, Version 1.0) 7 AMIC Technology, Inc.

LP621024D Series

Timing Waveforms (continued)

Write Cycle 1
(Write Enable Controlled)

Address

(6)

tWC

CE1

CE2

WE

DOUT

DIN

tAW

5

tCW

(4)

(4)

1

tAS

tWHZ

tWP

2

tDW

tWR

tDH

3

tOW

(August, 2001, Version 1.0) 8 AMIC Technology, Inc.

LP621024D Series

Timing Waveforms (continued)

Write Cycle 2
(Chip Enable Controlled)

tWC

Address

3

CE1

tAW tWR

5

tCW

(4)

1

tAS

CE2

WE

DIN

DOUT

(4)

5

tCW

2

tWP

tWHZ

tDW

7

tDH

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .

3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.

4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.

5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.

6. OE is continuously low. ( OE = VIL)

7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

(August, 2001, Version 1.0) 9 AMIC Technology, Inc.

LP621024D Series

AC Test Conditions

Input Pulse Levels 0V to 3.0V

Input Rise and Fall Time 5 ns

Input and Output Timing Reference Levels 1.5V

Output Load See Figures 1 and 2

+5V

I/O

* Including scope and jig.

1800

990

Ω

I/O

Ω

30pF*

+5V

1800

Ω

990

Ω

* Including scope and jig.

5pF*

Figure 1. Output Load Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW

Data Retention Characteristics (TA = 0°C to 70°C)

Symbol Parameter Min. Max. Unit Conditions

VDR1 2.0 5.5 V

VDR2 VCC for Data Retention 2.0 5.5 V

I

CCDR1

LL-Version

-

10**

Data Retention Current

µA

CE1 ≥ VCC - 0.2V

CE2 ≤ 0.2V

CE1 ≥ VCC - 0.2V or
CE1 ≤ 0.2V

VCC = 2.0V,

CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
VIN ≥ 0V

I

CCDR2

LL-Version

-

10**

µA

VCC = 2.0V
CE2 ≤ 0.2V
V

IN ≥ 0V

tCDR Chip Disable to Data Retention Time 0 - ns See Retention Waveform

tR Operation Recovery Time 5 - ms

** LP621024D-55LL/70LL ICCDR: Max. 2µA at TA = 0°C to + 40 °C

(August, 2001, Version 1.0) 10 AMIC Technology, Inc.

LP621024D Series

CE1

Low VCC Data Retention Waveform (1) (

Controlled)

DATA RETENTION MODE

VCC

CE1

4.5V

tCDR

VIH

VDR ≥ 2V

CE1 ≥ VDR - 0.2V

Low VCC Data Retention Waveform (2) (CE2 Controlled)

DATA RETENTION MODE

VCC

CE2

4.5V

tCDR

VIL

VDR ≥ 2V

CE2 < 0.2V

4.5V
tR

VIH

4.5V
tR

VIL

(August, 2001, Version 1.0) 11 AMIC Technology, Inc.

LP621024D Series

Ordering Information

Part No. Access Time (ns)

LP621024D-55LL 70 25 32L DIP

LP621024DM-55LL

LP621024DV-55LL 70 25 32L TSOP

LP621024DX-55LL 70 25 32L TSSOP

LP621024D-70LL 70 25 32L DIP

LP621024DM-70LL

LP621024DV-70LL 70 25 32L TSOP

LP621024DX-70LL 70 25 32L TSSOP

55

70

Operating Current

Max. (mA)

70 25 32L SOP

70 25 32L SOP

Standby Current

Max. (µµA)

Package

(August, 2001, Version 1.0) 12 AMIC Technology, Inc.

LP621024D Series

Package Information
P-DIP 32L Outline Dimensions unit: inches/mm

D

32

E1

17

1

S

AL

A2

B

e1

B1

16

A1

Base Plane

Seating Plane

α

E

C

eA

Symbol Dimensions in inches Dimensions in mm

A 0.210 Max. 5.33 Max.
A1 0.010 Min. 0.25 Min.
A2 0.155±0.010 3.94±0.25

B 0.018 +0.004 0.46 +0.10

B1 0.050 +0.004 1.27 +0.10

C 0.010 +0.004 0.25 +0.11

D 1.650 Typ. (1.670 Max.) 41.91 Typ. (42.42 Max.)

E 0.600±0.010 15.24±0.25
E1 0.550 Typ. (0.562 Max.) 13.97 Typ. (14.27 Max.)

e1 0.100±0.010 2.54±0.25

L 0.130±0.010 3.30±0.25

α 0° ~ 15° 0° ~ 15°

eA 0.655±0.035 16.64±0.89

S 0.090 Max. 2.29 Max.

-0.002

-0.002

-0.05

-0.05

-0.002 -0.05

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E1 does not include resin fins.

3. Dimension S includes end flash.

(August, 2001, Version 1.0) 13 AMIC Technology, Inc.

LP621024D Series

Package Information

SOP (W.B.) 32L Outline Dimensions unit: inches/mm

1

s

Seating Plane

1732

E

HE

16

b

D

A

y

e

D

A1 A2

See Detail F

Detail F

e1

L

e1

~

~

c

LE

Symbol Dimensions in inches Dimensions in mm

A 0.118 Max. 3.00 Max.
A1 0.004 Min. 0.10 Min.
A2 0.106±0.005 2.69±0.13

b 0.016 +0.004 0.41 +0.10

-0.002

-0.05

c 0.008 +0.004 0.20 +0.10

-0.002 -0.05
D 0.805 Typ. (0.820 Max.) 20.45 Typ. (20.83 Max.)
E 0.445±0.010 11.30±0.25
e 0.050 ±0.006 1.27±0.15

e1 0.525 NOM. 13.34 NOM.

HE 0.556±0.010 14.12±0.25

L 0.031±0.008 0.79±0.20

LE 0.055±0.008 1.40±0.20

S 0.044 Max. 1.12 Max.
y 0.004 Max. 0.10 Max.
θ 0° ~ 10° 0° ~ 10°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.

4. Dimension S includes end flash.

(August, 2001, Version 1.0) 14 AMIC Technology, Inc.

LP621024D Series

Package Information

TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm

D

e

0.25

BSC

Detail "A"

°12.0

b

A

θ

L

LE

0.10(0.004) M

A2

E

HD

Detail "A"

y

D

c

GAUGE PLANE

A1

S

Symbol Dimensions in inches Dimensions in mm

A 0.047 Max. 1.20 Max.

A1 0.004±0.002 0.10±0.05
A2 0.039±0.002 1.00±0.05

b 0.008±0.001 0.20±0.03
c 0.006±0.001 0.15±0.02
D 0.724±0.004 18.40±0.10
E 0.315±0.004 8.00±0.10
e 0.020 TYP. 0.50 TYP.

HD 0.787±0.007 20.00±0.20

L 0.020±0.004 0.50±0.10

LE 0.031 TYP. 0.80 TYP.

S 0.0167 TYP. 0.425 TYP.
Y 0.004 Max. 0.10 Max.
θ 0° ~ 6° 0° ~ 6°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.

4. Dimension S includes end flash.

(August, 2001, Version 1.0) 15 AMIC Technology, Inc.

LP621024D Series

Package Information

TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm

e

0.25

BSC

Detail "A"

Detail "A"

°12.0

A

θ

L

LE

b

0.10MM

D

SEATING PLANE

A2

E

D1

D

Detail "A"

c

GAUGE PLANE

A1

S

Symbol Dimensions in inches Dimensions in mm

A 0.049 Max. 1.25 Max.

A1 0.002 Min. 0.05 Min.
A2 0.039±0.002 1.00±0.05

b 0.008±0.001 0.20±0.03
c 0.006±0.0003 0.15±0.008
E 0.315±0.004 8.00±0.10
e 0.020 TYP. 0.50 TYP.
D 0.528±0.008 13.40±0.20

D1 0.465±0.004 11.80±0.10

L 0.02±0.008 0.50±0.20

LE 0.0266 Min. 0.675 Min.

S 0.0109 TYP. 0.278 TYP.
y 0.004 Max. 0.10 Max.
θ 0° ~ 6° 0° ~ 6°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.

4. Dimension S includes end flash.

(August, 2001, Version 1.0) 16 AMIC Technology, Inc.