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LP61L256C
Preliminary 32K X 8 BIT HIGH SPEED CMOS SRAM
Document Title
32K X 8 BIT HIGH SPEED CMOS SRAM
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue November 9, 2001 Preliminary
PRELIMINARY (November, 2001, Version 0.0) AMIC Technology, Inc.
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LP61L256C
Preliminary 32K X 8 BIT HIGH SPEED CMOS SRAM
Features
n Single +3.3V power supply
n Access times: 12/15 ns (max.)
n Current: Operating: 120mA (max.)
Standby: 5mA (max.)
n Full static operation, no clock or refreshing required
General Description
The LP61L256C is a high-speed, low-power 262,144-bit
static random access memory organized as 32,768
words by 8 bits and operates on a single 3.3V power
supply. It is built using high performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
n SOJ
n All inputs and outputs are directly TTL compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 28-pin SOJ package
Minimum standby power is drawn by this device when
CE is at a high level, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 2V.
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
LP61L256C
5
6
7
8
9
10
11
12
13
14 15
VCC
28
WE
27
A13
26
A8
25
A9
24
A11
23
OE
22
A10
21
CE
20
I/O7
19
I/O6
18
I/O5
17
I/O4
16
I/O3
PRELIMINARY (November, 2001, Version 0.0) 1 AMIC Technology, Inc.
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LP61L256C Series
Block Diagram
A10
A11
A12
I/O
I/O
CE
OE
WE
A0
A5
A6
A7
A9
0
7
CONTROL
CIRCUIT
ROW
DECODER
INPUT DATA
CIRCUIT
256 X 1024
MEMORY ARRAY
COLUMN I/O
COLUMN DECODER
A2
A3
A1 A14
A13
A8A4
VCC
GND
Pin Descriptions - SOJ
Pin No. Symbol Description
1 - 10, 21, 23 - 26 A0 - A14 Address Inputs
11 - 13, 15 - 19 I/O0 - I/O7 Data Inputs/Outputs
14 GND Ground
28 VCC Power Supply
20
22
27
CE
OE
WE
Chip Enable
Output Enable
Write Enable
PRELIMINARY (November, 2001, Version 0.0) 2 AMIC Technology, Inc.
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LP61L256C Series
Recommended DC Operating Conditions
(TA = 0°C to + 70°C)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 3.0 3.3 3.6 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.2 - VCC + 0.3 V
VIL Input Low (1) Voltage -0.5 0 +0.8 V
CL Output Load - - 30 pF
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C
Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C
Temperature Under Bias, Tbias . . . . . . . . -10°C to +85°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 1.0W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C, VCC = 3.3V ± 10%, GND = 0V)
Symbol Parameter
Min. Max.
ILI
ILO
ICC1 (2) Dynamic Operating Current - 120 mA
ISB - 30 mA
ISB1
VOL Output Low Voltage - 0.4 V IOL = 8 mA
VOH Output High Voltage 2.4 - V IOH = -4 mA
Notes: 1. VIL = -3.0V for pulses less than 20 ns.
2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
Input Leakage - 2
Output Leakage - 2
Standby Power
Supply Current
LP61L256C-12/15
-
5
Unit Conditions
µA
µA
mA
VIN = GND to VCC
CE = VIH or OE = VIH
VI/O = GND to VCC
CE = VIL, II/O = 0 mA
Min. Cycle, Duty = 100%
CE = VIH
CE ≥ VCC - 0.2V
VIN ≥ VCC -0.2V or
VIN ≤ 0.2V
PRELIMINARY (November, 2001, Version 0.0) 3 AMIC Technology, Inc.
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LP61L256C Series
CE OE WE
Truth Table
Mode
Standby H X X High Z ISB, ISB1
Output Disable L H H High Z ICC1
Read L L H DOUT ICC1
Write L X L DIN ICC1
Note: X = H or L
I/O Operation Supply Current
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance 10 pF VIN = 0V
CI/O* Input/Output Capacitance 10 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%)
Symbol Parameter
Min. Max. Min. Max.
Read Cycle
LP61L256C-12 LP61L256C-15
Unit
tRC Read Cycle Time 12 - 15 - ns
tAA Address Access Time - 12 - 15 ns
tACE Chip Enable Access Time - 12 - 15 ns
tOE Output Enable to Output Valid - 6 - 8 ns
tCLZ Chip Enable to Output in Low Z 3 - 3 - ns
tOLZ Output Enable to Output in Low Z 0 - 0 - ns
tCHZ Chip Disable Output in High Z 0 6 - 8 ns
tOHZ Output Disable to Output in High Z 0 6 0 8 ns
tOH Output Hold from Address Change 3 - 3 - ns
PRELIMINARY (November, 2001, Version 0.0) 4 AMIC Technology, Inc.
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LP61L256C Series
AC Characteristics (continued)
Symbol Parameter
LP61L256C-12 LP61L256C-15
Unit
Min. Max. Min. Max
Write Cycle
tWC Write Cycle Time 12 - 15 - ns
tCW Chip Enable to End of Write 10 - 12 - ns
tAS Address Setup Time of Write 0 - 0 - ns
tAW Address Valid to End of Write 10 - 12 - ns
tWP Write Pulse Width 10 - 12 - ns
tWR Write Recovery Time 0 - 0 - ns
tWHZ Write to Output in High Z 0 6 0 8 ns
tDW Data to Write Time Overlap 6 - 7 - ns
tDH Data Hold from Write Time 0 - 0 - ns
tOW Output Active from End of Write 3 - 3 - ns
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levles.
Timing Waveforms
Read Cycle 1
(1)
tRC
Address
tAA
OE
CE
DOUT
tCLZ
tOE
5
tOLZ
tACE
5
tOH
tCHZ
tOHZ
5
5
PRELIMINARY (November, 2001, Version 0.0) 5 AMIC Technology, Inc.
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LP61L256C Series
Timing Waveforms (continued)
Read Cycle 2
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
Read Cycle 3
(1, 3, 4,)
CE
tACE
5
tCLZ
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
tCHZ
5
PRELIMINARY (November, 2001, Version 0.0) 6 AMIC Technology, Inc.
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LP61L256C Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
Address
(6)
tWC
CE
WE
DIN
DOUT
Write Cycle 2
(Chip Enable Controlled)
Address
CE
tAW
5
tCW
(4)
1
tAS
7
tWHZ
tWP
2
tDW
tWR
3
tDH
7
tOW
tWC
1
tAS
(4)
tAW
tCW
5
tWR
3
2
tWP
WE
DIN
DOUT
tWHZ
tDW
7
tDH
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE .
3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (November, 2001, Version 0.0) 7 AMIC Technology, Inc.
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LP61L256C Series
AC Test Conditions
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Time 2 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
+3.3V
317
Ω
OUTPUT
ZO=50
RL=50
Ω
VT=1.5V
Ω
I/O
* Including scope and jig.
351
Ω
5pF*
Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol Parameter Min. Max. Unit Conditions
VDR VCC for Data Retention 2 3.6 V
ICCDR Data Retention Current
tCDR
Chip Disable to Data Retention
Time
-
2
0 - ns
mA
CE ≥ VCC - 0.2V
VCC = 2.0V
CE ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
See Retention Waveform
tR Operation Recovery Time tRC* - ns
tRC = Read Cycle Time
PRELIMINARY (November, 2001, Version 0.0) 8 AMIC Technology, Inc.
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LP61L256C Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
CE
3.0V
tCDR
VIH
VDR
≥
2.0V
CE ≥ VDR - 0.2V
3.0V
tR
VIH
Ordering Information
Part No. Access Time (ns)
Operating Current
Max. (mA)
LP61L256CS-12 12 120 5 28L SOJ
LP61L256CS-15 15 120 5 28L SOJ
Standby Current
Max. (mA)
Package
PRELIMINARY (November, 2001, Version 0.0) 9 AMIC Technology, Inc.
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LP61L256C Series
Package Information
SOJ 28L Outline Dimensions unit: inches/mm
1528
E
HE
1
S
Seating Plane
D
b
b1
14
A2
A
e
A1
y
D
L
e1
C
Symbol
A - - 0.140 - - 3.56
A1 0.027 - - 0.69 - A2 0.095 0.100 0.105 2.41 2.54 2.67
b1
b 0.018 TYP 0.46 TYP
C 0.010 TYP 0.25 TYP
D - 0.710 0.730 - 18.03 18.54
E 0.295 0.300 0.305 7.49 7.62 7.75
e 0.050 BSC 1.27 BSC
e1
HE
L 0.077 0.087 0.097 1.96 2.21 2.46
S - - 0.045 - - 1.14
y - - 0.004 - - 0.10
Dimensions in inches Dimensions in mm
Min Nom Max Min Nom Max
0.028 TYP 0.71 TYP
0.255 0.265 0.275 6.48 6.73 6.99
0.329 0.337 0.345 8.36 8.56 8.76
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY (November, 2001, Version 0.0) 10 AMIC Technology, Inc.
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