Page 1
LP61L256B Series
32K X 8 Bit High SPEED LOW VCC CMOS SRAM
Features
n Single +3.3 volt power supply
n Access times: 12 ns (max.)
n Current: Operating: 100mA (max.)
Standby: 10mA (max.)
n Full static operation, no clock or refreshing required
General Description
The LP61L256B is a high-speed, low-power 262,144-bit
static random access memory organized as 32,768 words
by 8 bits that operates on a single 3.3V power supply.
Input and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
n All inputs and outputs directly TTL compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 28-pin SOJ and TSOP packages
Minimum standby power is drawn by this device when CE
is at a high level, independent of the other input levels.
Data retention is guaranteed at a power supply voltage as
low as 2V.
Pin Configurations
nn SOJ nn TSOP
A14
A12
I/O1
I/O2
I/O3
GND
1
2
A7
3
4
A6
A5
5
6
A4
A3
7
A2
8
A1
9
10
A0
11
12
13
14
28
VCC
27
WE
A13
26
A8
25
A9
24
LP61L256B
A11
23
22
OE
A10
21
CE
20
I/O8
19
I/O7
18
17
I/O6
16
I/O5
15
I/O4
1OE2
Pin No.
Pin
Name
Pin No.
Pin
Name
A11
A2 A1 A0 I/O1I/O2I/O
14
15
3 4 5 6 7 8 9 10 11 12 13 14
A9 A8 A13 WE VCC A14 A12
1
LP61L256BV
28
3
I/O4I/O5I/O6I/O7I/O8CEGND
A7 A6 A5 A4 A3
A10
282726252423222017 1918 211615
(August, 2001, Version 1.0) 1 AMIC Technology, Inc.
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LP61L256B Series
Block Diagram
Pin Descriptions -SOJ
A12
I/O1
I/O
WE
A0
A5
A7
A9
8
CE
OE
CONTROL
CIRCUIT
ROW
DECODER
INPUT DATA
CIRCUIT
256 X 1024
MEMORY ARRAY
COLUMN I/O
COLUMN DECODER
A1 A14
A13
A8A4
VCC
GND
Pin Description - TSOP
Pin No. Symbol Description
1 - 10, 21,
23 - 26
A0 - A14 Address Inputs
11 - 13, 15 - 19 I/O1 - I/O8 Data Inputs/Outputs
14 GND Ground
20
22
27
CE
OE
WE
28 VCC
Chip Enable
Output Enable
Write Enable
Power Supply
(+3.3V)
Pin No. Symbol Description
1
OE
Output Enable
2 - 5, 8 - 17, 28 A0 - A14 Address Inputs
6
WE
Write Enable
7 VCC Power Supply
18 - 20, 22 - 26 I/O1 - I/O8 Data Inputs/Outputs
21 GND Ground
27
CE
Chip Enable
(August, 2001, Version 1.0) 2 AMIC Technology, Inc.
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LP61L256B Series
Recommended DC Operating Conditions
(TA = 0°C to + 70°C)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 3.0 3.3 3.6 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.2 - VCC + 0.3 V
VIL Input Low Voltage -0.3 0 0.8 V
CL Output Load - - 30 pF
TTL Output Load - - 1 -
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . . . -0.3V to VCC +0.3V
Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C
Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C
Power Dissipation, Pt . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics (TA = 0°C to 70°C, VCC = 3.3V ± 10%, GND = 0V)
LP61L256B-12
Symbol Parameter
Min. Max.
ILI
ILO
ICC1 (1) Dynamic Operating Current - 100 mA
ISB
ISB1
VOL Output Low Voltage - 0.4 V IOL = 8 mA
VOH Output High Voltage 2.4 - V IOH = -4 mA
Notes: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
Input Leakage Current - 2
Output Leakage Current - 2
Standby Power
Supply Current
- 20 mA
-
10
Unit Conditions
µA
µA
mA
VIN = GND to VCC
CE = VIH or OE = VIH
VI/O = GND to VCC
CE = VIL, II/O = 0 mA
CE = VIH
CE ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
(August, 2001, Version 1.0) 3 AMIC Technology, Inc.
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LP61L256B Series
CE OE WE
Truth Table
Mode
Standby H X X High Z ISB, ISB1
Output Disable L H H High Z ICC1
Read L L H DOUT ICC1
Write L X L DIN ICC1
I/O Operation Supply Current
Capacitance (TA = 25°C, f = 1.0 MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance - 10 pF VIN = 0 V
CI/O* Input/Output Capacitance - 10 pF VI/O = 0 V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0°C to + 70°C, VCC = 3.3V ± 10%)
Symbol Parameter
LP61L256B-12
Min. Max.
Unit
Read Cycle
tRC Read Cycle Time 12 - ns
tAA Address Access Time - 12 ns
tACE Chip Enable Access Time - 12 ns
tOE Output Enable to Output Valid - 7 ns
tCLZ Chip Enable to Output in Low Z 2 - ns
tOLZ Output Enable to Output in Low Z 2 - ns
tCHZ Chip Disable to Output in High Z 0 7 ns
tOHZ Output Disable to Output in High Z 2 6 ns
tOH Output Hold from Address Change 2 - ns
(August, 2001, Version 1.0) 4 AMIC Technology, Inc.
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LP61L256B Series
AC Characteristics (continued)
Symbol Parameter
LP61L256B-12
Min. Max.
Write Cycle
tWC Write Cycle Time 12 - ns
tCW Chip Enable to End of Write 10 - ns
tAS Address Setup Time of Write 0 - ns
tAW Address Valid to End of Write 10 - ns
tWP Write Pulse Width 8 - ns
tWR Write Recovery Time 0 - ns
tWHZ Write to Output in High Z 0 7 ns
tDW Data to Write Time Overlap 8 - ns
tDH Data Hold from Write Time 0 - ns
tOW Output Active from End of Write 5 - ns
Unit
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
(August, 2001, Version 1.0) 5 AMIC Technology, Inc.
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LP61L256B Series
Timing Waveforms (continued)
Read Cycle 2
CE
DOUT
(1, 3, 4)
tACE
5
tCLZ
tCHZ
5
Read Cycle 3
(1)
tRC
Address
tAA
OE
tOH
5
tOHZ
5
tCHZ
CE
DOUT
tCLZ
tOE
5
tOLZ
tACE
5
Note: 1. WE is high for Read cycle.
2. Device is continuously enabled, CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
(August, 2001, Version 1.0) 6 AMIC Technology, Inc.
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LP61L256B Series
Timing Waveforms (continued)
Write Cycle
(Write Enable Controlled)
Address
(6)
tWC
CE
WE
DIN
DOUT
Write Cycle 2
(Chip Enable Controlled)
Address
CE
tAW
5
tCW
(4)
1
tAS
7
tWHZ
tWP
2
tDW
tWR
3
tDH
7
tOW
tWC
1
tAS
(4)
tAW
tCW
5
tWR
3
2
tWP
WE
DOUT
DIN
tWHZ
tDW
7
tDH
Notes: 1. tAS is measured from address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE.
3. tWR is measured from CE or WE going high to the end of the Write cycle.
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. tCW is measured from CE going low to the end of Write.
6. OE is continuously low (OE = VIL).
7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
(August, 2001, Version 1.0) 7 AMIC Technology, Inc.
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LP61L256B Series
AC Test Conditions
Input Pulse Levels 0V - 3V
Input Rise and Fall Times 3 ns
Input and Current Timing Reference Levels 1.5V
Output Load See Figures 1, 2 and 3
+3.3V
I/O
* Including scope and jig.
320Ω
350Ω
I/O
30pF*
+3.3V
320Ω
350Ω
* Including scope and jig.
5pF*
OUTPUT
ZO=50Ω
RL=50Ω
VT=1.5V
Figure 1. Output Load Figure 2. Output Load for tCLZ, Figure 3. Output Load
tOLZ, tCHZ, tOHZ, tWHZ,
and tOW
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol Parameter Min. Max. Unit Conditions
VDR VCC for Data Retention 2.0 3.6 V
ICCDR Data Retention Current
-
0.5
mA
CE ≥ VCC - 0.2V
VCC = 2V, CE ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
tCDR Chip Disable to Data Retention Time 0 - ns
See Retention Waveform
tR Operation Recovery Time 5 - ms
(August, 2001, Version 1.0) 8 AMIC Technology, Inc.
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LP61L256B Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
CE
3.3V
tCDR
VIH
VDR ≥ 2V
CE ≥ VDR - 0.2V
3.3V
tR
VIH
Ordering Information
Part No. Access Time (ns)
Operating Current
Max. (mA)
LP61L256BS-12 12 100 10 28L SOJ
LP61L256BV-12 12 100 10 28L TSOP
Standby Current
Max. (mA)
Package
(August, 2001, Version 1.0) 9 AMIC Technology, Inc.
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LP61L256B Series
Package Information
SOJ 28L Outline Dimensions unit: inches/mm
1528
E
HE
1
S
Seating Plane
D
b
b1
14
A2
A
e
A1
y
D
L
e1
C
Symbol Dimensions in inches Dimensions in mm
A 0.140 Max. 3.56 Max.
A1 0.027 Min. 0.69 Min.
A2 0.100±0.005 2.54±0.13
b
1
b 0.018 Typ. 0.46 Typ.
C 0.010 Typ. 0.25 Typ.
D 0.710 Typ. (0.730 Max.) 18.03 Typ. (18.54 Max.)
E 0.300±0.005 7.62±0.13
e 0.050 Typ. 1.27 Typ.
e1
HE
L 0.087±0.10 2.21±0.25
S 0.045 Max. 1.14 Max.
y 0.004 Max. 0.10 Max.
0.028 Typ.
0.71 Typ.
0.265±0.010 6.73±0.25
0.337±0.008 8.56±0.20
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
(August, 2001, Version 1.0) 10 AMIC Technology, Inc.
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LP61L256B Series
Package Information
TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm
D
E
HD
y
D
RD
e
Detail "A"
0.25
BSC
Detail "A"
b
°12.0
A
θ
L
LE
A2
c
GAUGE PLANE
A1
S
Symbol Dimensions in inches Dimensions in mm
A 0.049 Max. 1.25 Max.
A1 0.002 Min. 0.05 Min.
A2 0.039±0.002 1.00±0.05
b 0.0079±0.0012 0.20±0.03
c 0.006±0.0003 0.15±0.008
D 0.465±0.004 11.80±0.10
E 0.315±0.004 8.00±0.10
e 0.0217 TYP. 0.55 TYP.
HD 0.528±0.008 13.40±0.20
L 0.02±0.008 0.50±0.20
LE 0.0266 TYP. 0.675 TYP.
S 0.0167 TYP. 0.425 TYP.
y 0.004 Max. 0.10 Max.
θ 0° ~ 6° 0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
(August, 2001, Version 1.0) 11 AMIC Technology, Inc.
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