Page 1
LP61L1008A
Preliminary 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Features
n Single 3.3V ± 10% power supply
n Access times: 8/10/12 ns (max.)
n Current: Operating: 160/155/150mA (max.)
Standby: 5mA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL compatible
General Description
The LP61L1008A is a high speed 1,048,576-bit static
random access memory organized as 131,072 words by
8 bits and operates on a single 3.3V power supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configuration
n Center Power/Ground Pin Configuration
n Common I/O using three-state output
n Output enable and one chip enable inputs for easy
application
n Data retention voltage: 2.0V (min.)
n Available in 32-pin SOJ 300 mil package
The chip enable input is provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
A0
A1
A2
A3
CE
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A4
A5
A6
1
2
3
4
5
LP61L1008AS
6
7
8
9
10
11
12
13
14
15
16 17
A16
32
A15
31
A14
30
A13
29
OE
28
I/O8
27
I/O7
26
GND
25
VCC
24
I/O6
23
I/O5
22
A12
21
A11
20
A10
19
A9
18
A8A7
PRELIMINARY (August, 2001, Version 1.0) 1 AMIC Technology, Inc.
Page 2
LP61L1008A
Block Diagram
VCC
GND
A14
A15
A16
I/O
I/O8
A0
512 X 2048
DECODER
1
INPUT
DATA
CIRCUIT
MEMORY ARRAY
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Pin Description
Pin No. Symbol Description
1 - 4, 13 - 21,
29- 32
12
28
5
6 –7, 10 - 11,
22 – 23, 26 - 27
8, 24 VCC Power Supply
9, 25 GND Ground
A0 - A16 Address Inputs
WE
OE
CE
Write Enable
Output Enable
Chip Enable
I/O1 - I/O8 Data Input/Outputs
PRELIMINARY (August, 2001, Version 1.0) 2 AMIC Technology, Inc.
Page 3
LP61L1008A
Recommended DC Operating Conditions
(TA = 0°C to + 70°C)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 3.0 3.3 3.6 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.2 - VCC + 0.3 V
VIL Input Low Voltage -0.3 0 +0.8 V
CL Output Load - - 30 pF
TTL Output Load - - 1 -
Absolute Maximum Ratings*
VCC to GND .............................................. -0.5V to +4.6V
IN, IN/OUT Volt to GND.....................-0.5V to VCC +0.5V
Operating Temperature, Topr...................... 0°C to +70°C
Storage Temperature, Tstg..................... -55°C to +125°C
Power Dissipation, Pt................................................1.0W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C, VCC = 3.3V ± 10%, GND = 0V)
Symbol Parameter
ILI
ILO
ICC1 (1)
ISB - 20 mA
Input Leakage Current - 2
Output Leakage Current - 2
Dynamic Operating
Current
-8 - 160
-10 - 155
-12 - 150
LP61L1008A- 8/10/12
Unit Conditions
Min. Max.
µA
µA
mA
VIN = GND to VCC
CE = VIH or
OE = VIH or WE = VIL
VI/O = GND to VCC
CE = VIL
II/O = 0 mA
CE = VIH
ISB1
VOL Output Low Voltage - 0.4 V IOL = 8 mA
VOH Output High Voltage 2.4 - V IOH = -4 mA
Note: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns
Standby Power
Supply Current
-
5
mA
CE ≥ VCC - 0.2V,
VIN ≤ 0.2V or VIN ≥ VCC - 0.2V
PRELIMINARY (August, 2001, Version 1.0) 3 AMIC Technology, Inc.
Page 4
LP61L1008A
CE
OE WE
Truth Table
Mode
Standby H X X High Z ISB, ISB1
Output Disable L H H High Z ICC1
Read L L H DOUT ICC1
Write L X L DIN ICC1
Note: X = H or L
I/O Operation Supply Current
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance 6 pF VIN = 0V
CI/O* Input/Output Capacitance 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%, GND = 0V)
Symbol Parameter
Min. Max. Min. Max. Min. Max.
LP61L1008A-8 LP61L1008A-10 LP61L1008A-12
Unit
Read Cycle
tRC Read Cycle Time 8 - 10 - 12 - ns
tAA Address Access Time - 8 - 10 - 12 ns
tACE Chip Enable Access Time
tOE Output Enable to Output Valid - 4 - 5 - 6 ns
tCLZ Chip Enable to Output in Low Z
tOLZ Output Enable to Output in Low Z 0 - 0 - 2 - ns
tCHZ Chip Disable to Output in High Z
tOHZ Output Disable to Output in High Z 0 4 0 5 2 6 ns
tOH Output Hold from Address Change 3 - 3 - 5 - ns
CE
CE
CE
- 8 - 10 - 12 ns
3
- 4 - 5 - 6 ns
-
3 - 5 - ns
PRELIMINARY (August, 2001, Version 1.0) 4 AMIC Technology, Inc.
Page 5
LP61L1008A
AC Characteristics (continued)
Symbol Parameter
LP61L1008A-8 LP61L1008A-10 LP61L1008A-12 Unit
Min. Max. Min. Max. Min. Max.
Write Cycle
tWC Write Cycle Time 8 - 10 - 12 - ns
tCW Chip Enable to End of Write 6 - 7 - 10 - ns
tAS Address Setup Time of Write 0 - 0 - 0 - ns
tAW Address Valid to End of Write 6 - 7 - 10 - ns
tWP Write Pulse Width 6 - 7 - 8 - ns
tWR Write Recovery Time 0 - 0 - 0 - ns
tWHZ Write to Output in High Z 0 4 0 5 0 5 ns
tDW Data to Write Time Overlap 4 - 5 - 8 - ns
tDH Data Hold from Write Time 0 - 0 - 0 - ns
tOW Output Active from End of Write 3 - 3 - 5 - ns
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
Timing Waveforms
Read Cycle 1
Address
DOUT
(1, 2, 4)
tRC
tAA
tOH
tOH
PRELIMINARY (August, 2001, Version 1.0) 5 AMIC Technology, Inc.
Page 6
LP61L1008A
Read Cycle 2
CE
DOUT
Read Cycle 3
Address
(1, 3, 4, 6)
(1)
tACE
5
tCLZ
tCHZ
5
tRC
tAA
OE
CE
DOUT
tACE
tOLZ
tOE
5
tCHZ
tOH
5
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VI.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (August, 2001, Version 1.0) 6 AMIC Technology, Inc.
Page 7
LP61L1008A
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
Address
(6)
tWC
CE
WE
DIN
DOUT
tAW
5
tCW
(4)
1
tAS
tWHZ
tWP
2
tDW
tWR
3
tDH
tOW
PRELIMINARY (August, 2001, Version 1.0) 7 AMIC Technology, Inc.
Page 8
LP61L1008A
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
3
CE
WE
tAW tWR
5
tCW
(4)
1
tAS
5
tCW
2
tWP
DIN
DOUT
tWHZ
tDW
7
tDH
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE.
3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle.
4. If the CE low transition with the WE low transition or after the WE transition, outputs remain in a high
impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (August, 2001, Version 1.0) 8 AMIC Technology, Inc.
Page 9
LP61L1008A
AC Test Conditions
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Time 3 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
+3.3V
320
Ω
Output
ZO=50
RL=50
Ω
VT=1.5V
Ω
I/O
350
Ω
* Including scope and jig.* Including scope and jig.
5pF*
Figure 1. Output Load Figure 2. Output Load for tCLZ,
tOHZ, tOLZ, tCHZ, tWHZ,
and tOW
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol Parameter Min. Max. Unit Conditions
VDR1
ICCDR1
tCDR Chip Disable to Data Retention Time 0 - ns
tR Operation Recovery Time 5 - ms
VCC for Data Retention
Data Retention Current
2
-
3.6
3
V
mA
CE ≥ VCC - 0.2V
VCC = 2V
CE ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
See Retention Waveform
PRELIMINARY (August, 2001, Version 1.0) 9 AMIC Technology, Inc.
Page 10
LP61L1008A
Low VCC Data Retention Waveform (CE Controlled)
DATA RETENTION MODE
VCC
CE
3.0V
tCDR
VIH
VDR ≥ 2V
CE ≥ VDR - 0.2V
3.0V
tR
VIH
Ordering Information
Part No. Access Time (ns)
Operating Current
Max. (mA)
LP61L1008AS-8 8 160 5 32L SOJ (300 mil)
LP61L1008AS-10 10 155 5 32L SOJ (300 mil)
LP61L1008AS-12 12 150 5 32L SOJ (300 mil)
Standby Current
Max. (mA)
Package
PRELIMINARY (August, 2001, Version 1.0) 10 AMIC Technology, Inc.
Page 11
LP61L1008A
Package Information
SOJ 32 (300mil BODY) Outline Dimensions unit: inches/mm
D
1732
DETAIL "A"
F
F
E
b
BASE METAL
WITH PLATING
SECTION F-F
c
1
s
SEATING PLANE
b1
b
16
DETAIL "A"
HE
A2
e
MIN
0.026"
0.004
D
y
A
A1
yy
e1
Symbol
A 0128 0.132 0.140 3.25 3.35 3.56
A1 0.052 - - 2.08 - A2 0.095 0.100 0.105 2.41 2.54 2.67
b 0.016 0.018 0.020 0.41 0.46 0.51
b1 0.026 0.028 0.032 0.66 0.71 0.81
c 0.006 0.008 0.012 0.15 0.20 0.30
D 0.820 0.825 0.830 20.83 20.96 21.08
HE 0.330 0.335 0.340 8.39 8.51 8.63
E 0.295 0.300 0.305 7.49 7.62 7.75
e1 0.260 0.267 0.274 6.61 6.78 6.96
e - 0.050 - - 1.27 -
s - - 0.048 - - 1.22
y - - 0.004 - - 0.10
Dimensions in inches Dimensions in mm
Min. Nom. Max. Min. Nom. Max.
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E doesn't include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY (August, 2001, Version 1.0) 11 AMIC Technology, Inc.
Loading...