Page 1
August 2004
LP3995
Micropower 150mA CMOS Voltage Regulator with Active
Shutdown
LP3995 Micropower 150mA CMOS Voltage Regulator with Active Shutdown
General Description
The LP3995 linear regulator is designed to meet the requirements of portable battery-powered applications and will provide an accurate output voltage with low noise and low
quiescent current. Ideally suited for powering RF/Analog
devices, this device will also be used to meet more general
circuit needs in which a fast turn-off is essential.
For battery powered applications the low dropout and low
ground current provided by the device allows the lifetime of
the battery to be maximized. The Enable(/Disable) control
allows the system to further extend the battery lifetime by
reducing the power consumption to virtually zero.
The Enable(/Disable) function on the device incorporates an
active discharge circuit on the output for faster device shutdown. Where the fast turn-off is not required the LP3999
linear regulator is recommended.
The LP3995 also features internal protection against shortcircuit currents and over-temperature conditions.
The LP3995 is designed to be stable with small 1.0 µF
ceramic capacitors. The small outline of the LP3995 micro
SMD package with the required ceramic capacitors can
realize a system application within minimal board area.
Performance is specified for a −40˚C to +125˚C temperature
range.
The device is available in micro SMD package and LLP
package. For other package options contact your local NSC
sales office.
The device is available in fixed output voltages in the ranges
1.5V to 3.3V. For availability, please contact your local NSC
sales office.
Key Specifications
n 2.5V to 6.0V Input Range
n Accurate Output Voltage;
n 60 mV Typical Dropout with 150 mA Load
n Virtually Zero Quiescent Current when Disabled
n Low Output Voltage Noise
n Stable witha1µFOutput Capacitor
n Guaranteed 150 mA Output Current
n Fast Turn-on; 30 µs (Typ.)
n Fast Turn-off; 175 µs (Typ.)
±
75mV / 2%
Features
n 5 pin micro SMD Package
n 6 pin LLP Package
n Stable with Ceramic Capacitor
n Logic Controlled Enable
n Fast Turn-on
n Active Disable for Fast Turn-off.
n Thermal-overload and Short-circuit Protection
n −40 to +125˚C Junction Temperature Range for
Operation
Applications
n GSM Portable Phones
n CDMA Cellular Handsets
n Wideband CDMA Cellular Handsets
n Bluetooth Devices
n Portable Information Appliances
Typical Application Circuit
20034901
© 2004 National Semiconductor Corporation DS200349 www.national.com
Page 2
Block Diagram
LP3995
Pin Description
5 pin micro SMD and LLP - 6
Pin No. Symbol Name and Function
micro
SMD
A1 3 V
B2 2 GND Common Ground
C1 6 V
C3 1 V
A3 4 C
LLP
EN
OUT
IN
BYPASS
5 N/C No internal connection. There should not be any board connection to this pin.
Pad GND Ground connection.
20034902
Enable Input; Disables the Regulator when ≤ 0.4V.
Enables the regulator when ≥ 0.9V
Voltage output. Connect this output to the load circuit.
Voltage Supply Input
Bypass Capacitor connection.
Connect a 0.01 µF capacitor for noise reduction.
Connect to ground plane for best thermal conduction.
Connection Diagrams
micro SMD, 5 Bump Package
Top View
See NS Package Number TLA05
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20034903
Page 3
Connection Diagrams (Continued)
LLP- 6 Package (SOT23 Footprint)
LP3995
Top View
See NS Package Number LDE06A
20034904
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Page 4
Ordering Information
LP3995
Output Voltage
(V)
1.5 STD LP3995ITL-1.5 LP3995ITLX-1.5
1.6 STD LP3995ITL-1.6 LP3995ITLX-1.6
1.8 STD LP3995ITL-1.8 LP3995ITLX-1.8
1.9 STD LP3995ITL-1.9 LP3995ITLX-1.9
2.1 STD LP3995ITL-2.1 LP3995ITLX-2.1
2.5 STD LP3995ITL-2.5 LP3995ITLX-2.5
2.8 STD LP3995ITL-2.8 LP3995ITLX-2.8
2.85 STD LP3995ITL-2.85 LP3995ITLX-2.85
3.0 STD LP3995ITL-3.0 LP3995ITLX-3.0
Output Voltage
(V)
1.5 (Note 2) STD LP3995ITL-1.5 LP3995ITLX-1.5
1.6 (Note 2) STD LP3995ITL-1.6 LP3995ITLX-1.6
1.8 (Note 2) STD LP3995ITL-1.8 LP3995ITLX-1.8
1.9 (Note 2) STD LP3995ITL-1.9 LP3995ITLX-1.9
2.1 (Note 2) STD LP3995ITL-2.1 LP3995ITLX-2.1
2.5 (Note 2) STD LP3995ITL-2.5 LP3995ITLX-2.5
2.8 (Note 2) STD LP3995ITL-2.8 LP3995ITLX-2.8
3.0 (Note 2) STD LP3995ITL-3.0 LP3995ITLX-3.0
For micro SMD Package
Grade LP3995 Supplied as 250
Units, Tape and Reel
For micro SMD Package unleaded
Grade LP3995 Supplied as 250
Units, Tape and Reel
LP3995 Supplied as
3000 Units, Tape and
Reel
LP3995 Supplied as
3000 Units, Tape and
Reel
Package
Marking
Package
Marking
For LLP- 6 Package
Output Voltage
(V)
1.5 STD LP3995ILD-1.5 LP3995ILDX-1.5 LO20B
1.6 STD LP3995ILD-1.6 LP3995ILDX-1.6 LO21B
1.8 STD LP3995ILD-1.8 LP3995ILDX-1.8 LO22B
1.9 (Note 2) STD LP3995ILD-1.9 LP3995ILDX-1.9 LO23B
2.1 (Note 2) STD LP3995ILD-2.1 LP3995ILDX-2.1 LO24B
2.5 (Note 2) STD LP3995ILD-2.5 LP3995ILDX-2.5 LO25B
2.8 STD LP3995ILD-2.8 LP3995ILDX-2.8 LO26B
3.0 STD LP3995ILD-3.0 LP3995ILDX-3.0 LO30B
3.3 (Note 2) STD LP3995ILD-3.3 LP3995ILDX-3.3 LO31B
Note 1: Available in sample quantities only
Note 2: For availability contact your local sales office
Grade LP3995 Supplied as 1000
Units, Tape and Reel
LP3995 Supplied as
4500 Units, Tape and
Reel
Package
Marking
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Page 5
LP3995
Absolute Maximum Ratings
(Notes 3, 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Input Voltage (V
Output Voltage −0.3 to (V
Enable Input Voltage −0.3 to 6.5V
Junction Temperature 150˚C
Lead/Pad Temperature
(Note 5)
micro SMD 260˚C
) −0.3 to 6.5V
IN
+ 0.3V)
IN
to 6.5V (max)
Operating Ratings (Note 3)
Input Voltage (V
Enable Input Voltage 0 to 6.0V
Junction Temperature −40 to +125˚C
Ambient Temperature
Range(Note 7)
IN
Thermal Properties(Note 8)
Junction to Ambient Thermal
Resistance
θ
(LLP pkg.) 88˚C/W
JA
θ
(micro SMD pkg.) 255˚C/W
JA
LLP 235˚C
Storage Temperature −65 to +150˚C
Continuous Power
Internally Limited
Dissipation(Note 7)
ESD (Note 9)
Human Body Model 2 kV
Machine Model 200V
Electrical Characteristics
Unless otherwise noted, VEN= 1.5, VIN=V
and limits appearing in normal type apply for T
range for operation, −40 to +125˚C. (Notes 14, 15)
Symbol Parameter Conditions Typical
V
IN
DEVICE OUTPUT: 1.5 ≤ V
∆V
OUT
Input Voltage 2.5 6.0 V
<
1.8V
OUT
Output Voltage Tolerance I
Line Regulation Error V
micro SMD
Load Regulation Error
LLP
Load Regulation Error
PSRR Power Supply Rejection Ratio
(Note 11)
DEVICE OUTPUT: 1.8 ≤ V
∆V
OUT
Output Voltage Tolerance I
OUT
<
2.5V
microSMDLine Regulation Error V
LLP
Line Regulation Error
micro SMD
Load Regulation Error
LLP
Load Regulation Error
PSRR Power Supply Rejection Ratio
(Note 11)
+ 1.0V, CIN= 1 µF, I
OUT
= 25˚C. Limits appearing in boldface type apply over the full temperature
J
= 1 mA -50 50
OUT
=(V
IN
OUT(NOM)
=1mA
I
OUT
I
=1mAto150mA
OUT
=1mAto150mA
I
OUT
f = 1 kHz, I
f = 10 kHz, I
= 1 mA -50 50
OUT
=(V
IN
=1mA
I
OUT
V
=(V
IN
=1mA
I
OUT
I
=1mAto150mA
OUT
I
=1mAto150mA
OUT
f = 1 kHz, I
f = 10 kHz, I
=1mA 55
OUT
=1mA 53
OUT
OUT(NOM)
OUT(NOM)
=1mA 55
OUT
=1mA 50
OUT
= 1 mA, C
OUT
+1.0V) to 6.0V,
+1.0V) to 6.0V,
+1.0V) to 6.0V,
OUT
) 2.5 to 6.0V
-40 to 85˚C
= 1 µF, cBP= 0.01 µF. Typical values
Limit
Min Max
-75 75
Units
mV
-3.5 3.5 mV/V
10 75
70 125
µV/mA
µV/mA
dB
−75 75
mV
−2.5 2.5 mV/V
−3.5 3.5 mV/V
10 75
80 125
µV/mA
µV/mA
dB
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Page 6
Electrical Characteristics (Continued)
Unless otherwise noted, VEN= 1.5, VIN=V
LP3995
and limits appearing in normal type apply for T
range for operation, −40 to +125˚C. (Notes 14, 15)
Symbol Parameter Conditions Typical
DEVICE OUTPUT: 2.5 ≤ V
∆V
OUT
Output Voltage Tolerance I
OUT
≤ 3.3V
Line Regulation Error V
micro SMD
Load Regulation Error
LLP
Load Regulation Error
Dropout Voltage I
PSRR Power Supply Rejection Ratio
(Note 11)
FULL V
I
LOAD
I
Q
I
SC
E
N
T
SHUTDOWN
RANGE
OUT
Load Current (Notes 10, 11) 0 µA
Quiescent Current VEN= 1.5V, I
Short Circuit Current Limit 450 mA
Output Noise Voltage ((Note 11)) BW = 10 Hz to 100 kHz,
Thermal Shutdown Temperature 160 ˚C
ENABLE CONTROL CHARACTERISTICS
I
EN
V
IL
V
IH
Maximum Input Current at
Input
V
EN
Low Input Threshold 0.4 V
High Input Threshold 0.9 V
TIMING CHARACTERISTICS
T
ON
T
OFF
Note 3: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 4: All voltages are with respect to the potential at the GND pin.
Note 5: For information regarding micro SMD and LLP packages please refer to the following application notes;
AN-1112 Micro SMD Package Wafer Level Chip Scale Package,
AN-1187. Leadless Leadframe Package.
Note 6: Internal Thermal shutdown circuitry protects the device from permanent damage.
Note 7: In applications where high power dissipation and/or poor thermal resistance is present, the maximum ambient temperature may have to be derated.
Maximum ambient temperature (T
the junction to ambient thermal resistance in the application (θ
Note 8: Junction to ambient thermal resistance is highly dependant on the application and board layout. In applications where high thermal dissipation is possible,
special care must be paid to thermal issues in the board design.
Note 9: The human body model is an 100 pF discharge through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into
each pin.
Note 10: The device maintains a stable, regulated output voltage without load.
Note 11: This electrical specification is guaranteed by design.
Note 12: Time from V
Note 13: Time from V
Turn On Time (Note 11) To 95% Level (Note 12) 30 µs
Turn Off Time (Note 11) To 5% Level (Note 13) 175 µs
) is dependant on the maximum operating junction temperature (T
A(max)
= 0.9V to V
EN
= 0.4V to V
EN
OUT
OUT
= 95% (V
=5%(V
OUT(NOM)
+ 1.0V, CIN= 1 µF, I
OUT
= 25˚C. Limits appearing in boldface type apply over the full temperature
J
=1mA -2 2 %of
OUT
=(V
IN
OUT(NOM)
=1mA
I
OUT
I
=1mAto150mA
OUT
I
=1mAto150mA
OUT
=1mA 0.4 2
OUT
I
= 150 mA 60 100
OUT
f = 1 kHz, I
f = 10 kHz, I
EN
V
EN
V
IN
OUT
OUT
= 1.5V, I
= 0.4V 0.003 1.5
= 4.2V, I
OUT
OUT
+1.0V) to 6.0V,
=1mA 60
=1mA 50
=0mA 85 150
OUT
= 150 mA 140 200
OUT
= 1mA
Hysteresis 20
V
= 0.0V and VIN= 6.0V
EN
). This relationship is given by :-
JA
T
A(max)=TJ(max-op)
)
OUT(NOM)
)
−(P
D(max)
= 1 mA, C
x θJA)
= 1 µF, cBP= 0.01 µF. Typical values
OUT
Limit
Min Max
−3 3
−0.1 0.1 %/V
0.0004 0.002 %/mA
0.002 0.005 %/mA
25 µVrms
0.001 µA
), the maximum power dissipation (P
J(max-op)
V
OUT(NOM)
D(max)
Units
mV
dB
µAV
), and
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Page 7
Electrical Characteristics (Continued)
Note 14: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production at TJ= 25˚C or correlated using
Statistical Quality Control methods. Operation over the temperature specification is guaranteed by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Note 15: V
is the stated output voltage option for the device.
OUT(NOM)
Recommended Output Capacitor
LP3995
Symbol Parameter Conditions VALUE
C
OUT
Output Capacitor Capacitance (Note 16) 1.0 0.70 µF
Limit
Min Max
ESR 5 500 mΩ
Note 16: The capacitor tolerance should be±30% or better over the temperature range. The recommended capacitor type is X7R however, dependant on the
application X5R, Y5V, and Z5U can also be used.
Input Test Signals
20034906
FIGURE 1. Line Transient Response Input Test Signal
Units
FIGURE 2. PSRR Input Test Signal
20034907
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Page 8
Typical Performance Characteristics Unless otherwise specified, C
=V
+ 1.0V, TA= 25˚C, Enable pin is tied to VIN.
LP3995
OUT
Output Voltage Change vs Temperature Ground Current vs Load Current (1.8V V
IN=COUT
= 1.0 µF Ceramic, V
)
OUT
IN
20034910
Ground Current vs Load Current (2.8V V
20034912
Ground Current vs V
@
125˚C Dropout vs Load Current
IN
) Ground Current vs V
OUT
20034911
@
25˚C
IN
20034913
20034914
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20034915
Page 9
LP3995
Typical Performance Characteristics Unless otherwise specified, C
=V
+ 1.0V, TA= 25˚C, Enable pin is tied to VIN. (Continued)
OUT
Short Circuit Current Line Transient Response (V
20034916 20034917
Ripple Rejection (V
= 1.8V) Ripple Rejection (V
OUT
IN=COUT
= 1.0 µF Ceramic, V
= 2.8V)
OUT
= 2.8V)
OUT
IN
Enable Start-Up Time (V
20034918 20034919
= 2.8V) Enable Start-Up Time (V
OUT
20034920 20034921
OUT
= 2.8V)
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Page 10
Typical Performance Characteristics Unless otherwise specified, C
=V
+ 1.0V, TA= 25˚C, Enable pin is tied to VIN. (Continued)
LP3995
OUT
IN=COUT
= 1.0 µF Ceramic, V
IN
Enable Start-Up Time (V
Turn-Off Time (V
OUT
= 1.8V) Enable Start-Up Time (V
OUT
20034922 20034923
= 2.8V) Turn-Off Time (V
OUT
= 1.8V)
OUT
= 1.8V)
Load Transient Response (V
20034924 20034925
= 2.8V) Load Transient Response (V
OUT
20034926 20034927
OUT
= 1.8V)
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Page 11
Application Hints
POWER DISSIPATION AND DEVICE OPERATION
The permissible power dissipation for any package is a
measure of the capability of the device to pass heat from the
power source, the junctions of the IC, to the ultimate heat
sink, the ambient environment. Thus the power dissipation is
dependent on the ambient temperature and the thermal
resistance across the various interfaces between the die and
ambient air.
The Thermal Resistance figure
Re-stating the equation in (Note 7) in the electrical specifi-
cation section, the allowable power dissipation for the device
in a given package can be calculated:
With a θJA= 255˚C/W, the device in the micro SMD package
returns a value of 392 mW with a maximum junction temperature of 125˚C.
With a θ
a value of 1.136 mW with a maximum junction temperature
of 125˚C.
The actual power dissipation across the device can be represented by the following equation:
This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage drop
across the device, and the continuous current capability of
the device. These two equations should be used to determine the optimum operating conditions for the device in the
application.
EXTERNAL CAPACITORS
In common with most regulators, the LP3995 requires external capacitors to ensure stable operation. The LP3995 is
specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance.
INPUT CAPACITOR
An input capacitor is required for stability. It is recommended
that a 1.0 µF capacitor be connected between the LP3995
input pin and ground (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than
1 cm from the input pin and returned to a clean analogue
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series
Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the
capacitor to ensure the capacitance will remain ≅ 1.0 µF over
the entire operating temperature range.
= 88˚C/W, the device in the LLP package returns
JA
=(VIN−V
P
D
OUT
)xI
OUT
.
OUTPUT CAPACITOR
The LP3995 is designed specifically to work with very small
ceramic output capacitors. A ceramic capacitor (dielectric
types Z5U, Y5V or X7R) in the 1.0 [to 10 µF] range, and with
ESR between 5 mΩ to 500 mΩ, is suitable in the LP3995
application circuit.
For this device the output capacitor should be connected
between the V
pin and ground.
OUT
It may also be possible to use tantalum or film capacitors at
the device output, V
, but these are not as attractive for
OUT
reasons of size and cost (see the section Capacitor Characteristics).
The output capacitor must meet the requirement for the
minimum value of capacitance and also have an ESR value
that is within the range 5 mΩ to 500 mΩ for stability.
NO-LOAD STABILITY
The LP3995 will remain stable and in regulation with no
external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
CAPACITOR CHARACTERISTICS
The LP3995 is designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer. For
capacitance values in the range of 1 µF to 4.7 µF, ceramic
capacitors are the smallest, least expensive and have the
lowest ESR values, thus making them best for eliminating
high frequency noise. The ESR of a typical 1 µF ceramic
capacitor is in the range of 20 mΩ to 40 mΩ, which easily
meets the ESR requirement for stability for the LP3995.
The temperature performance of ceramic capacitors varies
by type. Most large value ceramic capacitors ( ≥ 2.2 µF) are
manufactured with Z5U or Y5V temperature characteristics,
which results in the capacitance dropping by more than 50%
as the temperature goes from 25˚C to 85˚C.
A better choice for temperature coefficient in a ceramic
capacitor is X7R. This type of capacitor is the most stable
±
and holds the capacitance within
15% over the temperature range. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 1 µF to 4.7 µF range.
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
have to be larger in capacitance (which means bigger and
more costly) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25˚C down to −40˚C, so some guard band must be
allowed.
NOISE BYPASS CAPACITOR
A bypass capacitor should be connected between the C
BP
pin and ground to significantly reduce the noise at the regulator output. This device pin connects directly to a high
impedance node within the bandgap reference circuitry. Any
significant loading on this node will cause a change on the
regulated output voltage. For this reason, DC leakage current through this pin must be kept as low as possible for best
output voltage accuracy.
The use of a 0.01uF bypass capacitor is strongly recommended to prevent overshoot on the output during start-up.
LP3995
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Page 12
Application Hints (Continued)
LP3995
The types of capacitors best suited for the noise bypass
capacitor are ceramic and film. High quality ceramic capacitors with NPO or COG dielectric typically have very low
leakage. Polypropolene and polycarbonate film capacitors
are available in small surface-mount packages and typically
have extremely low leakage current.
Unlike many other LDO’s, the addition of a noise reduction
capacitor does not effect the transient response of the device.
ENABLE OPERATION
The LP3995 may be switched ON or OFF by a logic input at
the ENABLE pin, V
device on. When the enable pin is low, the regulator output is
off and the device typically consumes 3 nA. If the application
does not require the shutdown feature, the V
be tied to V
IN
To ensure proper operation, the signal source used to drive
the V
input must be able to swing above and below the
EN
specified turn-on/off voltage thresholds listed in the Electrical
Characteristics section under V
FAST TURN OFF AND ON
The controlled switch-off feature of the device provides a fast
turn off by discharging the output capacitor via an internal
FET device. This discharge is current limited by the RDSon
of this switch. Fast turn-on is guaranteed by control circuitry
. A high voltage at this pin will turn the
EN
to keep the regulator output permanently on.
and VIH.
IL
pin should
EN
within the reference block allowing a very fast ramp of the
output voltage to reach the target voltage.
micro SMD MOUNTING
The micro SMD package requires specific mounting techniques which are detailed in National Semiconductor Application Note AN-1112.
Referring to the section Surface Mount Technology (SMT)
Assembly Considerations, it should be noted that the pad
style which must be used with the 5 pin package is NSMD
(non-solder mask defined) type.
For best results during assembly, alignment ordinals on the
PC board may be used to facilitate placement of the micro
SMD device.
micro SMD LIGHT SENSITIVITY
Exposing the micro SMD device to direct sunlight will cause
incorrect operation of the device. Light sources such as
halogen lamps can affect electrical performance if they are
situated in proximity to the device.
Light with wavelengths in the red and infra-red part of the
spectrum have the most detrimental effect thus the fluorescent lighting used inside most buildings has very little effect
on performance. Tests carried out on a micro SMD test
board showed a negligible effect on the regulated output
voltage when brought within 1 cm of a fluorescent lamp. A
deviation of less than 0.1% from nominal output voltage was
observed.
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Page 13
Physical Dimensions inches (millimeters) unless otherwise noted
LP3995
micro SMD, 5 Bump, Package (TLA05)
NS Package Number TLA05ADA
The dimensions for X1, X2 and X3 are given as:
X1 = 1.006 +/− 0.03mm
X2 = 1.438 +/− 0.03mm
X3 = 0.600 +/− 0.075mm
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Page 14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LLP, 6 Lead, Package (SOT23 Land)
NS Package Number LDE06A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
LP3995 Micropower 150mA CMOS Voltage Regulator with Active Shutdown
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National Semiconductor
Americas Customer
Support Center
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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