Datasheet LP2988IM-2.5, LP2988AIMX-3.3, LP2988AIMX-3.0, LP2988AIMX-2.5, LP2988AIMMX-5.0 Datasheet (NSC)

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Page 1

March 1999

LP2987/LP2988 Micropower, 200 mA Ultra Low-Dropout Voltage Regulator with Programmable Power-On Reset Delay; Low Noise Version Available (LP2988)

LP2987/LP2988 Micropower, 200 mA Ultra Low-Dropout Voltage Regulator with Programmable

Power-On Reset Delay

General Description

The LP2987/8 are fixed-output 200 mA precision LDO voltage regulators with power-ON reset delay which can be implemented using a single external capacitor.

The LP2988 is specifically designed for noise-critical applications. Asingle external capacitor connected to the Bypass pin reduces regulator output noise.

Using an optimized VIP cess, these regulators deliver superior performance:

Dropout Voltage:180mV load (typical).

Ground Pin Current: 1mA 10 mA load (typical).

Sleep Mode: The LP2987/8 draws less than 2 µA quiescent current when shutdown pin is held low.

Error Flag/Reset: The error flag goes low when the output drops approximately 5%below nominal. This pin also provides a power-ON reset signal if a capacitor is connected to the DELAY pin.

Precision Output: Standard product versions of the LP2987 and LP2988 are available with output voltages of 5.0V, 3.8V,

3.3V, 3.2V, 3.0V, or 2.8V, with guaranteed accuracy of 0.5 (“A” grade) and 1%(standard grade) at room temperature.

™

(Vertically Integrated PNP) pro-

200 mAload,and1mV@1mA

200 mA load, and 200 µA

Block Diagrams

Features

n Ultra low dropout voltage n Power-ON reset delay requires only one component n Bypass pin for reduced output noise (LP2988) n Guaranteed continuous output current 200 mA n Guaranteed peak output current n SO-8 and mini SO-8 surface mount packages

2 µA quiescent current when shutdown

n Low ground pin current at all loads n 0.5%output voltage accuracy (“A” grade) n Wide supply voltage range (16V max)

n Overtemperature/overcurrent protection n −40˚C to +125˚C junction temperature range

250 mA

Applications

n Cellular Phone n Palmtop/Laptop Computer n Camcorder, Personal Stereo, Camera

DS100017-1

VIP™is a trademark ofNational Semiconductor Corporation.

DS100017-2

Page 2

Connection Diagram (LP2987)

Mini SO-8 Package Type MM: See NS Package Drawing Number MUA08A

SO-8 Package Type M: See NS Package Drawing Number M08A

For ordering information, refer to

Surface Mount Packages:

DS100017-3

Top View

Table 1

in this document.

Ordering Information (LP2987)

TABLE 1. Package Marking and Ordering Information

Output Voltage Grade Order Information Package Marking Supplied as:

5 A LP2987AIMMX-5.0 L44A 3.5k Units on Tape and Reel 5 A LP2987AIMM-5.0 L44A 250 Units on Tape and Reel 5 STD LP2987IMMX-5.0 L44B 3.5k Units on Tape and Reel 5 STD LP2987IMM-5.0 L44B 250 Units on Tape and Reel

3.8 A LP2987AIMMX-3.8 L96A 3.5k Units on Tape and Reel

3.8 A LP2987AIMM-3.8 L96A 250 Units on Tape and Reel

3.8 STD LP2987IMMX-3.8 L96B 3.5k Units on Tape and Reel

3.8 STD LP2987IMM-3.8 L96B 250 Units on Tape and Reel

3.3 A LP2987AIMMX-3.3 L43A 3.5k Units on Tape and Reel

3.3 A LP2987AIMM-3.3 L43A 250 Units on Tape and Reel

3.3 STD LP2987IMMX-3.3 L43B 3.5k Units on Tape and Reel

3.3 STD LP2987IMM-3.3 L43B 250 Units on Tape and Reel

3.2 A LP2987AIMMX-3.2 L66A 3.5k Units on Tape and Reel

3.2 A LP2987AIMM-3.2 L66A 250 Units on Tape and Reel

3.2 STD LP2987IMMX-3.2 L66B 3.5k Units on Tape and Reel

3.2 STD LP2987IMM-3.2 L66B 250 Units on Tape and Reel

3.0 A LP2987AIMMX-3.0 L42A 3.5k Units on Tape and Reel

3.0 A LP2987AIMM-3.0 L42A 250 Units on Tape and Reel

3.0 STD LP2987IMMX-3.0 L42B 3.5k Units on Tape and Reel

3.0 STD LP2987IMM-3.0 L42B 250 Units on Tape and Reel

2.8 A LP2987AIMMX-2.8 L89A 3.5k Units on Tape and Reel

2.8 A LP2987AIMM-2.8 L89A 250 Units on Tape and Reel

2.8 STD LP2987IMMX-2.8 L89B 3.5k Units on Tape and Reel

2.8 STD LP2987IMM-2.8 L89B 250 Units on Tape and Reel 5 A LP2987AIMX-5.0 2987AIM5.0 2.5k Units on Tape and Reel 5 A LP2987AIM-5.0 2987AIM5.0 Shipped in Anti-Static Rails 5 STD LP2987IMX-5.0 2987IM5.0 2.5k Units on Tape and Reel 5 STD LP2987IM-5.0 2987IM5.0 Shipped in Anti-Static Rails

3.8 A LP2987AIMX-3.8 2987AIM3.8 2.5k Units on Tape and Reel

3.8 A LP2987AIM-3.8 2987AIM3.8 Shipped in Anti-Static Rails

3.8 STD LP2987IMX-3.8 2987IM3.8 2.5k Units on Tape and Reel

3.8 STD LP2987IM-3.8 2987IM3.8 Shipped in Anti-Static Rails

3.3 A LP2987AIMX-3.3 2987AIM3.3 2.5k Units on Tape and Reel

3.3 A LP2987AIM-3.3 2987AIM3.3 Shipped in Anti-Static Rails

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Page 3

Ordering Information (LP2987) (Continued)

TABLE 1. Package Marking and Ordering Information (Continued)

Output Voltage Grade Order Information Package Marking Supplied as:

3.3 STD LP2987IMX-3.3 2987IM3.3 2.5k Units on Tape and Reel

3.3 STD LP2987IM-3.3 2987IM3.3 Shipped in Anti-Static Rails

3.2 A LP2987AIMX-3.2 2987AIM3.2 2.5k Units on Tape and Reel

3.2 A LP2987AIM-3.2 2987AIM3.2 Shipped in Anti-Static Rails

3.2 STD LP2987IMX-3.2 2987IM3.2 2.5k Units on Tape and Reel

3.2 STD LP2987AIM-3.2 2987IM3.2 Shipped in Anti-Static Rails

3.0 A LP2987IMX-3.0 2987AIM3.0 2.5k Units on Tape and Reel

3.0 A LP2987AIM-3.0 2987AIM3.0 Shipped in Anti-Static Rails

3.0 STD LP2987IMX-3.0 2987IM3.0 2.5 Units on Tape and Reel

3.0 STD LP2987IM-3.0 2987IM3.0 Shipped in Anti-Static Rails

2.8 A LP2987AIMX-2.8 2987AIM2.8 2.5 Units on Tape and Reel

2.8 A LP2987AIM-2.8 2987AIM2.8 Shipped in Anti-Static Rails

2.8 STD LP2987IMX-2.8 2987IM2.8 2.5 Units on Tape and Reel

2.8 STD LP298AIM-2.8 298AIM2.8 Shipped in Anti-Static Rails

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Page 4

Connection Diagram (LP2988)

Mini SO-8 Package Type MM: See NS Package Drawing Number MUA08A

SO-8 Package Type M: See NS Package Drawing Number M08A

For ordering information, refer to

Surface Mount Packages:

DS100017-16

Top View

Table 2

in this document.

Ordering Information (LP2988)

TABLE 2. Package Marking and Ordering Information

Output Voltage Grade Order Information Package Marking Supplied as:

5 A LP2988AIMMX-5.0 L51A 3.5k Units on Tape and Reel 5 A LP2988AIMM-5.0 L51A 250 Units on Tape and Reel 5 STD LP2988IMMX-5.0 L51B 3.5k Units on Tape and Reel 5 STD LP2988IMM-5.0 L51B 250 Units on Tape and Reel

3.8 A LP2988AIMMX-3.8 L0AA 3.5k Units on Tape and Reel

3.8 A LP2988AIMM-3.8 L0AA 250 Units on Tape and Reel

3.8 STD LP2988IMMX-3.8 L0AB 3.5k Units on Tape and Reel

3.8 STD LP2988IMM-3.8 L0AB 250 Units on Tape and Reel

3.3 A LP2988AIMMX-3.3 L50A 3.5k Units on Tape and Reel

3.3 A LP2988AIMM-3.3 L50A 250 Units on Tape and Reel

3.3 STD LP2988IMMX-3.3 L50B 3.5k Units on Tape and Reel

3.3 STD LP2988IMM-3.3 L50B 250 Units on Tape and Reel

3.2 A LP2988AIMMX-3.2 L67A 3.5k Units on Tape and Reel

3.2 A LP2988AIMM-3.2 L67A 250 Units on Tape and Reel

3.2 STD LP2988IMMX-3.2 L67B 3.5k Units on Tape and Reel

3.2 STD LP2988IMM-3.2 L67B 250 Units on Tape and Reel

3.0 A LP2988AIMMX-3.0 L49A 3.5k Units on Tape and Reel

3.0 A LP2988AIMM-3.0 L49A 250 Units on Tape and Reel

3.0 STD LP2988IMMX-3.0 L49B 3.5k Units on Tape and Reel

3.0 STD LP2988IMM-3.0 L49B 250 Units on Tape and Reel

2.8 A LP2988AIMMX-2.8 L0IA 3.5k Units on Tape and Reel

2.8 A LP2988AIMM-2.8 L0IA 250 Units on Tape and Reel

2.8 STD LP2988IMMX-2.8 L0IB 3.5k Units on Tape and Reel

2.8 STD LP2988IMM-2.8 L0IB 250 Units on Tape and Reel 5 A LP2988AIMX-5.0 2988AIM5.0 2.5k Units on Tape and Reel 5 A LP2988AIM-5.0 2988AIM5.0 Shipped in Anti-Static Rails 5 STD LP2988IMX-5.0 2988IM5.0 2.5k Units on Tape and Reel 5 STD LP2988IM-5.0 2988IM5.0 Shipped in Anti-Static Rails

3.8 A LP2988AIMX-3.8 2988AIM3.8 2.5k Units on Tape and Reel

3.8 A LP2988AIM-3.8 2988AIM3.8 Shipped in Anti-Static Rails

3.8 STD LP2988IMX-3.8 2988IM3.8 2.5k Units on Tape and Reel

3.8 STD LP2988IM-3.8 2988IM3.8 Shipped in Anti-Static Rails

3.3 A LP2988AIMX-3.3 2988AIM3.3 2.5k Units on Tape and Reel

3.3 A LP2988AIM-3.3 2988AIM3.3 Shipped in Anti-Static Rails

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Page 5

Ordering Information (LP2988) (Continued)

TABLE 2. Package Marking and Ordering Information (Continued)

Output Voltage Grade Order Information Package Marking Supplied as:

3.3 STD LP2988IMX-3.3 2988IM3.3 2.5k Units on Tape and Reel

3.3 STD LP2988IM-3.3 2988IM3.3 Shipped in Anti-Static Rails

3.2 A LP2988AIMX-3.2 2988AIM3.2 2.5k Units on Tape and Reel

3.2 A LP2988AIM-3.2 2988AIM3.2 Shipped in Anti-Static Rails

3.2 STD LP2988IMX-3.2 2988IM3.2 2.5k Units on Tape and Reel

3.2 STD LP2988IM-3.2 2988IM3.2 Shipped in Anti-Static Rails

3.0 A LP2988AIMX-3.0 2988AIM3.0 2.5k Units on Tape and Reel

3.0 A LP2988AIM-3.0 2988AIM3.0 Shipped in Anti-Static Rails

3.0 STD LP2988IMX-3.0 2988IM3.0 2.5 Units on Tape and Reel

3.0 STD LP2988IM-3.0 2988IM3.0 Shipped in Anti-Static Rails

2.8 A LP2988AIMX-2.8 2988AIM2.8 2.5 Units on Tape and Reel

2.8 A LP2988AIM-2.8 2988AIM2.8 Shipped in Anti-Static Rails

2.8 STD LP2988IMX-2.8 2988IM2.8 2.5 Units on Tape and Reel

2.8 STD LP2988IM-2.8 2988IM2.8 Shipped in Anti-Static Rails

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Page 6

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Storage Temperature Range −65˚C to +150˚C Operating Junction

Temperature Range −40˚C to +125˚C

Lead Temperature

(Soldering, 5 seconds) 260˚C

Input Supply Voltage

(Operating) 2.1V to +16V Shutdown Pin −0.3V to +16V Sense Pin −0.3V to +6V Output Voltage

(Survival) (Note 4) −0.3V to +16V I

(Survival) Short Circuit Protected

OUT

Input-Output Voltage

(Survival) (Note 5) −0.3V to +16V

ESD Rating (Note 2) 2 kV Power Dissipation (Note 3) Internally Limited Input Supply Voltage

(Survival) −0.3V to +16V

Electrical Characteristics

Limits in standard typeface are for TJ= 25˚C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN=VO(NOM) + 1V, IL= 1 mA, C

Symbol Parameter Conditions Typical

∆V

IN–VO

GND

(PK) Peak Output Current V

(MAX) Short Circuit Current RL= 0 (Steady State)

Output Voltage Tolerance

Output Voltage Line Regulation

Dropout Voltage

0.1 mA<I

VO(NOM) + 1V ≤ VIN≤ 16V

IL= 100 µA

(Note 7)

=75mA

= 200 mA

Ground Pin Current IL= 100 µA

=75mA

= 200 mA

0.3V 0.05 1.5 1.5 µA

S/D

≥ VO(NOM) − 5

OUT

(Note 10)

LP2987 Output Noise Voltage (RMS)

LP2988 Output Noise Voltage (RMS)

BW = 300 Hz to 50 kHz, V

=10µF

OUT

BW = 300 Hz to 50 kHz, V

=10µF

OUT

= .01 µF

BYPASS

Ripple Rejection f = 1 kHz, C

0 (LP2988)

BYP

Output Voltage

(Note 9)

OUT

= 3.3V

OUT

Temperature Coefficient

= 4.7 µF, CIN= 2.2 µF, V

OUT

LM2987/8AI-X.X

(Note 6)

= 2V.

S/D

LM2987/8I-X.X

(Note 6)

Min Max Min Max

−0.5 0.5 −1.0 1.0

200 mA −0.8 0.8 −1.6 1.6

−1.8 1.8 −2.8 2.8

0.007

180

100

500

400 250 250

0.014 0.014

0.032 0.032

2.0 2.0

3.5 3.5

120 120

170 170

230 230

350 350

120 120

150 150

800 800

1400 1400

2.1 2.1

3.7 3.7

400

100

=10µF

65 dB

20 ppm/˚C

µV(RMS)

Units

NOM

µA

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Page 7

Electrical Characteristics (Continued)

Limits in standard typeface are for TJ= 25˚C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN=VO(NOM) + 1V, IL= 1 mA, C

Symbol Parameter Conditions Typical

DELAY

Delay Pin Current Source

SHUTDOWN INPUT

S/D

S/D Input Voltage (Note 8)

S/D Input Current V

VH= O/P ON 1.4 1.6 1.6

= O/P OFF 0.55 0.18 0.18

=0 0 −1 −1

S/D

=5V 5 15 15

S/D

ERROR COMPARATOR

THR

(MAX) V

THR

(MIN)

Output “HIGH” Leakage VOH= 16V

Output “LOW” Voltage VIN=VO(NOM) − 0.5V,

(COMP) = 300 µA

Upper Threshold Voltage

Lower Threshold Voltage

HYST Hysteresis 2.0

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions.

Note 2: The ESD rating of the Bypass pin is 500V (LP2988 only.) Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T

and the ambient temperature, T

. The maximum allowable power dissipation at any ambient temperature is calculated using:

= 4.7 µF, CIN= 2.2 µF, V

OUT

2.2

0.01

150

−4.6

−6.6

= 2V.

S/D

LM2987/8AI-X.X

(Note 6)

LM2987/8I-X.X

(Note 6)

Min Max Min Max

1.6 2.8 1.6 2.8

1.4 3.0 1.4 3.0

220 220

350 350

−5.5 −3.5 −5.5 −3.5

−7.7 −2.5 −7.7 −2.5

−8.9 −4.9 −8.9 −4.9

−13.0 −3.3 −13.0 −3.3

(MAX), the junction-to-ambient thermal resistance, θ

Units

µA

OUT

J−A

The value of θ excessive die temperature, and the regulator will go into thermal shutdown.

Note 4: If used in a dual-supply system where the regulator load is returned to a negative supply, the LM2987/8 output must be diode-clamped to ground. Note 5: The output PNP structure contains a diode between the V

on this diode and may induce a latch-up mode which can damage the part (see Application Hints). Note 6: Limits are 100%production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control

(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 7: Dropout voltage is defined as the input to output differential at which the output voltage drops 100 mV below the value measured with a 1V differential. Note 8: Toprevent mis-operation, the Shutdown input must be driven by a signal that swings above V

Application Hints).

Note 9: Temperature coefficient is defined as the maximum (worst-case) change divided by the total temperature range. Note 10: See Typical Performance Characteristics curves.

for the SO-8 (M) package is 160˚C/W,and the mini SO-8 (MM) package is 200˚C/W. Exceeding the maximum allowable power dissipation will cause

J−A

and V

terminals that is normally reverse-biased. Forcing the output above the input will turn

OUT

and below VLwith a slew rate not less than 40 mV/µs (see

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Page 8

Typical Performance Characteristics Unless otherwise specified: T

= 2.2 µF, S/D is tied to VIN,VIN=VO(NOM) + 1V, IL= 1 mA.

vs Temperature

OUT

Dropout Voltage vs Temperature

= 25˚C, C

OUT

= 4.7 µF,

Dropout Voltage vs Load Current

Ground Pin Current vs Temperature and Load

DS100017-17

DS100017-19

DS100017-18

Dropout Characteristics

DS100017-20

Ground Pin Current vs Load Current

DS100017-21

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DS100017-22

Page 9

Typical Performance Characteristics Unless otherwise specified: T

= 2.2 µF, S/D is tied to VIN,VIN=VO(NOM) + 1V, IL= 1 mA. (Continued)

= 25˚C, C

OUT

= 4.7 µF,

Input Current vs V

Load Transient Response

DS100017-23

Input Current vs V

Load Transient Response

DS100017-24

Line Transient Response

DS100017-25

DS100017-27

DS100017-26

Line Transient Response

DS100017-28

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Page 10

Typical Performance Characteristics Unless otherwise specified: T

= 2.2 µF, S/D is tied to VIN,VIN=VO(NOM) + 1V, IL= 1 mA. (Continued)

= 25˚C, C

OUT

= 4.7 µF,

Turn-On Waveform

Short Circuit Current

DS100017-29

DS100017-31

Turn-On Waveform

DS100017-30

Short Circuit Current

DS100017-32

Short Circuit Current vs Output Voltage

DS100017-33

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Instantaneous Short Circuit Current vs Temperature

DS100017-34

Page 11

Typical Performance Characteristics Unless otherwise specified: T

= 2.2 µF, S/D is tied to VIN,VIN=VO(NOM) + 1V, IL= 1 mA. (Continued)

= 25˚C, C

OUT

= 4.7 µF,

DC Load Regulation

Shutdown Voltage vs Temperature

DS100017-35

Shutdown Pin Current vs Shutdown Pin Voltage

DS100017-36

Input to Output Leakage vs Temperature

Delay Pin Current vs V

DS100017-37

DS100017-45

Delay Pin Current vs Delay Pin Voltage

DS100017-38

DS100017-48

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Page 12

Typical Performance Characteristics Unless otherwise specified: T

= 2.2 µF, S/D is tied to VIN,VIN=VO(NOM) + 1V, IL= 1 mA. (Continued)

Delay Sink Current vs Temperature

= 25˚C, C

OUT

= 4.7 µF,

Output Impedance vs Frequency

Ripple Rejection (LP2987)

DS100017-47

DS100017-40

DS100017-46

Output Impedance vs Frequency

DS100017-41

Ripple Rejection (LP2988)

DS100017-42

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DS100017-51

Page 13

Typical Performance Characteristics Unless otherwise specified: T

= 2.2 µF, S/D is tied to VIN,VIN=VO(NOM) + 1V, IL= 1 mA. (Continued)

= 25˚C, C

OUT

= 4.7 µF,

Output Noise Density (LP2987)

Output Noise Density (LP2988)

Output Noise Voltage (LP2988)

DS100017-44

DS100017-39

Output Noise Density (LP2988)

Turn-On Time (LP2988)

DS100017-52

DS100017-54

DS100017-53

Turn-On Time (LP2988)

DS100017-55

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Page 14

Typical Performance Characteristics Unless otherwise specified: T

= 2.2 µF, S/D is tied to VIN,VIN=VO(NOM) + 1V, IL= 1 mA. (Continued)

Turn-On Time (LP2988)

DS100017-56

Basic Application Circuits

= 25˚C, C

OUT

= 4.7 µF,

*Capacitance value shown is minimum required to assure stability, but may be increased without limit. Larger output capacitor provides improved dynamic

response. **Shutdown must be actively terminated (see Application Hints). Tie to INPUT (pin 4) if not used.

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DS100017-5

DS100017-6

Page 15

Application Hints

EXTERNAL CAPACITORS

As with any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance.

INPUT CAPACITOR: An input capacitor (≥ 2.2 µF) is re- quired between the LP2987/8 input and ground (amount of capacitance may be increased without limit).

This capacitor must be located a distance of not more than

0.5” from the input pin and returned to a clean analog ground. Any good quality ceramic or tantalum may be used for this capacitor.

OUTPUT CAPACITOR: The output capacitor must meet the requirement for minimum amount of capacitance and also have an appropriate E.S.R. (equivalent series resistance) value.

Curves are provided which show the allowable ESR range as a function of load current for 3V and 5V outputs.

ESR Curves For 5V Output

DS100017-7

ESR Curves For 3V Output

DS100017-8

IMPORTANT: The output capacitor must maintain its ESR in the stable region

the application

The minimum required amount of output capacitance is

4.7 µF. Output capacitor size can be increased without limit. It is important to remember that capacitor tolerance and

variation with temperature must be taken into consideration when selecting an output capacitor so that the minimum re-

over the full operating temperature range of

to assure stability.

quired amount of output capacitance is provided over the full operating temperature range. A good Tantalumcapacitor will show very little variation with temperature, but a ceramic may not be as good (see next section).

The output capacitor should be located not more than 0.5” from the output pin and returned to a clean analog ground.

CAPACITOR CHARACTERISTICS TANTALUM: A solid tantalum capacitor is the best choice for

the output capacitor on the LM2987/8. Available from many sources, their typical ESR is very close to the ideal value required on the output of many LDO regulators.

Tantalums also have good temperature stability: a 4.7 µF was tested and showed only a 10%decline in capacitance as the temperature was decreased from +125˚C to −40˚C. The ESR increased only about 2:1 over the same range of temperature.

However,it should be noted that the increasing ESR at lower temperatures present in all tantalums can cause oscillations when marginal quality capacitors are used (where the ESR of the capacitor is near the upper limit of the stability range at room temperature).

CERAMIC: The ESR of ceramic capacitor can be low enough to cause an LDO regulator to oscillate: a 2.2 µF ceramic was measured and found to have an ESR of 15 mΩ.

If a ceramic capacitor is to be used on the LP2987/8 output, a1Ωresistor should be placed in series with the capacitor to provide a minimum ESR for the regulator.

A disadvantage of ceramic capacitors is that their capacitance varies a lot with temperature: Large ceramic capacitors are typically manufactured with the Z5U temperature characteristic, which results in the capacitance dropping by 50%as the temperature goes from 25˚C to 80˚C.

This means you have to buy a capacitor with twice the minimum C

to assure stable operation up to 80˚C.

OUT

ALUMINUM: The large physical size of aluminum electrolytics makes them unsuitable for most applications. Their ESR characteristics are also not well suited to the requirements of LDO regulators. The ESR of a typical aluminum electrolytic is higher than a tantalum, and it also varies greatly with temperature.

A typical aluminum electrolytic can exhibit an ESR increase of 50X when going from 20˚C to −40˚C. Also, some aluminum electrolytics can not be used below −25˚C because the electrolyte will freeze.

POWER-ON RESET DELAY

A power-on reset function can be easily implemented using the LP2987/8 by adding a single external capacitor to the Delay pin. The Error output provides the power-on reset signal when input power is applied to the regulator.

The reset signal stays low for a pre-set time period after power is applied to the regulator, and then goes high (see Timing Diagram below).

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Page 16

Application Hints (Continued)

DS100017-9

Timing Diagram for Power-Up

The external capacitor c The value of capacitor required for a given time delay may

sets the delay time (T

DLY

be calculated using the formula:

DLY=TDELAY

/(5.59 X 105)

To simplify design, a plot is provided below which shows values of C

versus delay time.

DLY

Plot of C

DLY

vs T

DS100017-11

DELAY

DETAILS OF ERR/RESET CIRCUIT OPERATION: (Refer

to LP2987/8 Equivalent Circuit).

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DELAY

DS100017-10

LP2987/8 Equivalent Circuit

The output of comparator U2 is the ERR/RESET flag. Since it is an open-collector output, it requires the use of a pull-up resistor (R put of U2, which means that its output is controlled by the

). The 1.23V reference is tied to the inverting in-

voltage applied to the non-inverting input. The output of U1 (also an open-collector) will force the non-

inverting input of U2 to go low whenever the LP2987/8 regulated output drops about 5%below nominal.

U1’s inverting input is also held at 1.23V. The other input samples the regulated output through a resistive divider (R and RB). When the regulated output is at nominal voltage, the voltage at the divider tap point will be 1.23V. If this voltage drops about 60 mV below 1.23V, the output of U1 will go low forcing the output of U2 low (which is the ERROR state).

Power-ON reset delay occurs when a capacitor (shown as C

) is connected to the Delay pin. At turn-ON, this capaci-

DLY

tor is initially fully discharged (which means the voltage at the Delay pin is 0V). The output of U1 keeps C charged (by sinking the 2.2 µA from the current source) until

DLY

fully dis-

the regulator output voltage comes up to within about 5%of nominal. At this point, U1’s output stops sinking current and the 2.2 µA starts charging up C

When the voltage across C U2 will go high (note that D1 limits the maximum voltage to

DLY

reaches 1.23V, the output of

DLY

about 2V). SELECTING C

this capacitor is 1 µF. The capacitor must not have exces-

: The maximum recommended value for

DLY

sively high leakage current, since it is being charged from a

2.2 µA current source. Aluminum electrolytics can not be used, but good-quality

tantalum, ceremic, mica, or film types will work.

SHUTDOWN INPUT OPERATION

The LP2987/8 is shut off by driving the Shutdown input low, and turned on by pulling it high. If this feature is not to be used, the Shutdown input should be tied to V regulator output on at all times.

to keep the

Page 17

Application Hints (Continued)

To assure proper operation, the signal source used to drive the Shutdown input must be able to swing above and below the specified turn-on/turn-off voltage thresholds listed as V and VL, respectively (see Electrical Characteristics).

It is also important that the turn-on (and turn-off) voltage signals applied to the Shutdown input have a slew rate which is not less than 40 mV/µs.

CAUTION:

if a slow-moving AC (or DC) signal is applied that is in the range between V

REVERSE INPUT-OUTPUT VOLTAGE

The PNP power transistor used as the pass element in the LP2987/8 has an inherent diode connected between the regulator output and input.

During normal operation (where the input voltage is higher than the output) this diode is reverse-biased.

However, if the output is pulled above the input, this diode will turn ON and current will flow into the regulator output.

In such cases, a parasitic SCR can latch which will allow a high current to flow into V can damage the part.

In any application where the output may be pulled above the input, an external Schottky diode must be connected from V

verse voltage across the LP2987/8 to 0.3V (see Absolute Maximum Ratings).

BYPASS CAPACITOR (LP2988)

The capacitor connected to the Bypass pin must have very low leakage. The current flowing out of the Bypass pin comes from the Bandgap reference, which is used to set the output voltage. Since the Bandgap circuit has only a few microamps flowing in it, loading effects due to leakage current will cause a change in the regulated output voltage.

Curves are provided which show the effect of loading the Bypass pin on the regulated output voltage.

the regulator output state can not be guaranteed

and VL.

(and out the ground pin), which

to V

(cathode on VIN, anode on V

OUT

), to limit the re-

Care must be taken to ensure that the capacitor selected for bypass will not have significant leakage current over the operating temperature range of the application.

A high quality ceramic capacitor which uses either NPO or

COG type dielectiric material will typically have very low leakage. Small surface-mount polypropolene or polycarbonate film capacitors also have extremely low leakage, but are slightly larger in size than ceramics.

DS100017-49

DS100017-50

www.national.com17

Page 18

Physical Dimensions inches (millimeters) unless otherwise noted

Mini SO-8 Package Type MM

NS Package Number MUA08A

www.national.com 18

Page 19

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

LP2987/LP2988 Micropower, 200 mA Ultra Low-Dropout Voltage Regulator with Programmable

Power-On Reset Delay

SO-8 Package Type M

NS Package Number M08A

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labeling, can be reasonably expected to result in a significant injury to the user.

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