Datasheet LNK623PG Specification

LNK623-626

Auto-Restart

LinkSwitch-CV Family

Energy-Efcient, Off-line Switcher with Accurate
Primary-side Constant-Voltage (CV) Control

Product Highlights

Dramatically Simplies CV Converters

• Eliminates optocoupler and all secondary CV control circuitry

• Eliminates bias winding supply – IC is self biasing

Advanced Performance Features

• Compensates for external component temperature variations

• Very tight IC parameter tolerances using proprietary trimming

technology

• Continuous and/or discontinuous mode operation for design

exibility

• Frequency jittering greatly reduces EMI lter cost

• Even tighter output tolerances achievable with external resistor

selection/trimming

Advanced Protection/Safety Features

• Auto-restart protection reduces delivered power by >95% for

output short-circuit and all control loop faults (open and shorted
components)

• Hysteretic thermal shutdown – automatic recovery reduces power

supply returns from the eld

• Meets HV creepage requirements between Drain and all other pins,

both on the PCB and at the package

EcoSmart™– Energy Efcient

• No-load consumption <200 mW at 230 VAC and down to below

70 mW with optional external bias

• Easily meets all global energy efciency regulations with no added

components

• ON/OFF control provides constant efciency down to very light

loads – ideal for mandatory EISA and ENERGY STAR 2.0 regulations

• No primary or secondary current sense resistors – maximizes

efciency

Green Package

• Halogen free and RoHS compliant package

Applications

• DVD/STB

• Adapters

• Standby and auxiliary supplies

• Home appliances, white goods and consumer electronics

• Industrial controls

Description

The LinkSwitchTM-CV dramatically simplies low power, constant voltage
(CV) converter design through a revolutionary control technique which
eliminates the need for both an optocoupler and secondary CV control
circuitry while providing very tight output voltage regulation. The
combination of proprietary IC trimming and E-Shield™ transformer
construction techniques enables Clampless™ designs with the
LinkSwitch-CV LNK623/4.

LinkSwitch-CV provides excellent cross-regulation for multiple-output

yback applications such as DVDs and STBs. A 725 V power MOSFET

and ON/OFF control state machine, self-biasing, frequency jittering,
cycle-by-cycle current limit, and hysteretic thermal shutdown circuitry
are all incorporated onto one IC.

*

Wide Range

High-Voltage

DC Input

LinkSwitch-CV

(a) Typical Application Schematic

V

O

(b) Output Characteristic

Figure 1. Typical Application Schematic (a) and Output Characteristic Envelope

(b). *Optional with LNK623-624PG/DG. (see Key Application Consider-
ations section for clamp and other external circuit design considerations).

D

S

FB

BP

±5%

PI-5196-012315

PI-5195-012915

I

O

Output Power Table

230 VAC ±15% 85-265 VAC

Product

3

Adapter

LNK623PG/DG 6.5 W 9 W 5.0 W 6 W

LNK624PG/DG 7 W 11 W 5.5 W 6.5 W

LNK625PG/DG 8 W 13.5 W 6.5 W 8 W

LNK626 PG/DG 10.5 W 17 W 8.5 W 10 W

Table 1. Output Power Table. Based on 5 V Output.

Note s:

1. Minimum continuous power in a t ypical non-ventilated enclosed adapter
measured at +50 °C ambient.

2. Maximum prac tical continuous power in an open frame design with adequate
heat sinking, measured at 50 °C ambient (see Key Application Considerations
section for more information).

3. Packages: P: PDIP-8C, D: SO-8C.

Figure 2. PDIP-8C and SO-8C Packages.

1

Peak or

Open

Frame

2

Adapter

1

Peak or

Open

Frame

2

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This Product is Covered by Patents and/or Pending Patent Applications.

LNK623-626

BYPASS

(BP)

FEEDBACK

(FB)

V

TH

+

-

t

SAMPLE-OUT

D Q

FB

OUT

STATE

MACHINE

I

LIM

DC

MAX

Drive

Reset

V

ILIMIT

6 V
5 V

DRAIN

REGULATOR

6 V

+

-

(D)

6.5 V

SOURCE

(S)

FB

DC

MAX

I

Auto-Restart

Open-Loop

OSCILLATOR

LIM

FAULT

Figure 3 Functional Block Diagram.

Pin Functional Description

DRAIN (D) Pin:

This pin is the power MOSFET drain connection. It provides internal
operating current for both start-up and steady-state operation.

BYPASS (BP) Pin:

This pin is the connection point for an external bypass capacitor for
the internally generated 6 V supply.

FEEDBACK (FB) Pin:

During normal operation, switching of the power MOSFET is
controlled by this pin. This pin senses the AC voltage on the bias
winding. This control input regulates the output voltage based on the

yback voltage of the bias winding.

SOURCE (S) Pin:

This pin is internally connected to the output MOSFET source for
high-voltage power and control circuit common returns.

THERMAL

SHUTDOWN

t

SAMPLE-OUT

+

V

-

ILIMIT

Current Limit

Comparator

P Package (DIP-8C)

FB

1

BP

2

D

4

Figure 4. Pin Conguration.

8

7

6

5

SAMPLE

DELAY

LEADING

EDGE

BLANKING

S

S

S

S

SOURCE

(S)

PI-5197-012915

D Package (SO-8C)

FB

BP

1

2

4

D

8

7

6

5

PI-5198-012315

S

S

S

S

2

Rev. I 08/16

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LNK623-626

LinkSwitch-CV Functional Description

The LinkSwitch-CV combines a high-voltage power MOSFET switch
with a power supply controller in one device. Similar to the
LinkSwitch-LP and TinySwitch-III it uses ON/OFF control to regulate
the output voltage. The LinkSwitch-CV controller consists of an
oscillator, feedback (sense and logic) circuit, 6 V regulator, over­temperature protection, frequency jittering, current limit circuit,
leading-edge blanking, and ON/OFF state machine for CV control.

Constant Voltage (CV) Operation

The controller regulates the FEEDBACK pin voltage to remain at V
using an ON/OFF state-machine. The FEEDBACK pin voltage is
sampled 2.5 ms after the turn-off of the high-voltage switch. At light
loads the current limit is also reduced to decrease the transformer

ux density.

Auto-Restart and Open-Loop Protection

In the event of a fault condition such as an output short or an open
loop condition the LinkSwitch-CV enters into an appropriate
protection mode as described below.

In the event the FEEDBACK pin voltage during the Flyback period falls
below V
for a duration in excess of 200 ms (auto-restart on-time (t
converter enters into auto-restart, wherein the power MOSFET is

-0.3 V before the FEEDBACK pin sampling delay (~2.5 ms)

FBth

AR-O N

disabled for 2.5 seconds (~8% auto-restart duty cycle). The auto-restart
alternately enables and disables the switching of the power MOSFET
until the fault condition is removed.

In addition to the conditions for auto-restart described above, if the
sensed FEEDBACK pin current during the Forward period of the
conduction cycle (switch “on” time) falls below 120 mA, the converter
annunciates this as an open-loop condition (top resistor in potential

FBth

) the

divider is open or missing) and reduces the auto-restart time from
200 ms to approximately 6 clock cycles (90 ms), whilst keeping the
disable period of 2.5 seconds. This effectively reduces the auto­restart duty cycle to less than 0.01%.

Over-Temperature Protection

The thermal shutdown circuitry senses the die temperature. The
threshold is set at 142 °C typical with a 60 °C hysteresis. When the
die temperature rises above this threshold (142 °C) the power
MOSFET is disabled and remains disabled until the die temperature
falls by 60 °C, at which point the MOSFET is re-enabled.

Current Limit

The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (I
MOSFET is turned off for the remainder of that cycle. The leading

), the power

LIMIT

edge blanking circuit inhibits the current limit comparator for a short
time (t
blanking time has been set so that current spikes caused by

) after the power MOSFET is turned on. This leading edge

LEB

capacitance and rectier reverse recovery time will not cause

premature termination of the MOSFET conduction.

6.0 V Regulator

The 6 V regulator charges the bypass capacitor connected to the
BYPASS pin to 6 V by drawing a current from the voltage on the
DRAIN, whenever the MOSFET is off. The BYPASS pin is the internal
supply voltage node. When the MOSFET is on, the device runs off of
the energy stored in the bypass capacitor. Extremely low power
consumption of the internal circuitry allows the LinkSwitch-CV to
operate continuously from the current drawn from the DRAIN pin.
A bypass capacitor value of 1 mF is sufcient for both high frequency
decoupling and energy storage.

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3

Rev. I 08/16

LNK623-626

Applications Example

L

85 - 265

VAC

N

F1

3.15 A

RT1

10 Ω

D1

FR106

RV1

275 V

D3

1N4007

D2

FR106

D4

1N4007

L1

3.5 × 7.6 mm
Ferrite Bead

C1
22 µF
400 V

L2

680 µH

R1

5.1 kΩ
1/8 W

VR1

1N5272B

C2
22 µF
400 V

R2

390 Ω

D5

1N4007

LinkSwitch-CV

U1

LNK626PG

D

FB

BP

S

C4
1 µF
50 V

C3

820 pF

1 kV

R4

6.2 kΩ

680 pF

50 V

C5

T1

EEL19

1 6

3

R5
47 kΩ
1/8 W

7

11

8,9,10

12

5

4

2

4.02 kΩ

UF4003

1N4148

R6

1%

UF4003

D7 SB540

R10

47 Ω

D9

D6

D8

R3

6.34 kΩ
1%

C6

10 µF

50 V

C13

270 pF

PI-5205-033116

Figure 5. 7 W (10 W peak) Multiple Output Flyback Converter for DVD Applications with Primary Sensed Feedback.

C9

47 µF

25 V

C8

1000 µF

10 V

C11

47 µF

50 V

L3

10 µH

C10

470 µF

10 V

R9
39 kΩ
1/8 W

R8
24 kΩ
1/8 W

510 Ω
1/8 W

-22 V, 15 mA

12 V, 0.1 A

5 V, 1.7 A

R7

RTN

Circuit Description

This circuit is congured as a three output, primary-side regulated
yback power supply utilizing the LNK626PG. It can deliver 7 W

continuously and 10 W peak (thermally limited) from an universal

input voltage range (85 – 265 VAC). Efciency is >67% at 115

VAC/230 VAC and no-load input power is <140 mW at 230 VAC.

Input Filter

AC input power is rectied by diodes D1 through D4. The rectied
DC is ltered by the bulk storage capacitors C1 and C2. Inductor L1,
L2, C1 and C2 form a pi (π) lter, which attenuates conducted
differential-mode EMI noise. This conguration along with Power

Integrations transformer E-shield technology allow this design to
meet EMI standard EN55022 class B with good margin without
requiring a Y capacitor. Fuse F1 provides protection against

catastrophic failure. Negative temperature coefcient thermistor RT1
limits the inrush current when AC is rst applied to below the

maximum rating of diodes D1 through D4. Metal oxide varistor RV1
clamps the AC input during differential line transients, protecting the
input components and maintaining the peak drain voltage of U1
below its 725 V BV
2 kV this component may be omitted.

LNK626 Primary

The LNK626PG device (U1) incorporates the power switching device,
oscillator, CV control engine, startup, and protection functions. The
integrated 725 V MOSFET provides a large drain voltage margin in
universal input AC applications, increasing reliability and also reducing
the output diode voltage stress by allowing a greater transformer
turns ratio. The device can be completely self-powered from the
BYPASS pin and decoupling capacitor C4. In this design a bias circuit
(D6, C6 and R4) was added to reduce no load input power below
140 mW.

rating. For differential surge levels at or below

DSS

The rectied and ltered input voltage is applied to one side of the

primary winding of T1. The other side of the transformer’s primary
winding is driven by the integrated MOSFET in U1. The leakage
inductance drain voltage spike is limited by the clamp circuit D5, R1,
R2, C3 and VR1. The Zener bleed clamp arrangement was selected
for lowest no-load input power but in applications where higher
no-load input power is acceptable VR1 may be omitted and the value
of R1 increased to form a standard RCD clamp.

Output Rectication

The secondaries of the transformer are rectied by D7, D8 and D9.
A Schottky barrier type was used for the main 5 V output for higher

efciency. The +12 V and -22 V outputs use an ultrafast rectier
diode. The main output is post ltered by L3 and C10 to remove

switching frequency ripple. Resistors R7, R8 and R9 provide a
preload to maintain the output voltages within their respective limits
when unloaded. To reduce high frequency ringing and associated
radiated EMI an RC snubber formed by R10 and C13 was added
across D7.

Output Regulation

The LNK626 regulates the output using ON/OFF control, enabling or
disabling switching cycles based on the sampled voltage on the
FEEDBACK pin. The output voltage is sensed using a primary
referenced winding on transformer T1 eliminating the need for an
optocoupler and a secondary sense circuit. The resistor divider formed
by R3 and R6 feeds the winding voltage into U1. Standard 1% resistor
values were used to center the nominal output voltages. Resistor R5
and C5 reduce pulse grouping by creating an offset voltage that is
proportional to the number of consecutive enabled switching cycles.

4

Rev. I 08/16

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LNK623-626

Key Application Considerations

Output Power Table

The data sheet maximum output power table (Table 1) represents the
maximum practical continuous output power level that can be obtained

in a yback converter under the following assumed conditions:

1. The minimum DC input voltage is 100 V or higher at 90 VAC input.

The value of the input capacitance should be large enough to
meet these criteria for AC input designs.

2. Secondary output of 5 V with a Schottky rectier diode.

3. Assumed efciency of 80%.

4. Continuous conduction mode operation (K

5. Reected Output Voltage (V

6. The part is board mounted with SOURCE pins soldered to a

sufcient area of copper to keep the SOURCE pin temperature at

or below 110 °C for P package and 100 °C for D packaged
devices.

) of 110 V.

OR

7. Ambient temperature of 50 °C for open frame designs and an

internal enclosure temperature of 60 °C for adapter designs.

Note: Higher output power are achievable if the efciency is higher

than 80%, typically for high output voltage designs.

BYPASS Pin Capacitor

A 1 mF BYPASS pin capacitor (C4) is recommended. The capacitor
voltage rating should be equal to or greater than 6.8 V. The
capacitor’s dielectric material is not important. The capacitor must be
physically located close to the LinkSwitch-CV BYPASS pin.

Circuit board layout

LinkSwitch-CV is a highly integrated power supply solution that
integrates on a single die, both the controller and the high-voltage
MOSFET. The presence of high switching currents and voltages
together with analog signals makes it especially important to follow
good PCB design practice to ensure stable and trouble free operation
of the power supply.

When designing a board for the LinkSwitch-CV based power supply, it
is important to follow the following guidelines:

= 0.4).

P

Single Point Grounding

Use a single point (Kelvin) connection at the negative terminal of the

input lter capacitor for the LinkSwitch-CV SOURCE pin and bias

winding return. This improves surge capabilities by returning surge

currents from the bias winding directly to the input lter capacitor.

Bypass Capacitor

The BYPASS pin capacitor should be located as close as possible to
the SOURCE and BYPASS pins.

Feedback Resistors

Place the feedback resistors directly at the FEEDBACK pin of the
LinkSwitch-CV device. This minimizes noise coupling.

Thermal Considerations

The copper area connected to the SOURCE pins provide the
LinkSwitch-CV heat sink. A rule of thumb estimate is that the
LinkSwitch-CV will dissipate 10% of the output power. Provide
enough copper area to keep the SOURCE pin temperature below
110° C to provide margin for part to part R

Secondary Loop Area

To minimize leakage inductance and EMI, the area of the loop
connecting the secondary winding, the output diode and the output

lter capacitor should be minimized. In addition, sufcient copper

area should be provided at the anode and cathode terminal of the
diode for heat sinking. A larger area is preferred at the quiet cathode
terminal. A large anode area can increase high frequency radiated EMI.

Electrostatic Discharge Spark Gap

In chargers and adapters ESD discharges may be applied to the
output of the supply. In these applications the addition of a spark
gap is recommended. A trace is placed along the isolation barrier to
form one electrode of a spark gap. The other electrode, on the
secondary-side, is formed by the output return node. The arrange­ment directs ESD energy from the secondary to the primary side AC
input. A 10 mil gap is placed near the AC input. The gap decouples
any noise picked up on the spark gap trace to the AC input. The
trace from the AC input to the spark gap electrode should be spaced
away from other traces to prevent unwanted arcing occurring and
possible circuit damage.

DS(O N)

variation.

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5

Rev. I 08/16

LNK623-626

Input Filter

Capacitor

Copper area

maximized for

heat sinking

Primary Side Secondary Side

Drain trace area

miniminzed

Clamp

Components

VR1

C1

L1

R2

C3

Isolation Barrier

Capacitor

(optional)

T1

Y1

C12

Output

Rectifiers

D9

R10

Output Filter

Capacitor

C11

C13

D1 D3

D2

F1

J1

AC

+

IN

Figure 6. PCB Layout Example.

B+

D7

L3

C8

C10

C9

R9

R7

L2

D4

RV1

RT1

R1

R5

FB

BP

R6

D5

D

R3

R4

D6

C6

Transformer

ESD

JP1

D8

R8

J2

1 6

C2

U1

S

S
S
S

C4

C5

spark gap

10 mil

-

gap

CLAMP

Bypass

Capacitor

close to device

Feedback

Resistors close

to device

DC Outputs

PI-5269-012315

B+

CLAMP

D

FB

BP

S

PRI RTN

Bias currents
return to bulk
capacitor

Figure 7. Schematic Representation of Recommended Layout without

External Bias.

Kelvin connection at

SOURCE pin, no power

currents in signal traces

Minimize

FEEDBACK

pin node

area

PI-5265-012315

6

Rev. I 08/16

Small FEEDBACK

pin node area

D

FB

BP

S

PRI RTN

Bias currents
return to bulk
capacitor

Figure 8. Schematic Representation of Recommended Layout with

External Bias.

Kelvin connection at

SOURCE pin, no power

currents in signal traces

Bias resistor

PI-5266-012315

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B+

LNK623-626

Drain trace in close

proximity of feedback trace

will couple noise into

feedback signal

Power currents

PRI RTN

flow in signal
source trace

Trace

impedance

∆V

Voltage drops across trace impedance

may cause degraded performance

D

FB

BP

S

Isource

S

Figure 9. Schematic Representation of Electrical Impact of Improper Layout.

CLAMP

Bias winding

currents flow in

signal source traces

PI-5267-012615

Line surge
currents can
flow through
device

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7

Rev. I 08/16

LNK623-626

Drain Clamp

Recommended Clamp Circuits

R

C2

D

C2

R

C1

D

C1

C

C1

PI-5108-110308

R

C1

D

C1

C

C1

PI-5107-012615

R

C2

Figure 10. RCD Clamp, Low Power or Low Leakage Inductance Designs. RCD Clamp With Zener Bleed. High Power or High Leakage Inductance Designs.

Components R1, R2, C3, VR1 and D5 in Figure 5 comprise the clamp.
This circuit is preferred when the primary leakage inductance is greater
than 125 mH to reduce drain voltage overshoot or ringing present on
the feedback winding. For best output regulation, the feedback

R

C2

C

C1

voltage must settle to within 1% at 2.1 ms from the turn off of the
primary MOSFET. This requires careful selection of the clamp circuit
components. The voltage of VR1 is selected to be ~20% above the

reected output voltage (VOR). This is to clip any turn off spike on the
drain but avoid conduction during the yback voltage interval when the

output diode is conducting. The value of R1 should be the largest

R

C1

D

C1

value that results in acceptable settling of the FEEDBACK pin voltage
and peak drain voltage. Making R1 too large will increase the discharge
time of C3 and degrade regulation. Resistor R2 dampens the leakage
inductance ring. The value must be large enough to dampen the ring
in the required time but must not be too large to cause the drain

PI-5107-012615

voltage to exceed 680 V.

If the primary leakage inductance is less than 125 mH, VR1 can be
eliminated and the value of R1 increased. A value of 470 kW with an
820 pF capacitor is a recommended starting point. Verify that the
peak drain voltage is less than 680 V under all line and load conditions.
Verify the feedback winding settles to an acceptable limit for good
line and load regulation.

Effect of Fast (500 ns) versus Slow (2 ms) Recovery Diodes in
Clamp Circuit on Pulse Grouping and Output Ripple.

A slow reverse recovery diode reduces the feedback voltage ringing.
The amplitude of ringing with a fast diode represents 8% error in
Figure 11.

8

Rev. I 08/16

Black Trace: DC1 is a FR107 (fast type, trr = 500 ns)
Gray Trace: D

is a 1N4007G (standard recovery, trr = 2 us)

C1

Figure 11. Effect of Clamp Diode on FEEDBACK Pin Settling. Clamp Circuit (top).

FEEDBACK Pin Voltage (bottom).

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LNK623-626

Clampless Designs

Clampless designs rely solely on the drain node capacitance to limit
the leakage inductance induced peak drain-to-source voltage.
Therefore the maximum AC input line voltage, the value of VOR, the
leakage inductance energy, (a function of leakage inductance and
peak primary current), and the primary winding capacitance determine

the peak drain voltage. With no signicant dissipative element

present, as is the case with an external clamp, the longer duration of
the leakage inductance ringing can increase EMI.

The following requirements are recommended for a universal input or
230 VAC only Clampless design:

1. Clampless designs should only be used for P

of ≤90 V

2. For designs with P

ensure adequate primary intra-winding capacitance in the range

≤5 W, a two-layer primary must be used to

O

≤5 W using a VOR

O

of 25 pF to 50 pF. A bias winding must be added to the trans-

former using a standard recovery rectier diode (1N4003–

1N4007) to act as a clamp. This bias winding may also be used
to externally power the device by connecting a resistor from the
bias winding capacitor to the BYPASS pin. This inhibits the
internal high-voltage current source, reducing device dissipation
and no-load consumption.

3. For designs with P

an external RCD or Zener clamp should be used.

>5 W, Clampless designs are not practical and

O

4. Ensure that worst-case, high line, peak drain voltage is below the

BV

specication of the internal MOSFET and ideally ≤650 V to

DSS

allow margin for design variation.

VOR (Reected Output Voltage), is the secondary output plus output

diode forward voltage drop that is reected to the primary via the

turns ratio of the transformer during the diode conduction time. The
VOR adds to the DC bus voltage and the leakage spike to determine the
peak drain voltage.

Pulse Grouping

Pulse grouping is dened as 6 or more consecutive pulses followed by

two or more timing state changes. The effect of pulse grouping is
increased output voltage ripple. This is shown on the right of Figure
12 where pulse grouping has caused an increase in the output ripple.

To eliminate group pulsing verify that the feedback signal settles
within 2.1 ms from the turn off of the internal MOSFET. A Zener diode
in the clamp circuit may be needed to achieve the desired settling
time. If the settling time is satisfactory, then a RC network across
R

(R6) of the feedback resistors is necessary.

LOWER

The value of R (R5 in the Figure 13) should be an order of magnitude
greater than R
C5 in Figure 13.

and selected such that R×C = 32 ms where C is

LOWER

Quick Design Checklist

As with any power supply design, all LinkSwitch-CV designs should be

veried on the bench to make sure that component specications are

not exceeded under worst-case conditions. The following minimum
set of tests is strongly recommended:

1. Maximum drain voltage – Verify that peak V

680 V at highest input voltage and maximum output power.

LinkSwitch-CV

U1

LNK626PG

D

FB

BP

S

C4
1 µF
50 V

Figure 13. RC Net work Across R

R4

6.2 kΩ

BOTTOM

47 kΩ
1/8 W

680 pF

(R6) to Reduce Pulse Grouping.

does not exceed

DS

5

4

2

R5

4.02 kΩ

C5

50 V

D6

1N4148

R6

1%

PI-5268-110608

R3

6.34 kΩ
1%

C6

10 µF

50 V

Top Trace: Drain Waveform (200 V/div)

Top Trace: Drain Waveform (200 V/div)
Bottom Trace: Output Ripple Voltage (50 mV/div)

Bottom Trace: Output Ripple Voltage (50 mV/div)

Figure 12. Not Pulse Grouping (<5 Consecutive Switching Cycles). Pulse Grouping (>5 Consecutive Switching Cycles).

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Split Screen with Bottom Screen Zoom

Split Screen with Bottom Screen Zoom
Top Trace: Drain Waveform (200 V/div)

Top Trace: Drain Waveform (200 V/div)
Bottom Trace: Output Ripple Voltage (50 mV/div)

Bottom Trace: Output Ripple Voltage (50 mV/div)

9

Rev. I 08/16

LNK623-626

2. Maximum drain current – At maximum ambient temperature,

maximum input voltage and maximum output load, verify drain
current waveforms at start-up for any signs of transformer
saturation and excessive leading edge current spikes. LinkSwitch-CV
has a leading edge blanking time of 215 ns to prevent premature
termination of the ON-cycle. Verify that the leading edge current
spike is below the allowed current limit envelope for the drain
current waveform at the end of the 215 ns blanking period.

3. Thermal check – At maximum output power, both minimum and

maximum input voltage and maximum ambient temperature;

verify that temperature specications are not exceeded for

LinkSwitch-CV, transformer, output diodes and output capacitors.
Enough thermal margin should be allowed for the part-to-part
variation of the R
sheet. It is recommended that the maximum SOURCE pin
temperature does not exceed 110 °C.

of LinkSwitch-CV, as specied in the data

DS(O N)

Design Tools

Up-to-date information on design tools can be found at the Power
Integrations web site: www.power.com

10

Rev. I 08/16

www.power.com

LNK623-626

Absolute Maximum Ratings

1,5

DRAIN Voltage ........................................................-0.3 V to 725 V

DRAIN Peak Current: LNK623 .................................400 (600) mA

LNK624 .................................400 (600) mA

LNK625 ................................. 528 (790) mA

LNK626 ............................... 720 (1080) mA

Peak Negative Pulsed DRAIN Current .................................-100 mA2

Feedback Pin Voltage .................................................. -0.3 V to 9 V

Feedback Pin Current ..........................................................10 0 mA

BYPASS Pin Voltage .................................................... -0.3 V to 9 V

BYPASS Pin Current ...............................................................10 mA

Storage Temperature ...................................... .......... -65 °C to 150 °C

Operating Junction Temperature ..............................-40 °C to 150 °C

Lead Temperature

(3)

.............................................................. 260 °C

Thermal Resistance

Thermal Resistance: P Package:

(qJA) .......................... .............. 70 °C/W2; 60 °C/W

(qJC)1 ...................................................... 11 °C/W

D Package:

(qJA) .....................................100 °C/W2; 80 °C/W

(qJC)1 ....................................................... 30 °C/W

Conditions

Parameter Symbol

SOURCE = 0 V; T

(Unless Otherwise Specied)

J

Notes:

4

1. All voltages referenced to SOURCE, TA = 25 °C.

4

2. Duration not to exceed 2 msec.

4

3. 1/16 in. from case for 5 seconds.

4

4. The higher peak DRAIN current is allowed while the DRAIN
voltage is simultaneously less than 400 V.

5. Maximum ratings specied may be applied, one at a time

without causing permanent damage to the product.
Exposure to Absolute Maximum ratings for extended
periods of time may affect product reliability.

Notes:

3

1. Measured on pin 8 (SOURCE) close to plastic interface.

2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.

3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.

3

= -40 to 125 °C

Min Typ Max Units

Control Functions

Output Frequency f

Frequency Jitter

Ratio of Output
Frequency at Auto­Restart

f

OSC(AR)

Maximum Duty Cycle DC

FEEDBACK Pin Voltage V

FEEDBACK Pin
Voltage Temperature

TC

Coefcient

FEEDBACK Pin Voltage
at Turn-Off Threshold

V

Power Coefcient I

OSC

MAX

FBth

VFB

FB(AR)

2

TJ = 25 °C, VFB = V

FBth

Peak-Peak Jitter Compared to

Average Frequency, T

TJ = 25 °C

Relative to f

OSC

TJ = 25 °C

See Notes B, C

LNK623/6 93 100 106 kHz

= 25 °C

J

, See Note C

±7 %

80 %

54 %

LNK623-624P 1.815 1.840 1.865

TJ = 25 °C

See Figure 15

CBP = 1 mF

See Note D

LNK623-624D 1.855 1.880 1.905

V

LNK625P, LNK625D 1.835 1.860 1.885

LNK626P, LNK626D 1.775 1.800 1.825

-0.01 %/°C

1.45 V

2

2

I

f = I

LIMI T(TYP)

× f

OSC( TYP)

f

2

2

I

f = I

LIMI T(TYP)

× f

OSC( TYP)

LNK623/6P

TJ = 25 °C

LNK623/6D

TJ = 25 °C

0.9 × I2f I2f 1.17 × I2f

0.9 × I2f I2f 1.21 × I2f

2

A

Hz

www.power.com

11

Rev. I 08/16

LNK623-626

Parameter Symbol

Control Functions (cont.)

Minimum Switch
“O n”-T ime

FEEDBACK Pin
Sampling Delay

DRAIN Supply

Current

t

ON(min)

Conditions

SOURCE = 0 V; T

(Unless Otherwise Specied)

t

FB

I

S1

FB Voltage = V

I

S2

Switch ON-Time = tON (MOSFET

FB Voltage > V

Switching at f

= -40 to 125 °C

J

Min Typ Max Units

See Note C 700 ns

2.35 2.55 2.75 ms

FBth

280 330

LNK623/4 440 520

FBth

OSC

-0.1,
LNK625 480 560

)

LNK626 520 600

mA

BYPASS Pin

Charge Current

BYPASS Pin Voltage V

BYPASS Pin

Voltage Hysteresis

BYPASS Pin

Shunt Voltage

V

Circuit Protection

Current Limit I

Leading Edge
Blanking Time

Thermal Shutdown
Temperature

I

CH1

I

CH2

V

SHUNT

LIMIT

t

LEB

T

BPH

VBP = 0 V

LNK623/4 -5.0 -3.4 -1.8

LNK625/6 -7.0 -4.5 -2.0

mA

LNK623/4 -4.0 -2. 3 -1.0

VBP = 4 V

LNK625/6 -5.6 -3.2 -1.4

BP

5.65 6.00 6.25 V

0.70 1.00 1.20 V

6.2 6.5 6.8 V

LNK623

di/dt = 50 mA/ms , TJ = 25 °C

LNK624

di/dt = 60 mA/ms , T

= 25 °C

J

LNK625

di/dt = 80 mA/ms , TJ = 25 °C

LNK626

di/dt = 110 mA/ms , TJ = 25 °C

TJ = 25 °C

See Note C

SD

196 210 225

233 250 268

mA

307 330 353

419 450 482

170 215 ns

135 142 150 °C

Thermal Shutdown
Hysteresis

12

Rev. I 08/16

T

SDH

60 °C

www.power.com

Parameter Symbol

Output

Conditions

SOURCE = 0 V; T

(Unless Otherwise Specied)

LNK623

ID = 50 mA

= -40 to 125 °C

J

TJ = 25 °C 24 28

TJ = 100 °C 36 42

LNK623-626

Min Typ Max Units

ON-State
Resistance

OFF-State
Leakage

Breakdown

Voltage

DRAIN Supply

Voltage

Auto-Restart
ON -Time

Auto-Restart
OF F-Time

Open-Loop

FEEDBACK Pin
Current Threshold

R

BV

t

t

DS(O N)

I

DSS1

I

DSS2

DSS

AR-O N

AR-O FF

I

OL

LNK624

ID = 50 mA

LNK625

ID = 62 mA

LNK626

ID = 82 mA

VDS = 560 V, See Figure 20

TJ = 125 °C, See Note A

VDS = 375 V, See Figure 20

TJ = 50 °C

TJ = 25 °C

See Figure 20

VFB = 0

See Note C

See Note C -12 0 mA

TJ = 25 °C 24 28

TJ = 100 °C 36 42

W

TJ = 25 °C 16 19

TJ = 100 °C 24 28

TJ = 25 °C 9.6 11

TJ = 100 °C 14 17

50

mA

15

725 V

50 V

200 ms

LNK623/624/626 2 s

LNK625 1

Open-Loop
ON -Time

See Note C 90 ms

NOTES:

A. I

is the worst-case OFF-state leakage specication at 80% of BV

DSS1

specication under worst-case application conditions (rectied 265 VAC) for no-load consumption calculations.

B. When the duty cycle exceeds DC

the LinkSwitch-CV operates in on-time extension mode.

MAX

and maximum operating junction temperature. I

DSS

is a typical

DSS2

C. This parameter is derived from characterization.

D. Mechanical stress induced during the assembly may cause shift in this parameter. This shift has not impact on the ability of LinkSwitch-CV

to meet CV = ±5% in mass production given the design follows recommendation in AN-45 and good manufacturing practice.

13

www.power.com

Rev. I 08/16

LNK623-626

(Normalized to 25 °C)

Feedback Voltage

(Normalized to 25 °C)

Breakdown Voltage

(Normalized to 25

Drain Current (mA)

Drain Capacitance (pF)

600

PI-5212-012615

Typical Performance Characteristics

1.200

1.000

0.800

0.600

Frequency

0.400

0.200

0.000

-40 -15 10 35 60 85 110 135

Temperature (°C)

Figure 14. Output Frequency vs. Temperature.

1.1

°C)

1.0

PI-5086-012315

PI-2213-012315

1.200

1.000

0.800

0.600

0.400

0.200

0.000

-40 -15 10 35 60 85 110 135

Temperature (°C)

Figure 15. Feedback Voltage vs. Temperature.

300

250

T
T

CASE

CASE

=25 °C
=100 °C

200

150

PI-5089-012315

PI-5211-080708

0.9

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

Figure 16. Breakdown vs. Temperature.

1000

100

10

1

0 100 200 300 400 500 600

Drain Voltage (V)

Figure 18. C

vs. Drain Voltage. Figure 19. Drain Capacitance Power.

OSS

Scaling Factors:
LNK623 1.0
LNK624 1.0
LNK625 1.5
LNK626 2.5

PI-5201-012615

100

50

Scaling Factors:
LNK623 1.0
LNK624 1.0
LNK625 1.5
LNK626 2.5

0

0 2 4 6 8 10

DRAIN Voltage (V)

Figure 17. Output Characteristic.

50

Scaling Factors:
LNK623 1.0
LNK624 1.0

40

LNK625 1.5
LNK626 2.5

30

20

Power (mW)

10

0

0 200 400

DRAIN Voltage (V)

14

Rev. I 08/16

www.power.com

LinkSwitch-CV

5 µF

50 kΩ

16 V

LNK623-626

FB

S

10 kΩ

4 kΩ

V

IN

+

1 µF

S1

.1 µF

BP

S

S

D

S

S2

Curve
Tracer

To measure BV

1) Close S1, open S2

2) Power-up V

3) Open S1, close S2

4) Measure I/V characteristics of DRAIN pin using the curve tracer

Figure 20. Test Set-up for Leakage and Breakdown Tests.

, I

, and I

DSS

DSS1

source (16 V)

IN

follow these steps:

DSS2

PI-5203-012615

www.power.com

15

Rev. I 08/16

LNK623-626

-E-

.240 (6.10)
.260 (6.60)

Pin 1

-D-

.125 (3.18)
.145 (3.68)

-T­SEATING
PLANE

.100 (2.54) BSC

D S

⊕

.356 (9.05)
.387 (9.83)

.014 (.36)
.022 (.56)

.004 (.10)

.048 (1.22)
.053 (1.35)

⊕

T E D S

PDIP-8C (P Package)

Notes:

1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.

2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.

3. Dimensions shown do not include mold flash or other
protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.

4. Pin locations start with Pin 1, and continue counter-clock­ wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.

5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).

6. Lead width measured at package body.

7. Lead spacing measured with the leads constrained to be
.057 (1.45)
.068 (1.73)

(NOTE 6)

.015 (.38)

MINIMUM

.118 (3.00)
.140 (3.56)

.137 (3.48)

MINIMUM

.010 (.25) M

perpendicular to plane T.

.008 (.20)
.015 (.38)

.300 (7.62) BSC

(NOTE 7)

.300 (7.62)
.390 (9.91)

P08C

PI-3933-081716

16

Rev. I 08/16

www.power.com

SO-8C (D Package)

LNK623-626

0.10 (0.004)

2X

1.35 (0.053)

1.75 (0.069)

0.10 (0.004)

0.25 (0.010)

4

3.90 (0.154) BSC

2

D

C

Pin 1 ID

1.27 (0.050) BSC

B

4.90 (0.193) BSC

A

8

1

1.25 - 1.65

(0.049 - 0.065)

4

5

6.00 (0.236) BSC

4

0.10 (0.004)

D

2X

7X 0.31 - 0.51 (0.012 - 0.020)

0.25 (0.010)

0.10 (0.004)

7X

SEATING PLANE

C

2

A-B

2X

C

0.20 (0.008)

M

C A-B D

C

SEATING
PLANE

C

C

1.04 (0.041) REF

0.40 (0.016)

1.27 (0.050)

H

0.17 (0.007)

0.25 (0.010)

DETAIL A

o

0 - 8

0.25 (0.010)
BSC

DETAIL A

GAUGE
PLANE

Reference
Solder Pad
Dimensions

2.00 (0.079)

D07C

1.27 (0.050)

Part Ordering Information

LNK 625 D G - TL

+

Notes:

1. JEDEC reference: MS-012.

4.90 (0.193)

+

+

+

0.60 (0.024)

• LinkSwitch Product Family

• CV Series Number

• Package Identier

P Plastic PDIP-8C

D Plastic SO-8C

• Package Material

G GREEN: Halogen Free and RoHS Compliant

• Tape & Reel and Other Options

Blank Standard Congurations

TL Tape & Reel, 2.5 k pcs for D Package. Not available for P Package.

2. Package outline exclusive of mold flash and metal burr.

3. Package outline inclusive of plating thickness.

4. Datums A and B to be determined at datum plane H.

5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.

PI-4526-012315

www.power.com

17

Rev. I 08/16

LNK623-626

Revision Notes Date

B Release data sheet. 11/08
C Correction made to Figure 5. 12/08
D Introduced Max Current Limit when V DRAIN is below 400 V. 07/09
E Introduced LNK626DG. 09/09
F Added Note 4 to Parameter Table 02/10
F Specied Max BYPASS Pin Current. 03/14

Figure removed “Test Set-up for FEEDBACK Pin Measurements” from previous version. Updated t

G

Updated to latest Brand Style.

H Update BV

from 700 V to 725 V 08/15

DSS

H Corrected schematic error in Figure 5. 03/16

I Updated PDIP-8C (P Package) per PCN-16232. 08/16

parameter.

AR-O FF

02/15

18

Rev. I 08/16

www.power.com

Notes

LNK623-626

www.power.com

19

Rev. I 08/16

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGR ATIONS MAKES NO WARRANT Y
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information

The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRIT TEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose

failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signicant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the

failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE-iDriver, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch, InnoSwitch, Hi p erTFS,
HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of
Power Integrations, Inc. Other trademarks are property of their respective companies. ©2016, Power Integrations, Inc.

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