Datasheet LNK564PN, LNK564DN Specification

LNK562-564

®

LinkSwitch-LP

Energy Effi cient Off-Line Switcher IC for
Linear Transformer Replacement

Product Highlights

Lowest System Cost and Advanced Safety Features

• Lowest component count switcher

• Very tight parameter tolerances using proprietary IC
trimming technology and transformer construction
techniques enable Clampless™designs – decreases
component count/system cost and increases effi ciency

• Meets industry standard requirements for thermal overload
protection – eliminates the thermal fuse used with linear
transformers or additional components in RCC designs

• Frequency jittering greatly reduces EMI – enables low cost
input fi lter confi guration

• Meets HV creepage requirements between DRAIN and all
other pins, both on the PCB and at the package

• Proprietary E-Shield™ transformer eliminates Y-capacitor

AC

IN

LinkSwitch-LP

V

O

V

R

D

FB

BP

S

(a)

PI-3923-092705

Rated Output Power = VR • I

+

DC

Output

R

Superior Performance over Linear and RCC

• Hysteretic thermal shutdown protection – automatic
recovery improves fi eld reliability

• Universal input range allows worldwide operation

• Auto-restart reduces delivered power by >85% during
short circuit and open loop fault conditions

• Simple ON/OFF control, no loop compensation needed

• High bandwidth provides fast turn on with no overshoot
and excellent transient load response

EcoSmart®– Energy Effi ciency Technology

• Easily meets all global energy effi ciency regulations with
no added components

• No-load consumption <150 mW at 265 VAC input

• ON/OFF control provides constant effi ciency to very
light loads – ideal for mandatory CEC regulations

Applications

• Chargers for cell/cordless phones, PDAs, power tools,
MP3/portable audio devices, shavers etc.

• Standby and auxiliary supplies

Description

LinkSwitch-LP switcher ICs cost effectively replace all
unregulated isolated linear transformer based (50/60 Hz) power
supplies up to 3 W output power. For worldwide operation, a
single universal input design replaces multiple linear transformer
based designs. The self-biased circuit achieves an extremely low
no-load consumption of under 150 mW. The internal oscillator
frequency is jittered to signifi cantly reduce both quasi-peak and
average EMI, minimizing fi lter cost.

I

R

(b)

PI-3924-011706

Figure 1. Typical Application – not a Simplifi ed Circuit (a) and
Output Characteristic Envelope (b).

OUTPUT POWER TABLE

I

O

1

230 VAC ±15% 85-265 VAC

PRODUCT

4

Adapter

2

Frame

Open

Adapter

3

Open

2

Frame

LNK562P/G/D 1.9 W 1.9 W 1.9 W 1.9 W

LNK563P/G/D 2.5 W 2.5 W 2.5 W 2.5 W

LNK564P/G/D 3 W 3 W 3 W 3 W

Table 1. Output Power Table.

Notes:

1. Output power may be limited by specifi c application parameters
including core size and Clampless operation (see Key Application
Considerations).

2. Minimum continuous power in a typical non-ventilated enclosed
adapter measured at 50 °C ambient.

3. Minimum practical continuous power in an open frame design with
adequate heat sinking, measured at 50 °C ambient.

4. Packages: P: DIP-8B, G: SMD-8B, D: SO-8C. For lead-free
package options, see Part Ordering Information.

3

November 2008

LNK562-564

E

BYPASS

(BP)

FEEDBACK

(FB)

OPEN LOOP
PULLDOWN

0.8 V

+

1.69 V -V

TH

Figure 2. Functional Block Diagram.

6.3 V

JITTER

ADJ

OSCILLATOR

AUTO-RESTART

COUNTER

RESET

CLOCK

DC

MAX

FAULT
PRESENT

5.8 V

4.85 V

+

-

THERMAL

SHUTDOWN

SRQ

REGULATOR

5.8 V

BYPASS PIN
UNDER-VOLTAGE

Q

CURRENT LIMIT
COMPARATOR

+

-

LEADING

EDGE

BLANKING

PI-3958-092905

DRAIN

(D)

V

I

LIMIT

SOURC

(S)

Pin Functional Description

DRAIN (D) Pin:

The power MOSFET drain connection provides internal
operating current for both startup and steady-state operation.

BYPASS (BP) Pin:

A 0.1 μF external bypass capacitor for the internally generated

5.8 V supply is connected to this pin.

FEEDBACK (FB) Pin:

During normal operation, switching of the power MOSFET is
controlled by this pin. MOSFET switching is disabled when a
current greater than 70 μA fl ows into this pin.

SOURCE (S) Pin:

This pin is the power MOSFET source connection. It is also the
ground reference for the BYPASS and FEEDBACK pins.

LinkSwitch-LP Functional
Description

LinkSwitch-LP comprises a 700 V power MOSFET switch with
a power supply controller on the same die. Unlike conventional
PWM (pulse width modulation) controllers, it uses a simple
ON/OFF control to regulate the output voltage. The controller
consists of an oscillator, feedback (sense and logic) circuit, 5.8
V regulator, BYPASS pin undervoltage circuit, over-temperature

P Package (DIP-8B)

G Package (SMD-8B)

S

1

S

2

BP

3

FB

4

Figure 3. Pin Confi guration.

8

7

5

D Package (SO-8C)

BP

S

S

D

FB

1

2

D

4

S

8

7

S

6

S

5

S

PI-4547-011107

protection, frequency jittering, current limit circuit, and leading
edge blanking.

Oscillator

The typical oscillator frequency is internally set to an average
of 66/83/100 kHz for the LNK562, 563 & 564 respectively.
Two signals are generated from the oscillator: the maximum
duty cycle signal (DC

) and the clock signal that indicates

MAX

the beginning of each switching cycle.

2

Rev. H 11/08

LNK562-564

The oscillator incorporates circuitry that introduces a small
amount of frequency jitter, typically 5% of the switching
frequency, to minimize EMI. The modulation rate of the
frequency jitter is set to 1 kHz to optimize EMI reduction
for both average and quasi-peak emissions. The frequency
jitter, which is proportional to the oscillator frequency, should
be measured with the oscilloscope triggered at the falling
edge of the DRAIN voltage waveform. The waveform in
Figure 4 illustrates the frequency jitter. The oscillator frequency
is reduced when the FB pin voltage is less than 1.69 V as
described below.

Feedback Input Circuit

The feedback input circuit at the FB pin consists of a low
impedance source follower output set at 1.69 V. When the current
delivered into this pin exceeds 70 μA, a low logic level (disable)
is generated at the output of the feedback circuit. This output
is sampled at the beginning of each cycle on the rising edge of
the clock signal. If high, the power MOSFET is turned on for
that cycle (enabled), otherwise the power MOSFET remains
off (disabled). Since the sampling is done only at the beginning
of each cycle, subsequent changes in the FB pin voltage or
current during the remainder of the cycle are ignored. When
the FB pin voltage falls below 1.69 V, the oscillator frequency
linearly reduces to typically 48% at the auto-restart threshold
voltage of 0.8 V. This function limits the power supply output
current at output voltages below the rated voltage regulation
threshold VR (see Figure 1).

Over-Temperature Protection

The thermal shutdown circuitry senses the die temperature.
The threshold is set at 142 °C typical with a 75 °C hysteresis.
When the die temperature rises above this threshold (142 °C)
the power MOSFET is disabled and remains disabled until the
die temperature falls by 75 °C, at which point the MOSFET
is re-enabled.

Current Limit

The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (I

LIMIT

), the
power MOSFET is turned off for the remainder of that cycle. The
leading edge blanking circuit inhibits the current limit comparator
for a short time (t

) after the power MOSFET is turned on. This

LEB

leading edge blanking time has been set so that current spikes
caused by capacitance and rectifi er reverse recovery time will
not cause premature termination of the MOSFET conduction.

600

500

V

400

300

200

100

DRAIN

PI-3660-081303

5.8 V Regulator and 6.3 V Shunt Voltage Clamp

The 5.8 V regulator charges the bypass capacitor connected to
the BYPASS pin to 5.8 V by drawing a current from the voltage
on the DRAIN, whenever the MOSFET is off. The BYPASS
pin is the internal supply voltage node. When the MOSFET
is on, the device runs off of the energy stored in the bypass
capacitor. Extremely low power consumption of the internal
circuitry allows LinkSwitch-LP to operate continuously from the
current drawn from the DRAIN pin. A bypass capacitor value of

0.1 μF is suffi cient for both high frequency decoupling and
energy storage.

In addition, there is a 6.3 V shunt regulator clamping the
BYPASS pin at 6.3 V when current is provided to the BYPASS
pin externally. This facilitates powering the device externally
through a resistor from the bias winding to decrease the no­load consumption.

BYPASS Pin Undervoltage

The BYPASS pin undervoltage circuitry disables the power
MOSFET when the BYPASS pin voltage drops below 4.85 V.
Once the BYPASS pin voltage drops below 4.85 V, it must rise
back to 5.8 V to enable (turn on) the power MOSFET.

0

020

Figure 4. Frequency Jitter at f

68 kHz
64 kHz

Time (μs)

.

OSC

Auto Restart

In the event of a fault condition such as output short circuit or
an open loop condition, LinkSwitch-LP enters into auto-restart
operation. An internal counter clocked by the oscillator gets reset
every time the FB pin voltage exceeds the FEEDBACK Pin
Auto-Restart Threshold Voltage (V
drops below V

for more than 100 ms, the power MOSFET

FB(AR)

). If the FB pin voltage

FB(AR)

switching is disabled. The auto-restart alternately enables and
disables the switching of the power MOSFET at a duty cycle
of typically 12% until the fault condition is removed.

3

Rev. H 11/08

LNK562-564

L

J-1

90-265

J-2

N

1N4937

VAC

1N4005

D1

D2

RF1*

8.2 Ω

2.5 W

L1

3300 μH

C1
10 μF
400 V

LinkSwitch-LP

U1

LNK564PN

T1

EE16

2

1

D

FB

BP

S

C2

0.1 μF
50 V

Figure 5. 6 V, 330 mA CV/CC Linear Replacement Power Supply.

Applications Example

The circuit shown in Figure 5 is a typical implementation of
a 6 V, 330 mA, constant voltage, constant current (CV/CC)
output power supply.

VR1*

R3

1N5240B

2 kΩ

10 V

C4*

100 pF

250 VAC

*Optional components

6 V,

0.33 A

J3-2

J3-1

RTN

7

6

4

5

D3

1N4005

D4

UF4002

R2

3 kΩ

C5

220 μF

25 V

R1

37.4 kΩ

C3

330 nF

50 V

PI-4106-010208

output of the power supply), the power supply will turn OFF
for 800 ms and then turn back on for 100 ms. It will continue
in this mode until the auto-restart threshold is exceeded. This
function reduces the average output current during an output
short circuit condition.

AC input differential fi ltering is accomplished with the very
low cost input fi lter stage formed by C1 and L1. The proprietary
frequency jitter feature of the LNK564 eliminates the need for
an input pi fi lter, so only a single bulk capacitor is required.
Adding a sleeve may allow the input inductor L1 to be used as a
fuse as well as a fi lter component. This very simple Filterfuse™
input stage further reduces system cost. Alternatively, a fusible
resistor RF1 may be used to provide the fusing function.

Input diode D2 may be removed from the neutral phase in
applications where decreased EMI margins and/or decreased
input surge withstand is allowed. In such applications, D1 will
need to be an 800 V diode.

The power supply utilizes simplifi ed bias winding voltage
feedback, enabled by LNK564 ON/OFF control. The resistor
divider formed by R1 and R2 determine the output voltage across
the transformer bias winding during the switch OFF time. In the
V/I constant voltage region, the LNK564 device enables/disables
switching cycles to maintain 1.69 V on the FB pin. Diode D3 and
low cost ceramic capacitor C3 provide rectifi cation and fi ltering
of the primary feedback winding waveform. At increased loads,
beyond the constant power threshold, the FB pin voltage begins
to reduce as the power supply output voltage falls. The internal
oscillator frequency is linearly reduced in this region until it
reaches typically 50% of the starting frequency. When the FB
pin voltage drops below the auto-restart threshold (typically

0.8 V on the FB pin, which is equivalent to 1 V to 1.5 V at the

No-load consumption can be further reduced by increasing C3
to 0.47 μF or higher.

A Clampless primary circuit is achieved due to the very
tight tolerance current limit trimming techniques used in
manufacturing the LNK564, plus the transformer construction
techniques used. Peak drain voltage is therefore limited to
typically less than 550 V at 265 VAC, providing signifi cant
margin to the 700 V minimum drain voltage specifi cation
(BV

).

DSS

Output rectifi cation and fi ltering is achieved with output rectifi er
D4 and fi lter capacitor C5. Due to the auto-restart feature, the
average short circuit output current is signifi cantly less than
1 A, allowing low cost rectifi er D4 to be used. Output circuitry is
designed to handle a continuous short circuit on the power supply
output. Diode D4 is an ultra-fast type, selected for optimum
V/I output characteristics. Optional resistor R3 provides a
preload, limiting the output voltage level under no-load output
conditions. Despite this preload, no-load consumption is within
targets at approximately 140 mW at 265 VAC. The additional
margin of no-load consumption requirement can be achieved
by increasing the value of R4 to 2.2 kΩ or higher while still
maintaining output voltage well below the 9 V maximum
specifi cation. Placement is left on the board for an optional
Zener clamp (VR1) to limit maximum output voltage under
open loop conditions, if required.

4

Rev. H 11/08

LNK562-564

Key Application Considerations

Output Power Table

The data sheet maximum output power table (Table 1) represents
the maximum practical continuous output power level that can
be obtained under the following assumed conditions:

1. The minimum DC input voltage is 90 V or higher for 85 VAC
input, or 240 V or higher for 230 VAC input or 115 VAC with
a voltage doubler. The value of the input capacitance should
be large enough to meet these criteria for AC input designs.

2. Secondary output of 6 V with a Schottky rectifi er diode.

3. Assumed effi ciency of 70%.

4. Voltage only output (no secondary-side constant current
circuit).

5. Discontinuous mode operation (K

6. A suitably sized core to allow a practical transformer design
(see Table 2).

7. The part is board mounted with SOURCE pins soldered
to a suffi cient area of copper to keep the SOURCE pin
temperature at or below 100 °C.

8. Ambient temperature of 50 °C for open frame designs and an
internal enclosure temperature of 60 °C for adapter designs.

LinkSwitch-LP Device

Core Size LNK562 LNK563 LNK564

EE13 1.1 W 1.4 W 1.7 W

EE16 1.3 W 1.7 W 2 W

EE19 1.9 W 2.5 W 3 W

Table 2. Estimate of Transformer Power Capability vs.
LinkSwitch-LP Device and Core Size at a Flux Density of
1500 Gauss (150 mT).

Below a value of 1, KP is the ratio of ripple to peak primary
current. Above a value of 1, KP is the ratio of primary MOSFET
OFF time to the secondary diode conduction time. Due to
the fl ux density requirements described below, typically a
LinkSwitch-LP design will be discontinuous, which also has
the benefi t of allowing lower-cost fast (vs. ultra-fast) output
diodes and reducing EMI.

> 1).

P

1. Clampless designs should only be used for PO ≤ 2.5 W using
a VOR of ≤ 90 V

2. For designs with PO ≤ 2 W, a two-layer primary must be
used to ensure adequate primary intra-winding capacitance
in the range of 25 pF to 50 pF.

3. For designs with 2 < PO ≤ 2.5 W, a bias winding must be added
to the transformer using a standard recovery rectifi er diode
(1N4003– 1N4007) to act as a clamp. This bias winding may
also be used to externally power the device by connecting
a resistor from the bias winding capacitor to the BYPASS
pin. This inhibits the internal high-voltage current source,
reducing device dissipation and no-load consumption.

4. For designs with PO >2.5 W, Clampless designs are not practical
and an external RCD or Zener clamp should be used.

5. Ensure that worst-case, high line, peak drain voltage is below
the BV

specifi cation of the internal MOSFET and ideally

DSS

≤ 650 V to allow margin for design variation.

VOR (Refl ected Output Voltage), is the secondary output plus
output diode forward voltage drop that is refl ected to the
primary via the turns ratio of the transformer during the diode
conduction time. The VOR adds to the DC bus voltage and the
leakage spike to determine the peak drain voltage.

Audible Noise

The cycle skipping mode of operation used in LinkSwitch-LP
can generate audio frequency components in the transformer.
To limit this audible noise generation, the transformer should
be designed such that the peak core fl ux density is below
1500 Gauss (150 mT). Following this guideline and using the
standard transformer production technique of dip varnishing,
practically eliminates audible noise. Vacuum impregnation
of the transformer is not recommended, as it does not provide
any better reduction of audible noise than dip varnishing. And
although vacuum impregnation has the benefi t of increased
transformer capacitance (which helps in Clampless designs),
it can also upset the mechanical design of the transformer,
especially if shield windings are used. Higher fl ux densities are
possible, increasing the power capability of the transformers
above what is shown in Table 2. However careful evaluation of
the audible noise performance should be made using production
transformer samples before approving the design.

Clampless Designs

Clampless designs rely solely on the drain node capacitance
to limit the leakage inductance induced peak drain-to-source
voltage. Therefore the maximum AC input line voltage, the
value of V

, the leakage inductance energy, (a function of

OR

leakage inductance and peak primary current), and the primary
winding capacitance determine the peak drain voltage. With no
signifi cant dissipative element present, as is the case with an
external clamp, the longer duration of the leakage inductance
ringing can increase EMI.

The following requirements are recommended for a universal
input or 230 VAC only Clampless design:

Ceramic capacitors that use dielectrics such as Z5U, when used
in clamp circuits, may also generate audio noise. If this is the
case, try replacing them with a capacitor having a different
dielectric or construction, for example a fi lm type.

Bias Winding Feedback

To give the best output regulation in bias winding designs, a
slow diode such as the 1N400x series should be used as the
rectifi er. This effectively fi lters the leakage inductance spike
and reduces the error that this would give when using fast
recovery time diodes. The use of a slow diode is a requirement
in Clampless designs.

5

Rev. H 11/08

LNK562-564

TOP VIEW

Transformer

Output Filter

Capacitor

Y1-

Capacitor

+

DC

OUT

-

D

S

S

LinkSwitch-LP

FB

BP

S

S

Maximize hatched copper
areas ( ) for optimum
heatsinking

C

HV DC

-

INPUT

BP

Input Filter

Capacitor

+

PI-4157-101305

Figure 6. Recommended Circuit Board Layout for LinkSwitch-LP using P Package (Assumes a HVDC Input Stage).

LinkSwitch-LP Layout Considerations

DRAIN pin at turn off. This can be achieved by using an RCD
clamp or a Zener (~200 V) and diode clamp across the primary

Layout

See Figure 6 for a recommended circuit board layout for
LinkSwitch-LP (P & G package).

Single Point Grounding

Use a single point ground connection from the input fi lter
capacitor to the area of copper connected to the SOURCE pins.

winding. In all cases, to minimize EMI, care should be taken
to minimize the circuit path from the clamp components to the
transformer and LinkSwitch-LP.

Thermal Considerations

The copper area underneath the LinkSwitch-LP acts not only as
a single point ground, but also as a heatsink. As it is connected
to the quiet source node, this area should be maximized for

Bypass Capacitor (CBP)

The BYPASS pin capacitor should be located as near as possible

good heat sinking of LinkSwitch-LP. The same applies to the
cathode of the output diode.

to the BYPASS and SOURCE pins.

Y-Capacitor

Primary Loop Area

The area of the primary loop that connects the input fi lter
capacitor, transformer primary and LinkSwitch-LP together
should be kept as small as possible.

The placement of the Y-type cap should be directly from the
primary input fi lter capacitor positive terminal to the common/
return terminal of the transformer secondary. Such a placement
will route high magnitude common-mode surge currents away
from the LinkSwitch-LP device. Note: If an input pi (C, L, C)

Primary Clamp Circuit

An external clamp may be used to limit peak voltage on the

EMI fi lter is used, then the inductor in the fi lter should be placed
between the negative terminals on the input fi lter capacitors.

6

Rev. H 11/08

TOP VIEW

FB

BP

D

LinkSwitch-LP

S
S

S

S

LNK562-564

Input Filter

Capacitor

Transformer

Output Filter

Capacitor

Figure 7. Recommended Circuit Board Layout for LinkSwitch-LP using D Package (Assumes a HVDC Input Stage).

Output Diode

For best performance, the area of the loop connecting the
secondary winding, the output diode and the output fi lter
capacitor should be minimized. In addition, suffi cient copper
area should be provided at the anode and cathode terminals
of the diode for heat sinking. A larger area is preferred at the
quiet cathode terminal. A large anode area can increase high­frequency radiated EMI.

Y1-

Capacitor

+

DC

OUT

-

C

BP

HV DC

-

INPUT

Maximize hatched copper
areas ( ) for optimum
heatsinking

(overload) power, verify drain current waveforms for any
signs of transformer saturation and excessive leading-edge
current spikes at startup. Repeat under steady state conditions
and verify that the leading-edge current spike event is below
I

LIMIT(MIN)

at the end of the t

LEB(MIN)

maximum DRAIN current should be below the specifi ed
absolute maximum ratings.

3. Thermal Check – At specified maximum output
power, minimum input voltage and maximum ambient

Quick Design Checklist

temperature, verify that the temperature specifi cations
are not exceeded for LinkSwitch-LP, transformer, output

As with any power supply design, all LinkSwitch-LP designs
should be verifi ed on the bench to make sure that component
specifi cations are not exceeded under worst-case conditions. The
following minimum set of tests is strongly recommended:

diode and output capacitors. Enough thermal margin
should be allowed for part-to-part variation of the R
LinkSwitch-LP as specifi ed in the data sheet. Under low line
and maximum power, a maximum LinkSwitch-LP SOURCE pin
temperature of 100 °C is recommended to allow for

1. Maximum drain voltage – Verify that VDS does not exceed

these variations.

650 V at the highest input voltage and peak (overload) output
power. A 50 V margin to the 700 V BV

specifi cation gives

DSS

Design Tools

margin for design variation, especially in Clampless designs.

2. Maximum drain current – At maximum ambient
temperature, maximum input voltage and peak output

Up-to-date information on design tools can be found at the
Power Integrations web site: www.powerint.com.

+

PI-4582-021407

. Under all conditions, the

of

DS(ON)

7

Rev. H 11/08

LNK562-564

ABSOLUTE MAXIMUM RATINGS

DRAIN Voltage ..................................................700 V

Peak DRAIN Current...................................200 mA (375 mA)

Peak Negative Pulsed Drain Current (see Fig. 10) ... 100 mA

FEEDBACK Voltage .........................................-0.3 V to 9 V

FEEDBACK Current.............................................100 mA

BYPASS Voltage ..........................................-0.3 V to 9 V

Storage Temperature .......................................... -65 °C to 150 °C

(4)

Operating Junction Temperature
Lead Temperature

(5)

........................................................260 °C

..................... -40 °C to 150 °C

(2)

(3)

THERMAL IMPEDANCE

Thermal Impedance: P or G Package:

(θJA) ........................... 70 °C/W

(1)

(θJC)

............................................... 11 °C/W

D Package:

(θJA) ..................... .... 100 °C/W

(2)

(θJC)

............................................... 30 °C/W

(3)

; 60 °C/W

(3)

; 80 °C/W

(4)

(4)

Conditions

Parameter Symbol

SOURCE = 0 V; TJ = -40 to 125 °C

See Figure 8

(Unless Otherwise Specifi ed)

(1,6)

Notes:

1. All voltages referenced to SOURCE, TA = 25 °C.

2. The higher peak DRAIN current is allowed while the
DRAIN voltage is simultaneously less than 400 V.

3. Duration not to exceed 2 μs.

4. Normally limited by internal circuitry.

5. 1/16 in. from case for 5 seconds.

6. Maximum ratings specifi ed may be applied, one at a time,
without causing permanent damage to the product.
Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect product reliability.

Notes:

1. Measured on pin 2 (SOURCE) close to plastic interface.

2. Measured on pin 8 (SOURCE) close to plastic interface.

3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.

4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.

Min Typ Max Units

CONTROL FUNCTIONS

Output
Frequency

f

OSC

Ratio of Output
Frequency At Auto­Restart to f

OSC

f

OSC(AR)

Frequency Jitter
Maximum Duty

Cycle

DC

FEEDBACK Pin
Turnoff Threshold

I

Current
FEEDBACK Pin

Voltage at Turnoff

V

Threshold

I

DRAIN Supply
Current

I

FB

S1

S2

MAX

FB

TJ = 25 °C

VFB =1.69 V

TJ = 25 °C, VFB = V

Average

LNK562 61 66 71

LNK564 93 100 107

FB(AR)

48 %

Peak-Peak Jitter, TJ = 25 °C 5 %

S2 Open 66 70 %

TJ = 25 °C

See Note A

TJ = 0 to 125 °C

See Note A

56 70 84

1.60 1.69 1.78 V

VFB ≥ 2 V

(MOSFET Not Switching)

160 220

See Note B

FEEDBACK Open

(MOSFET Switching)

220 260

See Notes B, C

kHzLNK563 77 83 89

μA

μA

μA

8

Rev. H 11/08

Parameter Symbol

SOURCE = 0 V; TJ = -40 to 125 °C

CONTROL FUNCTIONS (cont.)

LNK562-564

Conditions

Min Typ Max Units

See Figure 8

(Unless Otherwise Specifi ed)

BYPASS Pin
Charge Current

BYPASS Pin
Voltage

BYPASS Pin
Voltage Hysteresis

BYPASS Pin
Supply Current

V

I

CIRCUIT PROTECTION

Current Limit

Power Coeffi cient

Leading Edge
Blanking Time

Thermal Shutdown
Temperature

I

CH1

I

CH2

V

BPH

BPSC

I

LIMIT

I2f

t

LEB

T

BP

SD

VBP = 0 V, TJ = 25 °C, See Note D -5.5 -3.3 -1.8

VBP = 4 V, TJ = 25 °C, See Note D -3.8 -2.3 -1.0

5.55 5.8 6.10 V

0.8 0.95 1.2 V

See Note E 84

di/dt = 40 mA/μs

TJ = 25 °C

LNK562 1099 1221 1380

di/dt = 40 mA/μs

TJ = 25 °C

LNK564 1665 1850 2091

TJ = 25 °C

See Note F

124 136 148 mA

220 265 ns

135 142 150

mA

μA

A2HzLNK563 1381 1535 1735

°C

Thermal Shutdown
Hysteresis

OUTPUT

ON-State
Resistance

OFF-State Drain
Leakage Current

Breakdown Voltage

DRAIN Supply
Voltage

Output Enable
Delay

Output Disable
Setup Time

T

R

BV

SHD

DS(ON)

I

DSS

DSS

t

EN

t

DST

See Note G 75

TJ = 25 °C

ID = 13 mA

TJ = 100 °C

VBP = 6.2 V, VFB ≥2 V, VDS = 560 V,

TJ = 25 °C

VBP = 6.2 V, VFB ≥2 V,

See Note H, TJ = 25 °C

See Figure 10 17

°C

48 55

76 88

50

700 V

50 V

0.5

μA

μs

μs

Ω

9

Rev. H 11/08

LNK562-564

Parameter Symbol

OUTPUT (cont.)

FEEDBACK Pin
Auto-Restart
Threshold Voltage

V

FB(AR)

Conditions

SOURCE = 0 V; TJ = -40 to 125 °C

See Figure 8

(Unless Otherwise Specifi ed)

TJ = 25 °C

Min Typ Max Units

0.8 V

Auto-Restart
ON-Time

Auto-Restart
Duty Cycle

DC

AR

VFB = V

FB(AR)

TJ = 25 °C

100 ms

12 %

NOTES:

A. In a scheme using a resistor divider network at the FB pin, where RU is the resistor from the FB pin to the rectifi ed

bias voltage and RL is the resistor from the FB pin to the SOURCE pin, the output voltage variation is infl uenced
by VFB and IFB variations. To determine the contribution from the VFB variation in percent, the following equation
can be used:

x = 100 #

J

V

K
K
K

K

V

L

FB(MAX)

FB(TYP)

R

L

RU+ R

cm

R

L

RU+ R

cm

L

+ I

FB(TYP)RU

L

+ I

FB(TYP)RU

-1

N
O
O
O

O
P

To determine the contribution from IFB variation in percent, the following equation can be used:

y = 100 #

J

V

K
K
K

K

V

L

RU+ R

cm

FB(TYP)

FB(TYP)

R

L

RU+ R

cm

R

L

L

+ I

FB(MAX)RU

L

+ I

FB(TYP)RU

Since IFB and VFB are independent parameters, the composite variation in percent would be .

-1

N
O
O
O

O
P

! x2+ y

2

B. Total current consumption is the sum of IS1 and I

switching) and the sum of IS2 and I

when FEEDBACK pin is shorted to SOURCE (MOSFET switching).

DSS

when FEEDBACK pin voltage is ≥2 V (MOSFET not

DSS

C Since the output MOSFET is switching, it is diffi cult to isolate the switching current from the supply current at the
DRAIN. An alternative is to measure the BYPASS pin current at 6 V.

D. See Typical Performance Characteristics section Figure 16 for BYPASS pin startup charging waveform.

E. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK

pins and not any other external circuitry.

F. This parameter is guaranteed by design.

G. This parameter is derived from characterization.

H. Breakdown voltage may be checked against minimum BV

exceeding minimum BV

DSS

.

by ramping the DRAIN pin voltage up to but not

DSS

10

Rev. H 11/08

LNK562-564

Figure 8. General Test Circuit.

S1

470 Ω

5 W

FB

D

BP

S

S

SS

DC

MAX

470 kΩ

0.1 μF

S2

50 V50 V

PI-3490-060204

(internal signal)

t

P

FB

t

V

DRAIN

tP =

f

1

OSC

EN

PI-3707-112503

Figure 9. Duty Cycle Measurement.

Figure 10. Output Enable Timing.

100

2 μs

0

-100

DRAIN Current (mA)

Time (μs)

Figure 11. Peak Negative Pulsed DRAIN Current
Waveform.

PI-4021-101305

11

Rev. H 11/08

LNK562-564

1.1

1.0

0.9

-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

Breakdown Voltage

(Normalized to 25 °C)

PI-2213-012301

Typical Performance Characteristics

1.2

Figure 12. Breakdown vs. Temperature.

1.4

1.2

1.0

0.8

0.6

Current Limit

0.4

(Normalized to 25 °C)

0.2

PI-4164-100505

1.0

0.8

0.6

0.4

Output Frequency

(Normalized to 25 °C)

0.2

0

-50 -25 0 25 50 75 100 125

Junction Temperature (°C)

Figure 13. Frequency vs. Temperature.

1.1

1.0

(Normalized to 25 °C)

FEEDBACK Pin Voltage

PI-2680-012301

PI-4057-071905

0

-50 0 50 100 150

Figure 14. Current Limit vs. Temperature.

7

6

5

4

3

2

1

BYPASS Pin Voltage (V)

0

0 0.2 0.4 0.6 0.8 1.0

Figure 16. BYPASS Pin Startup Waveform.

12

Rev. H 11/08

Temperature (°C)

Time (ms)

PI-2240-012301

0.9

-50 -25 0 25 50 75 100 125 150

Temperature (°C)

Figure 15. FEEDBACK Pin Voltage vs. Temperature.

200

175

150

125

100

75

50

DRAIN Current (mA)

25

0

0

25 °C

100 °C

4286 101214161820

DRAIN Voltage (V)

Figure 17. Output Characteristics.

PI-3927-083104

Drain Voltage (V)

Drain Capacitance (pF)

PI-3928-083104

0 100 200 300 400 500 600

1

10

100

1000

Typical Performance Characteristics (cont.)

LNK562-564

Figure 18. C

PART ORDERING INFORMATION

LNK 562 D N - TL

vs. Drain Voltage.

OSS

LinkSwitch Product Family

LP Series Number

Package Identifi er

G Plastic Surface Mount DIP

P Plastic DIP

D Plastic SO-8

Lead Finish

N Pure Matte Tin (RoHS Compliant)

RoHS Compliant and Halogen Free (P and D Package

G

only)

Tape & Reel and Other Options

Blank Standard Confi gurations

Tape & Reel, 1 k pcs minimum for G Package. 2.5 k pcs

TL

for D Package. Not available for P Package.

13

Rev. H 11/08

LNK562-564

-E-

.240 (6.10)
.260 (6.60)

Pin 1

-D-

.125 (3.18)
.145 (3.68)

-T-

SEATING
PLANE

.100 (2.54) BSC

D S

⊕

.367 (9.32)
.387 (9.83)

.014 (.36)
.022 (.56)

.004 (.10)

T E D S

⊕

.137 (3.48)
MINIMUM

.048 (1.22)
.053 (1.35)

.010 (.25) M

.057 (1.45)
.068 (1.73)

(NOTE 6)

.015 (.38)
MINIMUM

.120 (3.05)
.140 (3.56)

DIP-8B

Notes:

1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.

2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.

3. Dimensions shown do not include mold flash or other
protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.

4. Pin locations start with Pin 1, and continue counter-clock­ wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 6 is omitted.

5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).

6. Lead width measured at package body.

7. Lead spacing measured with the leads constrained to be
perpendicular to plane T.

.008 (.20)
.015 (.38)

.300 (7.62) BSC

(NOTE 7)

.300 (7.62)
.390 (9.91)

P08B

PI-2551-121504

-E-

.240 (6.10)
.260 (6.60)

Pin 1

-D-

.125 (3.18)
.145 (3.68)

.032 (.81)
.037 (.94)

D S

.004 (.10)

⊕

.100 (2.54) (BSC)

.367 (9.32)
.387 (9.83)

.048 (1.22)
.053 (1.35)

.137 (3.48)
MINIMUM

.372 (9.45)
.388 (9.86)

E S

⊕

.057 (1.45)
.068 (1.73)

(NOTE 5)

.009 (.23)

.010 (.25)

SMD-8B

Pin 1

.004 (.10)
.012 (.30)

.046

.086

.060

.186

.060

.286

Solder Pad Dimensions

.004 (.10)

.036 (0.91)
.044 (1.12)

.046

.080

Notes:

1. Controlling dimensions are
inches. Millimeter sizes are
shown in parentheses.

2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
protrusions shall not exceed
.006 (.15) on any side.

.420

3. Pin locations start with Pin 1,
and continue counter-clock­ wise to Pin 8 when viewed
from the top. Pin 6 is omitted.

4. Minimum metal to metal
spacing at the package body
for the omitted lead location
is .137 inch (3.48 mm).

5. Lead width measured at
package body.

6. D and E are referenced
datums on the package
body.

°

°

8

0 -

PI-2546-121504

G08B

14

Rev. H 11/08

SO-8C

LNK562-564

0.10 (0.004)

2X

1.35 (0.053)

1.75 (0.069)

0.10 (0.004)

0.25 (0.010)

3.90 (0.154) BSC

2

D

C

Pin 1 ID

1.27 (0.050) BSC

B

4

1.25 - 1.65

(0.049 - 0.065)

2

4.90 (0.193) BSC

A

8

1

4

5

4

0.10 (0.004)

A-B

2X

C

D

6.00 (0.236) BSC

0.20 (0.008)

2X

7X 0.31 - 0.51 (0.012 - 0.020)

0.25 (0.010)

0.10 (0.004)

7X

SEATING PLANE

C

M

C A-B D

C

C

SEATING
PLANE

1.04 (0.041) REF

C

0.40 (0.016)

1.27 (0.050)

H

0.17 (0.007)

0.25 (0.010)

DETAIL A

o

0 - 8

0.25 (0.010)
BSC

DETAIL A

GAUGE
PLANE

Reference
Solder Pad
Dimensions

+

Notes:

1. JEDEC reference: MS-012.

2.00 (0.079)

4.90 (0.193)

2. Package outline exclusive of mold flash and metal burr.

3. Package outline inclusive of plating thickness.

4. Datums A and B to be determined at datum plane H.

5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.

PI-4526-040207

D07C

1.27 (0.050)

+

+

+

0.60 (0.024)

Revision Notes Date

E 1) Final Release Data Sheet 10/05

F 1) Revision of PI-3924 10/05

G 1) Added SO-8C Package 2/07

H 1) Updated Part Ordering Information section with Halogen Free 11/08

15

Rev. H 11/08

LNK562-564

For the latest updates, visit our website: www.powerint.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANT Y HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information

The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A
complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.powerint.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1.

A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifi cant
injury or death to the user.

2.

A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert
and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
©2007, Power Integrations, Inc.

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16

Rev. H 11/08