Datasheet LND-TRM33 Datasheet (Linear Dimensions)

Page 1

General Description

The LND TRM33 is a low power Amplitude Shift Keying (ASK) transmitter designed to operate at transmit frequencies between 300 and 500MHz. It is comprised of a frequency synthesizer and modulator, which accepts a simple CMOS digital data input and generates an ASK modulated output. Output power can be adjusted to a maximum of 2dBm. The LND TRM33 has been optimized for use in batterypowered applications with low current consumption in both transmit and standby modes.

DATA SHEET

Applications

• Wireless office and home

security systems

• Automotive remote locking/starting

• Consumer remote control units

• Radio data transmission

• Low power telemetry

Features

• Low current consumption in

transmit mode

• Low standby current

(typically a few nA)

• Conforms to requirements of

ETSI-300-220, PT1340 and FCC Part 15

• Easy to use with low external

component count and cost

• No discrete external inductors

required

• Adjustable output power level

LND TRM33

LOW POWER 300 TO 500 MHz ASK TRANSMITTER

How Does it Work

Simply connect the supply (as low as 2.6V), an external oscillator to RO1 and RO2, and all ground connections. The chip converts logic level inputs to balanced, complimentary, amplitude modulated outputs, Out1 and Out 2. Output power can be adjusted using resistor values in Table 5, and can be easily switched with logic input to Standby Mode (extremely low power) when not transmitting. Component selections, network, and antenna options are included in this document.

VCC VEE1 VEE2 VSUB

PS OUT2

OUT1

DATA

VEE

RO2

RO1

BYPS

SBY

divide-

by64

buffer

crystal oscillator

charge

pump

phase

detector

VCO

ASK

modulator

P.A.

Figure 1: Block Diagram

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LND TRM33

LOW POWER 300 TO 500 MHz ASK TRANSMITTER

Table 3: DC Characteristics at 3.0V VCC and 23ºC ambient temperature all parameters 100% production tested under these conditions unless otherwise stated

Parameter Conditions Symbol Min Typ Max Unit Standby Current SBY = low Iccstb 0.1 1 µA Supply Current DATA = low Icclow 16.5 mA Supply Current DATA = high, including open-collector

output currents

Icchigh 25 mA

DATA logic high level guaranteed by design Vhigh 0.7*VCC VCC+0.3V DATA logic low level guaranteed by design Vlow -0.3V 0.3*VCC DATA input current guaranteed by design

-0.3 < Vin < Vcc+0.3

Idata -10 +10 µA

Bias voltage on pin PS guaranteed by design

I(PS) = 100 µA

V(PS) 0.4 V

Table 2: Operating conditions @ 434 MHz; @ 318 MHz

Parameter Symbol Min Max Unit Supply voltage VCC 2.6 4.8 V Ambient temperature Ta -40 65 °C Note:

All specification parameters

uaranteed only with the following components

(please refer to fi

ure 2 for application circuit):

RF transformer Crystal

Mini-Circuits TC4-14 Euroquartz B537 6.78-MHz crystal (Cload = 10 pF) R1 = 3.9 k R2 = 3.3 k C7 = 1 nF C8 = 47 pF C1 = C2 = 22 pF

Table 1: Absolute maximum ratings Parameter Conditions Symbol Min Max Unit Supply voltage VCC -0.3 +7.0 V Input voltage - Logic Inputs DATA & SBY pins -0.3V VCC + 0.3V Input Current DATA & SBY pins -1.0 +1.0 mA Storage temperature -40 150 °C Junction temperature -40 150 °C Power Dissipation (SO16) 200 mW

Theory of operation

The LND TRM33 comprises three main elements: 1 Input buffer and modulator 2 Frequency synthesizer for generation of the RF

output carrier from a low frequency external

crystal 3 Power amplifier (PA) for driving an external

antenna

The IC accepts a digital CMOS input, and modu-

lates a fixed RF carrier frequency on or off

according to the digital input level. The RF carrier

is generated by the on-chip phase locked loop

(PLL) frequency synthesizer. This contains a

fixed divider which ensures that the RF output

frequency is 64 times the crystal reference

frequency. The power amplifier provides a variable output level of up to 2 dBm of output power depending upon the value of an external resistor R1.

The PA has balanced outputsOUT1 and OUT2 which are in open collector configuration. A balanced output is used since it provides a high degree of suppression of even-order harmonics of the fundamental. Odd order harmonic suppression is achieved using on-chip cancellation techniques.

Electrical characteristics

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LND TRM33

LOW POWER 300 TO 500 MHz ASK TRANSMITTER

Table 4: AC Characteristics at 3.0V VCC and 23ºC ambient temperature, fc = 433.92 MHz, unless otherwise stated all parameters 100 % production tested under these conditions unless otherwise stated

Parameter Conditions Symbol Min Typ Max Unit Maximum Carrier Frequency fcmax 440 MHz

Minimum Carrier Frequency fcmin 290 MHz Maximum Data Rate received BER<1% with receiver

pre-detection bandwidth matched to data rate

Rmfsk 200 kbits/s

Extinction Ratio R=1.5 kbit/s M 50 dB Reference Frequency

uaranteed by design,

external crystal

fref 4.5 7.0 MHz

Output Power with R1=3.9 kOhms Po 0.5 dBm 2nd Harmonic P2 -34 -29 dBc 3rd Harmonic P3 -35 -28 dBc Reference Spurious at fc + (fref to 3fref) Pref -45 -40 dBc

Phase Noise

uaranteed by design,

at 10 kHz offset

PN -75 dBc/Hz

VCOgain

uaranteed by design KVCO 125 MHz/V

Phase detectorgain

uaranteed by design KPD 16 µA/rad

Electrical characteristics (continued)

Matching network and antenna options

Figure 2: Application Diagram

Figure 2 shows a typical application diagram.

In order to minimise second harmonic distortion, a differential output configuration is recommended.

OP1

VCC

50 Ohms

VEE1

SBY

DATA

VEE2

N/C

RO1

RO2

VSUB

VCC

BYPS

VEE

OP21

SBY

DATA

1+1:1

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LND TRM33

LOW POWER 300 TO 500 MHz ASK TRANSMITTER

Table 5: Output Power Settings

(kOhms)

Output power

(dBm)

Current cons.

(mA)

2.8 2 25

3.8 0 22

5.2 -2 20

6.7 -4 19

8.5 -6 18

9.7 -8 17

10.3 -10 16

10.7 -12 16

Table 6: Recommended External Components

Component Function Value Tolerance Units

C1 Crystal Oscillator 22 ± 5% pF C2 Crystal Oscillator 22 ± 5% pF C5 Supply Decoupling 100 ± 20% nF C6 Regulator Decoupling 100 ± 20% nF C7 PLL Loop Filter 1 ± 5% nF C8 PLL Loop Filter 47 ± 5% pF R1 O/P power set 3.9 ± 5% kOhms R2 PLL Loop Filter 3.3 ± 5% kOhms X1 Crystal 6.78 < 20ppm MHz

Note: Recommended Crystal Oscillator type: B537

Table 7: I/O interfacing

No. Signal Description

1 OP1 PA Output 2 VEE1 Ground (0V) 3 PS Power Set 4 SBY Standby (complete power down) 5 DATA Data 6 VEE2 Ground (0V) 7 N/C Not connected 8 RO1 Reference Oscillator (emitter)

9 RO2 Reference Oscillator (base) 10 VSUB Substrate Connection (0V) 11 VCC Supply (Battery) 12 BYPS Power supply decoupling to ground 13 LF Low Pass Filter 15 VEE Ground (0V) 16 OP2 PA Output (complement)

The LND TRM33 needs the following:

1) a dc bias reference to VCC (for instance through use of printed bias inductors with a connection to VCC, or direct connection of a loop antenna connected to VCC at its centre). Linear’s TRM3x series of evaluation boards provide large and small loop antenna solutions for customers to copy. These boards require a minimum number of external components, and importantly no discrete inductors are required. For driving an external single-ended antenna, a high-efficiency printed balun is also available.

For optimum operation, the following points are highlighted:

1) the IC can provide 7.5mA of current into the load

2) for maximum output power, it is recommended that the antenna load be transformed to an impedance of 200Ohms

3) a PLL synthesizer is designed to operate with an external second order loop filter as shown in figure 2, with component values as shown in Table 6. These values determine the loop bandwidth and dynamics and operation of the loop is not guaranteed for any other values

4) the bias current for the power amplifier directly controls the output current and hence the O/P power. This bias current is set by an external resistor connected between PS and ground. Output power versus R1 values is shown in Table 5, for a differential load impedance of 200Ω.

Matching network and antenna options (continued)

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LND TRM33

LOW POWER 300 TO 500 MHz ASK TRANSMITTER

from modulator

400 mV

+VCC OP1 OP2

∅ = 7.5 mA

+ VCC

LF1

+ VCC

DATA SBY

+ VCC

25kΩ

RO2

RO1

P.A.

VBIAS

Input and output interface diagrams

Figure 3: Input and output interface diagrams

Pinout Information

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LND TRM34

LOW POWER 300 TO 500 MHz FSK TRANSMITTER

OP1

VEE1

SBY

DATA

VEE2

N/C

RO1

SOP 16 / SSOP 16

RO2

VSUB

VCC

BYPS

VEE

OP2

5 6

7 89

Package Information