Datasheet LNBP21 Datasheet (ST)

LNBP21

LNBP SUPPLY AND CONTROL IC WITH

STEP-UP CONVERTER AND I

■ COMPLETE INTERFACE BETWEEN LNB

■ BUILT-IN DC/DC CONTROLLER FOR

■ ACCURATE BUILT-IN 22KHz TONE

■ SUITS WIDELY ACCEPTED STANDARDS

■ FAST OSCILLATOR START -U P F ACILITA TES

■ BUIL T-IN 22KHz TONE DETECTOR

■ LOOP-THROUGH FUNCTION FOR SLAVE

■ LNB SHORT CIRCUIT PROTECTION AND

■ CABLE LENGTH DIGITAL COMPENSATION

■ INTERNAL OVER TEMPERATURE

■ ESD RATING 4KV ON POWER

2CTM

AND I

BUS
SINGLE 12V SUPPLY OPERATION
OSCILLATOR

DiSEqC

TM

ENCODING
SUPPORTS BI-DIRECTIONAL DiSEqC
OPERATION
DIAGNOSTIC

PROTECTION
INPUT-OUTPUT PINS

TM

2

C INTERFACE

SO-20PowerSO-20

DESCRIPTION

Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBP21 is a
monolithic voltage regulator and interface IC,
assembled in SO-20 and PowerSO-20,
specifically designed to provide the power and the
13/18V, 22KHz t one signalling to the LNB down
converter in the antenna or to the multiswitch box.
In this application field, it offers a complete
solution with extremely low co mpo nent c ount, low

Figure 1: Block Diagram

Gate

Sense

Vup

Vcc

Byp

SDA
SCL

ADDR

DSQIN

Preregul.+

U.V.lockout

+P.ON res.

I²C
interf.

Step-up

Controller

LNBP21

Feedback

Enable
I Select
V Sele ct

Linear Post-reg

+Modulator

+Protections

22KHz
Oscill.

Diagnostics

Tone

Detector

LT1

LT2

OUT

EXTM

DETIN

DSQOUT

Rev. 3

1/24October 2004

LNBP21

power dissipation together with simple design and

2CTM

I

standard interfacing.
This IC has a built in DC/DC step-up controller
that, from a single supply source ranging from 8 to
15V, generates the voltages that let the linear
post-regulator to work at a minimum dissipated
power. An UnderVoltage Lockout circuit will
disable the whole circuit when th e supplied V

CC

drops below a fixed threshold (6.7V typically). The
internal 22KHz tone generator is factory trimmed
in accordance to the standards, and can be
controlled either by the I
dedicated pin (DSQIN) that allows immediate
DiSEqC

TM

data encoding (*). A ll the functions of

this IC are controlled via I

2CTM

interface or by a

2CTM

bus by writing 6
bits on the System Register (SR, 8 bits). The
same register can be read back, a nd two bits will
report the diagnostic status. When the IC is put in
Stand-by (EN bit LOW), the power blocks are
disabled and the loop-through switch between
LT1 and LT2 pins is closed, thus leaving all LNB
powering and control functions to the Master
Receiver (**). When the regulator blocks are
active (EN bit HIGH), the output can be logic
controlled to be 13 or 18 V (typ.) by mean of the
VSEL bit (Voltage SELect) for remote controlling
of non-DiSEqC LNBs. Additionally, it is possible to
increment by 1V (typ.) the sel ected vol tage value
to compensate for the ex cess voltage drop along
the coaxial cable (LLC bit HIGH). In order to
minimize the power dissipation, the output voltage
of the internal step-up converter is adjusted to
allow the linear regulator to work at minimum
dropout. Another bit of the SR is addressed to the
remote control of non-DiSEqC LNBs: the TEN
(Tone ENable) bit. When it is set to HIGH, a
continuous 22KHz tone is generated regardless of
the DSQIN pin logic status. The TEN bi t must be
set LOW when the DSQIN pin is used for
DiSEqC
DiSEqC
22KHz tone detector. Its input pin (DETIN) must
be AC coupled to the DiSEqC

TM

encoding. The fully bidirectional

TM

interfacing is completed b y the bui lt-in

TM

bus, and the
extracted PWK data are available on the
DSQOUT pin (*).
In order to improve design flexibility and to allow
implementation of newcoming LNB remote control
standards, an analogic modulation input pin is
available (EXTM). An appropriate DC blocking
capacitor must be used to couple the modulating
signal source to the EXTM pin. When external

(*): External components are needed to comply to bi-di rectional Di S EqCTM bus hard ware requir em ents. Full complian ce of the whole appl i ­cation to DiSEqCTM specificat i ons is not imp l i ed by the use of th i s I C.
(**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must be
externally limited.

modulation is not used, the relevant pin can be left
open.

The current limitation block has two thresholds
that can be selected by the I

bit of the SR; the

SEL

lower threshold is between 400 and 550mA
(I

=HIGH), while the higher threshold is

SEL

between 500 and 650mA (I

SEL

=LOW).

The current protection block is SOA type. This
limits the short circuit current (I
200mA with I
I

=LOW when the output port is connected to

SEL

=HIGH and at 300mA with

SEL

) typically at

SC

ground.
It is possible to set the Short Circuit Current

protection either statically (simple current clam p)
or dynamically by the PCL bit of the SR; when the
PCL (Pulsed Current Limiting) bit is set to LOW,
the overcurrent protection circuit works
dynamically: as soon as an overloa d is detected,
the output is shut-down for a time t

, typically

off

900ms. Simultaneously th e OLF bit of the System
Register is set to HIGH. After this time has
elapsed, the output is resumed for a time t
10t

(typ.). At the end of ton, if the overload is still

off

on

=1/

detected, the protection circuit will cycle again
through T

and Ton. At the end of a full Ton in

off

which no overload is detected, normal operation is
resumed and the OLF bit is reset to LOW. Typical
T

time is 990ms and it is determined by an

on+Toff

internal timer. This d yn amic operat ion can greatly
reduce the power dissipation in short circuit
condition, still ensuring excellent power-on start
up in most conditions (**).

However, there could be some cases in which an
highly capacitive load on the output may cause a
difficult start-up when the dynamic protection is
chosen. This can be solved by initiating any power
start-up in static mode (PCL=HIGH) and then
switching to the dynamic m ode (PCL=LO W) a fter
a chosen am ount of time. When in static m ode,
the OLF bit goes HIGH when the current clamp
limit is reached and returns LOW when the
overload condition is cleared.

This IC is also protected against overheating:
when the junction temperature exceeds 150°C
(typ.), the step-up converter and the linear
regulator are shut off, the loop-trough switch is
opened, and the OTF bit of the SR is set to HIGH.
Normal operation is resum ed and the OTF bit is
reset to LOW when the junction is cooled down to
140°C (typ.).

2/24

Table 1: Ordering Codes

LNBP21

TYPE

SO-20

(Tube)

SO-20

(Tape & Reel)

PowerSO-20

(Tube)

PowerSO-20

(Tape & Reel)

LNBP21 LNBP21D2 LNBP21D2-TR LNBP21PD LNBP21PD-TR

Table 2: Absolute Maximum Ratings

Symbol Parameter Value Unit

V
V

V

LT1

I

V

V

V

DETIN

V

I

V

I

GATE

V

SENSE

V

ADDRESS

T
T

DC Input Voltage

CC

DC Input Voltage

UP

, V

DC Input Voltage

LT2

Output Current

O

DC Output Pin Voltage

O

Logic Input Voltage (SDA, SCL, DSQIN)

I

Detector Input Signal Amplitude
Logic High Output Voltage (DSQOUT)

OH

Bypass Switch ON Current

LT

Bypass Switch OFF Voltage

LT

Gate Current
Current Sense Voltage
Address Pin Voltage
Storage Temperature Range

stg

Operating Junction Temperature Range

op

16 V
25 V
20 V

Internally Limited mA

-0.3 to 22 V

-0.3 to 7 V
2
7V

900 mA
±20 V

±400 mA

-0.3 to 1 V

-0.3 to 7 V

-40 to +150 °C

-40 to +125 °C

V

PP

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.

Table 3: Thermal Data

Symbol Parameter SO-20 PowerSO-20 Unit

R

thj-case

Thermal Resistance Junction-case

15 2 °C/W

Figure 2: Pin Conf i guration (top view)

SO-20

PowerSO-20

3/24

LNBP21

Table 4: Pin Description

PIN NUMBER

SYMBOL NAME FUNCTION

V

Supply Input 8V to 15V supply. A 220µF bypass capacitor to

CC

GND with a 470nF (ceramic) in parallel is
recommended

GATE External Switch Gate External MOS switch Gate connection of the

step-up converter

SENSE Current Sense Input Current Sense comparator input. Connected to

current sensing resistor

V

Step-up Voltage Input of the linear post-regulator. The voltage on this

up

pin is monitored by internal step-ut controller to
keep a minimum dropout across the linear pass
transistor

OUT Output Port Output of the linear post regulator modulator to the

LNB. See truth table for voltage selections.

SDA Serial Data

SCL Serial Clock

Bidirectional data from/to I
Clock from I

2

C bus.

2

C bus.

DSQIN DiSEqC Input When the TEN bit of the System Register is LOW,

this pin will accept the DiSEqC code from the main
µcontroller. The LNBP21 will use this code to
modulate the internally generated 22kHz carrier. Set
to GND this pin if not used.

DETIN Detector In 22kHz Tone Detector Input. Must be AC coupled to

the DiSEqC bus.

DSQOUT DiSEqC Output Open collector output of the tone Detector to the

main µcontroller for DiSEqC data decoding. It is
LOW when tone is detected.

EXTM External Modulator External Modulation Input. Need DC decoupling to

the AC source. If not used, can be left open.
GND Ground Pins to be connected to ground. 5, 6, 15, 16 1, 6, 10, 11, 20
BYP Bypass Capacitor Needed for internal pre regulator filtering 8 8

LT1 Loop Through Switch In standby mode the power switch between L T1 and

LT2 is closed. Max allowed current is 900mA. this

pin can be left open if loopthrough function is not

needed.

LT2 Loop Through Switch Same as above 2 3

ADDR Address Setting

2

C bus addresses available by setting the

Four I

Address Pin level voltage

vs. PAC KAG E

SO-20 PowerSO-20

19 18

17 17

14 16

20 19

12

11 12
12 13
13 14

99

10 15

45

34

77

4/24

Figure 3: Typical Applica t i on Circuit

C3

C3

C3

C3
470nF

470nF

470nF

470nF

Ceramic

Ceramic

Ceramic

Ceramic

C4

C4

C4

C4
470nF

470nF

470nF

470nF

Ceramic

Ceramic

Ceramic

Ceramic

IC2

IC2

(Note 3)

(Note 3)

L1=22µH

L1=22µH

Vin

Vin

12V

12V

C2

C2
220µF

220µF

STS4DNFS30L

STS4DNFS30L

STS4DNFS30L

STS4DNFS30L

sc

sc

sc

sc

R

R

R

R

ΩΩΩΩ

ΩΩΩΩ

ΩΩΩΩ

ΩΩΩΩ

0.1

0.1

0.1

0.1

(Note 4)

(Note 4)

C1

C1

C1

C1
220µF

220µF

220µF

220µF

IC1

IC1

Vup

Vup

Gate

Gate

Sense

Sense

Vcc

Vcc

DSQIN(Note 1)

DSQIN(Note 1)
SCL

SCL
SDA

SDA

D1 1N4001

D1 1N4001

D1 1N4001

D1 1N4001

LNBP21

LNBP21

GND

GND

LT1

LT1

LT2

LT2

Vo

Vo

DETIN

DETIN
(Note 1)

(Note 1)

Byp

Byp

EXTM

EXTM

ADDRESS

ADDRESS

DSQOUT

DSQOUT

C8

C8
10nF

10nF

C6

C6
10nF

10nF

C5

C5
470nF

470nF

C7

C7

C7

C7
10nF

10nF

10nF

10nF

D2

D2

D2

D2
BAT43

BAT43

BAT43

BAT43

Master S TB

Master S TB

270µH

270µH

15 ohm

15 ohm

see Note 2

see Note 2

0<Vaddr<V

0<Vaddr<V

Byp

Byp

LNBP21

to LNB

to LNB

(*) Set to GND if not used
(**) fil ter to be used according to EUTELSAT re c o m m endation to implemen t t h e Di S E q CTM 2.x, not needed if bidirec tional DiSEqCTM 2.x is
not impl em ented (see Di S EqC implem entation not e)
(***) IC2 is a ST Fettky, STS4DNFS30L, that includes both the schottky diode and the N-Channel MosFet, needed for the DC/DC converter,

in a So-8 pa ckage. It ca n be replaced b y a schottky di ode (STPS2L3A or similar) and a N-Channel MosFet (STN4 NF 03L or similar)

I2C BUS INTERFACE

Data transmission from main µP to the LNBP21
and viceversa takes place through the 2 wires I2C
bus interface, consisting of the two lines SDA and
SCL (pull-up resistors to positive supply voltage
must be externally connected).

DATA VALIDITY

As shown in fig. 3, the data on the SDA line must
be stable during the h igh period of t he clock. T he
HIGH and LOW state of the data line can only
change when the c lock signal on the SCL line is
LOW.

ACKNOWLEDGE

The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 4). The peripheral (LNBP21) that
acknowledges has to pull-down (LOW) the SDA
line during the ack nowledge clock pulse, so that
the SDA line is stable LOW during this clock pulse.
The peripheral which has been addressed has to
generate an acknowledge after the reception of
each byte, other-wise the SDA line remains at the
HIGH level during the ninth clock pulse time. In
this case the master transm itter can generate t he
STOP information in order to abort the transfer.

START AND STOP CONDITIONS

As shown in fig. 4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.

The LNBP21 won't generate the acknowledge if
the V

supply is below the Undervoltage Lockout

CC

threshold (6.7V typ.).
The stop condition is a LOW to HI GH t ransition of
the SDA line while SCL is HIGH. A STOP
conditions must be sent before each START
condition.

TRANSMISSION WITHOUT ACKNOWLEDGE

Avoiding to detect the acknowledge of the

LNBP21, the µP can use a simpler transmission:

BYTE FORMAT

Every byte transferred to the SDA line must
contain 8 bits. Eac h byte must be follo wed by an
ac-knowledge bit. The MSB is transferred first.

simply it waits one clock without checking the

slave acknowledging, and sends the new data.

This approach of course is less protected from

misworking and decreases the noise immunity.

5/24

LNBP21

Figure 4: Data Validity On The I2C BUS

2

Figure 5: Timi ng Diagram On I

C Bus

Figure 6: Acknowledge On I

6/24

2

C Bus

LNBP1 SOFTWARE DESCRIPTION

LNBP21

INTERFACE PROTOCOL

The interface protocol comprises:

- A start condition (S)

CHIP ADDRESS DATA

MSB LSB MSB LSB

S0001000R/WACK ACKP

ACK= Acknowledge
S= Start
P= Stop
R/W= Read/Write

- A chip address byte = hex 10 / 11 (the LSB bit

determines read(=1)/write(=0) transmission)

- A sequence of data (1 byte + acknowledge)

- A stop condition (P)

SYSTEM REGISTER (SR, 1 BYTE)

MSB LSB
R, W R, W R, W R, W R, W R, W R R

PCL ISEL TEN LLC VSEL EN OTF OLF

R,W= read and write bit
R= Read-only bit
All bits reset to 0 at Power-On

TRANSMITTED DATA (I2C BUS WRITE MODE)

When the R/W bit in the chip addres s is set to 0,
the main µP can write on the System Register
(SR) of the LNBP21 via I

2

C bus. Only 6 bits out of

the 8 available can be written by the µP, since the

remaining 2 are left to the diagnostic flags, and are

read-only.

PCL ISEL TEN LLC VSEL EN OTF OLF Function

=13V, VUP=16V Loopthrough switch open

001XX
011XX
101XX

111XX
0 1 X X 22KHz tone is controlled by DSQIN pin
1 1 X X 22KHz tone is ON, DSQIN pin disabled

01XX

11XX
0 1 X X Pulsed (dynamic) current limiting is selected
1 1 X X Static current limiting is selected

XXXXX0XXPower blocks disabled, Loopthrough switch closed

X= don't care.
Values are typical unl ess otherwi se specified

RECEIVED DATA (I2C bus READ MODE)

The LNBP21 c an provide to th e Master a copy of
the SYSTEM R EGISTER inform ation via I

2

C bus
in read mode. The read mode is Master activated
by sending the chip address with R/W bit set to 1.
At the following master generate d clocks bits, the
LNBP21 issues a byte on the SDA da ta bus line
(MSB transmitted first).
At the ninth clock bit the MCU master can:

V

OUT

=18V, VUP=21V Loopthrough switch open

V

OUT

=14V, VUP=17V Loopthrough switch open

V

OUT

V

=19V, VUP=22V Loopthrough switch open

OUT

I

OUT(min)

I

OUT(min)

=500mA, I
=400mA, I

OUT(max)
OUT(max)

=650mA ISC=300mA
=550mA ISC=300mA

- acknowledge the reception, starting in this way
the transmission of another byte from the
LNBP21;

- no acknowledge, stopping the read mode
communication.

While the whole register is read back by the µP,
only the two read-only bi ts OLF and OTF conv ey
diagnostic informations about the LNBP21.

7/24

LNBP21

PCL ISEL TEN LLC VSEL EN OTF OLF Function

TJ<140°C, normal operation

>150°C, power block disabled, Loopthrough switch open

T

J

0
1

I

OUT<IOMAX

I

OUT>IOMAX

, normal operation
, overload protection triggered

These bits are read exactly the same as

they were left after last write operation

Values are typical unl ess otherwi se specified

0
1

POWER-ON I2C INTERFACE RESET

2

The I

C interface built in the LNBP21 is
automatically reset at power-on. As long as the
V

stays be-low the UnderVoltage Lockout

CC

threshold (6.7V typ.), the interface will not respond
to any I

2

C command and the System Register
(SR) is in itialized to all zeroe s, thus keeping the
power blocks disabled. Once the V

7.3V, the I

2

C interface becomes operative and the

rises above

CC

SR can be configured by the main µP. This is due
to About 500mV of hysteresis provided in the UVL
threshold to avoid false retriggering of the
Power-On reset circuit.

DiSEqC

TM

IMPLEMENTATION

The LNBP21 helps the system designer to
implement the bidirectional (2.x) DiSEqC protocol
by allowing an easy PWK modulation/
demodulation of the 22KHz carrier. The PWK data
are exchanged between the LNBP21 and the
main µP using logic levels that are compatible with
both 3.3 and 5V microcontrollers. This data
exchange is made through two dedicated pins,
DSQIN and DSQOUT, in order to maintain the
timing relationships between the PWK data and
the PWK modulation as accurate as possible.
These two pins should be directly connected to
two I/O pins of the µP, thus leaving to the resident
firmware the task of e ncoding and decoding the

PWK data in accordance t o the DiSEqC protocol.
Full compliance of the s ystem to the s pecification
is thus not implied by the bare use of the LNBP21.

The system designer should also take in
consideration the bus hardware requirements,
that include the source impedance of the Master
Transmitter measured at 22KHz. To limit the
attenuation at carrier frequency, this impedance
has to be 15ohm at 22K Hz, d ropping to zero ohm
at DC to allow the power flow towards the
peripherals. This can be simply accomplished by
the LR termination put on the OUT pin of the
LNBP, as sh own i n the T y pical Application Circuit
on page 5.

Unidirectional (1.x) DiSEqC and non-DiSEqC
systems normally don't need this termination, and
the OUT pin can be directly connected to the LNB
supply port of the Tune r. There is also no need of
Tone Decoding, thus, it is recommended to
connect the DETIN and DS QOUT pins to ground
to avoid EMI.

ADDRESS PIN

Connecting this pin to GND the Chip I

2

C interface
address is 0001000, but, it is possib le to choice
among 4 different addresses simply setting this
pin at 4 fixed voltage levels (see table on page

10).

8/24

LNBP21

Table 5: Electrical Characteristics For LNBP Series (TJ = 0 to 85°C, EN=1, LLC=0, TEN=0, ISEL=0,

PCL=0, DSQIN=0, V

2

for I

C access to the system register)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

Supply Voltage IO = 500 mA TEN=VSEL=LLC=1 8 15 V

IN

LT1 Input Voltage 20 V

V

LT1

Supply Current IO = 0mA TEN=VSEL=LLC=1 EN=1 20 40 mA

I

IN

V

Output Voltage IO = 500 mA VSEL=1 LLC=0 17.3 18 18.7 V

O

Output Voltage IO = 500 mA VSEL=0 LLC=0 12.5 13 13.5 V

V

O

∆V

Line Regulation V

O

Load Regulation VSEL=0 or 1 I

∆V

O

Output Current Limiting ISEL=1 400 550 mA

I

MAX

I

Output Short Circuit Current ISEL=1 200 mA

SC

t

Dynamic Overload

OFF

protection OFF Time

t

Dynamic Overload

ON

protection ON Time

f

A

D

G
V

Z

f

DETIN

V

Z

Tone Frequency TEN=1 20 22 24 KHz

TONE

Tone Amplitude TEN=1 0.55 0.72 0.9 Vpp

TONE

Tone Duty Cycle TEN=1 40 50 60 %

TONE

t

, tfTone Rise and Fall Time TEN=1 5 10 15 µs

r

External Modulation Gain ∆V

EXTM

External Modulation Input

EXTM

Voltage
External Modulation

EXTM

Impedance

V

Loopthrough Switch Voltage

LT

Drop (lt1 to LT2)
DC/DC Converter Switch

f

SW

Frequency
Tone Detector Frequency

Capture Range
Tone Detector Input

DETIN

Amplitude
Tone Detector Input

DETIN

Impedance

V

DSQOUT Pin Logic LOW Tone present IOL=2mA 0.3 0.5 V

OL

DSQOUT Pin OFF State

I

OZ

Leakage Current

V

DSQIN Input Pin Logic

IL

LOW

V

DSQIN Input Pin Logic

IH

HIGH

I

DSQIN Pins Input Current VIH = 5V 15 µA

IH

=12V, I

IN

=50mA, unless otherwise specified. See software description section

OUT

EN=0 2.55mA

LLC=1 19 V

LLC=1 14 V

=15 to 18V VSEL=0 5 40 mV

IN1

VSEL=1 5 60 mV

= 50 to 500mA 200 mV

OUT

ISEL=0 500 650 mA

ISEL=0 300 mA

PCL=0 Output Shorted 900 ms

PCL=0 Output Shorted t

OUT

/∆V

, f = 10Hz to 40KHz 6

EXTM

/10 ms

OFF

AC Coupling 400 mVpp

f = 10Hz to 50KHz 260 Ω

EN=0, ILT=300mA, VMI=12 or

0.35 0.6 V

19V

220 kHz

0.4Vpp sinewave 18 24 kHz

fIN=22kHz sinewave 0.2 1.5 Vpp

150 kΩ

Tone absent VOH = 6V 10 µA

0.8 V

2V

9/24

LNBP21

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

Output Backward Current EN=0 V

OBK

T

∆T

Temperature Shutdown

SHDN

Threshold
Temperature Shutdown

SHDN

Hysteresis

Table 6: Gate And Sense Electrical Characteristics (TJ = 0 to 85°C, VIN=12V)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

R

DSON-L

R

DSON-H

V

SENSE

Gate LOW R
Gate LOW R

DSON
DSON

I

=-100mA 4.5 Ω

GATE

I

=100mA 4.5 Ω

GATE

Current Limit Sense Voltage 200 mV

= 18V -4 -10 mA

OBK

150 °C

15 °C

Table 7: I

2

C Electrical Characteristics (TJ = 0 to 85°C, VIN=12V)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

LOW Level Input Voltage SDA, SCL 0.8 V

IL

HIGH Level Input Voltage SDA, SCL 2 V

V

IH

Input Current SDA, SCL, VIN= 0.4 to 4.5v -10 10 µA

I

IH

V

DSQIN Input Pin Logic

IL

LOW

f

Maximum Clock Frequency SCL 500 KHz

MAX

Table 8: Address Pin Characteristics (T

SDA (open drain), IOL = 6mA 0.6 V

= 0 to 85°C, VIN=12V)

J

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

ADDR-1

V

ADDR-2

V

ADDR-3

V

ADDR-4

"0001000" Addr Pin Voltage 0 0.7 V
"0001001" Addr Pin Voltage 1.3 1.7 V
"0001010" Addr Pin Voltage 2.3 2.7 V
"0001011" Addr Pin Voltage 3.3 5 V

10/24

Figure 7: Test Cir cuit

STPS2L30A

L1=22µH

IIN

Vin

A

From I2C
Master

Pulse Gen.

SDA

{

SCL

STN4NF03L

Rsc

0.1

ΩΩΩΩ

470nF

470nF

220µF

220µF 470nF

Vup

Gate

Sense

Vcc

SDA
SCL

DSQIN

BYP

ADDRESS

1N4001

LNBP21

LT1

LT2

OUT

EXTM

DETIN

DSQOUT

LNBP21

ILT

V

MI, VOBK

V

, IOBK

A

VOUT

A

IOZ / IOL

LT

A

V

Scope Probe

Load

VEXTM, VDETIN

OH

OL

V

/ I

10nF

V

IO

10nF

20µF

10nF

OL

V

V

TYPICAL CHARACTERISTICS (unless otherwise specified T
Figure 8: Output Voltage vs Temperature

Figure 9: Output Voltage vs Temperature

= 25°C)

j

11/24

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Figure 1 0: Line Regulation vs Temperature

Figure 1 1:

Line Regulation vs Temperature

Figure 1 3:

Figure 1 4:

Load Regulation vs Temperature

Supply Current vs Temperature

Figure 1 2:

12/24

Load Regulation vs Temperature

Figure 1 5:

Supply Current vs Temperature

LNBP21

Figure 1 6: Dynamic Overload Protection ON

Time vs Temperature

Figure 1 7:

Time vs Temperature

Dynamic Overload Protection OFF

Figure 1 9:

Temperature

Figure 2 0:

Output Current Limiting vs

Tone Frequency vs Temperature

Figure 1 8:

Temperature

Output Current Limiting vs

Figure 2 1:

Tone Amplitude vs Temperature

13/24

LNBP21

Figure 2 2: Tone Duty Cycle vs Temperature

Figure 2 3:

Tone Rise Time vs Temperature

Figure 2 5:

Temperature

Figure 2 6:

Temperature

Loopthrought Switch Drop Voltage vs

Loopthrought Switch Drop Voltage vs

Figure 2 4:

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Tone Fall Time vs Temperature

Figure 2 7:

Loopthrought Current

Loopthrought Switch Drop Voltage vs

LNBP21

Figure 2 8: Loopthrou ght Switch Drop Voltage vs

Loopthrought Current

Figure 2 9:

Temperature

DSQOUT Pin Logic Low vs

Figure 3 1:

Temperature

Figure 3 2:

Temperature

Output Backward Current vs

DC/DC Converter Efficiency vs

Figure 3 0:

Temperature

Undervoltage Lockout Threshold vs

Figure 3 3:

Current Limit Sense vs Temperature

15/24

LNBP21

Figure 3 4: 22kHz Tone

VCC=12V, IO=50mA, EN=TEN=1

Figure 3 5:

Response

DSQIN Tone Enable Transient

Figure 3 7:

Response

VCC=12V, IO=50mA, EN=1, TEN=0

Figure 3 8:

from 13V to 18V

DSQIN Tone Disable Transient

Output Voltage Transient Response

VCC=12V, IO=50mA, EN=1, TEN=0

Figure 3 6:

Response

VCC=12V, IO=50mA, EN=1, TEN=0

16/24

DSQIN Tone Enable Transient

VCC=12V, IO=50mA, VSEL=from 0 to 1, EN=1

Figure 3 9:

from 13V to 18V

VCC=12V, IO=50mA, VSEL=from 1 to 0, EN=1

Output Voltage Transient Response

THERMAL DESIGN NOT ES

LNBP21

During normal operation, this device dissipates
some power. At maximum rated output current
(500mA), the voltage drop on the linear regulator
lead to a total dissipated power that is of about

1.7W. The heat generated requires a suitable
heatsink to keep the junction temperature below
the over temperature protection threshold.
Assuming a 40°C temperature inside the
Set-Top-Box case, the total Rthj-amb has to be
less than 50°C/W.

While this can be easily achieved using a
through-hole power package that can be attached
to a small heatsink o r to the meta llic fram e of the
receiver, a surface mount power package must
rely on PCB solutions whose thermal efficiency is
often limited. The simplest solution is to use a
large, continuous copper area of the GND layer to
dissipate the heat coming from the IC body.

The SO-20 package of this IC has 4 GND pins that
are not just intended for electrical GND
connection, but also to provide a low thermal
resistance path between the silicon chip and the
PCB heatsink. Given an Rthj-c equal to 15°C/W, a
maxi mum o f 35°C/W are left to the PC B heatsink .
This figure is achieved if a minimum of 25cm
copper area is placed just below the IC body. This

area can be the inner GND layer of a multi-layer
PCB, or, in a dual layer PCB , an unbroken GND
area even on the opposite side where the IC is
placed. In both cases, the thermal path between
the IC GND pins and the d issipating copper area
must exhibit a low thermal resistance.

In figure 40, it is shown a suggested layout for the
SO-20 package with a dual layer PCB, where t he
IC Ground pins and the square dissipating area
are thermally connected through 32 vias holes,
filled by solder. This arrangement, when L=50mm,
achieves an Rthc-a of about 25°C/W.

Different layouts are possible, too. Basic
principles, however, suggest to keep the IC and its
ground pins approximately in the middle of the
dissipating area; to provide as many vias as
possible; to design a dissipating area having a
shape as square as possible and not interrupted
by other copper traces.

Due to presence of an ex po sed pad connected to
GND below the IC body, the PowerSO-20
package has a Rthj-c much lower than the SO-20,
only 2°C/W. As a result, much lower copper area
must be provided to dissipate the same power and

2

minimum of 12cm

2

copper area is enough, see

figure 41.

Figure 40: SO-20 Suggested PCB Heatsink Layout

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Figure 41: PowerSO-20 Suggested PCB Heatsi nk L ayou t

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SO-20 MECHANICAL DATA

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DIM.

A 2.35 2.65 0.093 0.104

A1 0.1 0.30 0.004 0.012

B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 12.60 13.00 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050
H 10.00 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

k0° 8° 0° 8°

ddd 0.100 0.004

MIN. TYP MAX. MIN. TYP. M AX.

mm. inch

0016022D

19/24

LNBP21

PowerSO-20 MECHANICAL DATA

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

A 3.60 0.1417

a1 0.10 0.30 0.0039 0.0118
a2 3.30 0.1299
a3 0 0.10 0 0.0039

b 0.40 0.53 0.0157 0.0209

c 0.23 0.32 0.0090 0.0013

D (1) 15.80

16.00

0.6220 0.630
E 13.90 14.50 0.5472 0.5710
e 1.27 0.0500

e3 11.43 0.4500

E1 (1) 10.90 11.10 0.4291 0.4370

E2 2.90 0.1141

G 0 0.10 0.0000 0.0039

h 1.10 0.0433
L 0.80 1.10 0.0314 0.0433
N

0˚ 10˚

1

S0˚ 8˚0˚ 8˚
T 10.0 0.3937

(1) “D and E1” do not include mo

ld flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.00

”)

6

E2

h x 45˚

NN

a2

b

DETAIL A

110

e3

D

T

e

1120

A

E1

DETAIL B

PSO20MEC

R

lead

a3

Gage Plane

E

DETAIL

0.35

S

B

a1

L

c

DETAIL A

slug

-C-

SEATING PLANE

GC

(COPLANARITY)

0056635

20/24

LNBP21

Tape & Reel SO-20 MECHANICAL

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 30.4 1.197

Ao 10.8 11 0.425 0.433
Bo 13.2 13.4 0.520 0.528
Ko 3.1 3.3 0.122 0.130
Po 3.9 4.1 0.153 0.161

P 11.9 12.1 0.468 0.476

DATA

21/24

LNBP21

Tape & Reel PowerSO-20 MECHANICAL DATA

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 30.4 1.197

Ao 15.1 15.3 0.594 0.602
Bo 16.5 16.7 0.650 0.658
Ko 3.8 4.0 0.149 0.157
Po 3.9 4.1 0.153 0.161

P 23.9 24.1 0.941 0.949

W 23.7 24.3 0.933 0.957

mm. inch

22/24

Table 9: Revision History

Date Revision Description of Change s

07-Jul-2004 2 Typing error on text.

05-Oct-2004 3 Mistake Pin 6 Power SO-20 - Table 4.

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LNBP21

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of s uch inf ormati on nor for a ny infr ing eme nt o f p atent s or o ther ri ghts of third parties wh ich m ay res ul t from i ts use. No license i s gr an ted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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