Datasheet LNBP20PD-TR, LNBP12SP-TR, LNBP11SP-TR, LNBP10SP-TR, LNBP16SP-TR Datasheet (SGS Thomson Microelectronics)

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LNBP SUPPLY AND CONTROL VOLTAGE

REGULATOR (PARALLEL INTERFACE)

■ COMPLETE INTERFACE FOR TWO LNBs

REMOTE SUPPLY AND CONTROL

■ LNB SELECTION AND STAND-BY

FUNCTION

■ BUILT-IN TONE OSCILLATOR FACTORY

TRIMMED AT 22KHz

■ FAST OSCILLATORSTART-UP FACILITATES

DiSEqC

■ TWO SUPPLY INPUTS FOR LOWEST

DISSIPATION

■ BYPASS FUNCTION FOR SLAVE

OPERATION

■ LNB SHORT CIRCUIT PROTECTION AND

DIAGNOSTIC

■ AUXILIARY MODULATION INPUT EXTENDS

FLEXIBILITY

■ CABLE LENGTH COMPENSATION

■ INTERNAL OVER TEMPERATURE

PROTECTION

■ BACKWARD CURRENT PROTECTION

DESCRIPTION

Intended for analog and digital satellite receivers, the LNBP is a monolithic linear voltage regulator, assembled in Multiwatt-15, PowerSO-20 and PowerSO-10, specifically designed to provide the powering voltages and the interfacing signals to the LNB downconverter situated in the antenna via the coaxial cable. Since most satel lite receivers have two antenna ports, the output voltage of the regulator is available at one of two logic-selectable output pins (LNBA, LNBB ). When the IC is powered and put in Stand-by (EN pin LOW), both regulat or outputs are disabled to allow the antenna downconverters to be supplied/ controlled by others satellite receivers sharing the same coaxial lines. I n this oc c urrence the device will limit at 3 mA (max) the backw ard current that could flow from LNBA and LNBB output pins to GND. For slave operation in single dish, dual receiver systems, the bypass function is implemented by an electronic switch between t he Master Input pin (MI) and the LNBA pin, thu s leaving all LNB powering and control functions to the Master Receiver. This electronic switch is close d when the device is powered and EN pin is LOW.



ENCODING

LNBP10 SERIES

LNBP20

Multiwatt-15

Power SO-20

The regulator outputs can be logic controlled to be 13 or 18 V (typ.) by mean of the VSEL pin for remote controlling of LNBs. Additionally, it is possible to increment by 1V (typ.) the selected voltage value to compensate the excess voltage drop along th e c oax ial c able (LLC pin HIGH). In orde r to reduc e the power dissipation of the device when the l owes t output voltage is selected, the regulator has two Supply Input pins V V

. They must be powered respec ti v ely at 16V

CC2

(min) and 23V (min), and an internal switch automatically will select the suitable supply pin according to the s elected output voltage. If adequate heatsink is provided and higher power losses are ac ceptable, both supply pins can be powered by the same 23V source without affecting any other circuit performance. The ENT (T one Enable) pin activates the internal oscillator so that the DC output is modulated by a ±0.3 V , 22KHz (typ.) square wave. This internal oscillator is factory trimmed within a tolerance of ±2KHz, thus no further adjustments neither external components are required. A burst coding of the 22KHz tone can be accomplished thanks to the fast response of the ENT i nput and the prompt oscillator start-up. This helps designers who want to implement the DiSEqC



protocols (*). In order to improve design flexibility and to allow implementation of newcoming LNB remote contro l standards, an analogic modulation

PowerSO-10

CC1

and

1/20June 2003

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LNBP10 SERIES - LNBP20

input pin is available (EXTM). An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. When external modulation is not used, the relevant pin can be left open. Two pins are dedicated to the overcurrent protection/monitoring: CEXT and OLF. T he overcurrent protection circuit works dynamically: as soon as an overload i s detected in either LNB output, th e output is shut-down for a time t

off

determined by t he capacitor connected between CEXT and GND. Simultaneously the OLF pin, that is an open collector diagnostic output flag, from HIGH IMPEDANCE state goes LOW. After t he time has elapsed, the output is resumed for a time t

(*): External components are needed to comply to level 2.x and above (bidirectional) DiSEqCbus hardware requirements. DiSEqCis a trademark or EUTELSAT.

=1/15t

(typ.) and OLF goes in HIG H

off

IMPEDANCE. If the overload is still present, the protection circuit will cycle again through t ton until the ov erload is removed. Typical t

and

off

on+toff

value is 1200ms when a 4.7µF external capacitor is used. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up even with highly capacitive loads on LNB out puts. The device is packaged in Multiwatt15 for thru-holes mounting and in PowerSO-20 for surface mounting. When a limited functionality in a smaller package matches design needs, a range of cost-effective PowerSO-10 solutions is also offered. All versions have built-in thermal protection agains t overheating damage.

ORDERING CODES

TYPE Multiwatt-15 PowerSO-20 PowerSO-10

LNBP10 LNBP10SP-TR (*) LNBP11 LNBP11SP-TR (*) LNBP12 LNBP12SP-TR (*) LNBP13 LNBP13SP-TR (*) LNBP14 LNBP14SP-TR (*) LNBP15 LNBP15SP-TR (*) LNBP16 LNBP16SP-TR (*) LNBP20 LNBP20CR LNBP20PD-TR

(*) Available on request

PIN CONFIGUARATION (top view)

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PowerSo-20 PowerSO-10Multiwatt-15

Page 3

TABLE A: PIN CONFIGURATIONS

LNBP10 SERIES - LNBP20

SYMBOL NAME FUNCTION

PIN NUMBER vs SALES TYPE (LNBP)

20CR 20PD 10SP 11SP 12SP 13SP 14SP 15SP 16SP

Supply Input 1 15V to 25V supply. It is

CC1

automatically selected when V

Supply Input 2 22V to 25V supply. It is

CC2

automatically selected when V

=13or14V

OUT

=18or19V

OUT

LNBA Output Port See truth table voltage

12111 111

232222222

343333333 and port selection. In stand-by mode this port is powered by the MI pin via the internal Bypass Switch

SEL

Output Voltage Selection:13 or

Logic control input: see truth table

454444444

18V (typ)

EN Port Enable Logic control input: see

565555555 truth table

OSEL Port Selection Logic control input: see

7 7 9 NA NA NA NA NA NA truth table

GND Ground Circuit Ground. It is

internally connected to the die frame

10 11

66 6666

ENT 22KHz Tone

Enable

CEXT External

Capacitor

Logic control input: see truth table

Timing Capacitor used by the Dynamic

9137777777

10148888888

Overload protection. Typical application is

4.7µF for a 1200ms cycle

EXTM External

Modulator

External Modulation Input. Needs DC

11 15 NA NA NA 9 NA 9 9

decoupling to the AC source. if not used, can be left open.

LLC Line Length

Compens.

Logic control input: see truth table

12 16 NA NA 9 NA 9 NA 10

(1V typ)

OLF Over Load

Flag

Logic output (open collector). Normally in

13 17 NA 9 NA NA 10 10 NA

HIGH IMPEDANCE, goes LOW when current or thermal overload occurs

MI Master Input In stand-by mode, the

14 18 NA 10 10 10 NA NA NA voltage on MI is routed to LNBA pin. Can be left open if bypass function is not needed

LNBB Output Port See truth tables for

15 19 10 NA NA NA NA NA NA voltage and port selection

NOTE: the limited pin availability of the PowerSO-10 package leads to drop some functions.

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LNBP10 SERIES - LNBP20

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter² Value Unit

V I V

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.

THERMAL DATA

Symbol Parameter Value Unit

thj-case

LOGIC CONTROLS TRUTH TABLE

DC Input Voltage (V

Output Current (LNBA, LNBB)

Logic Input Voltage (ENT, EN OSEL, VSEL, LLC)

CC1,VCC2

Bypass Switch Current Power Dissipation at T

Storage Temperature Range

stg

Operating Junction Temperature Range

Thermal Resistance Junction-case

case

, MI)

< 85°C

28 V

Internally Limited mA

-0.5 to 7 V 900 mA

14 W

-40 to +150 °C

-40 to +125 °C

2 °C/W

CONTROL I/O PIN NAME L H

OUT OLF I

OUT>IOMAX

or Tj>150°C I

OUT<IOMAX

IN ENT 22KHz tone OFF 22KHz tone ON IN EN See Table Below See Table Below IN OSEL See Table Below See Table Below IN VSEL See Table Below See Table Below IN LLC See Table Below See Table Below

EN OSEL VSEL LLCO

LXXXV

LNBA

- 0.4V (typ.) Disabled

H L L L 13V (typ.) Disabled H L H L 18V (typ.) Disabled H L L H 14V (typ.) Disabled H L H H 19V (typ.) Disabled H H L L Disabled 13V (typ.) H H H L Disabled 18V (typ.) H H L H Disabled 14V (typ.) HHHH Disabled 19V (typ.)

NOTE: All logic input pins have internal pull-down resistor (typ. = 250KΩ)

LNBB

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BLOCK DIAGRAM

LNBP10 SERIES - LNBP20

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LNBP10 SERIES - LNBP20

ELECTRICALCHARACTERISTICS FOR LNBP SERIES (TJ=0 to 85°C, CI=0.22µF, CO=0.1µF, EN=H,

ENT=L, LLC=L, V

Symbol Parameter Test Conditions Min. Typ. Max. Unit

∆V

SVR Supply Voltage Rejection V

TONE

A D

G V

IN1

IN2

MAX

OFF

CC1

CC2

Output Voltage IO= 500 mA VSEL=L, LLC=L 17.3 18 18.7 V

Output Voltage IO= 500 mA VSEL=L, LLC=L 12.5 13 13.5 V

Line Regulation V

Load Regulation V

Output Current Limiting 500 650 800 mA Dynamic Overload

protection OFF Time Dynamic Overload

protection ON Time Tone Frequency ENT=H 20 22 24 KHz

Tone Amplitude ENT=H 0.55 0.72 0.9 Vpp

TONE

Tone Duty Cycle ENT=H 40 50 60 %

TONE

Tone Rise and Fall Time ENT=H 5 10 15 µs

r,tf

External Modulation Gain ∆V

EXTM

External Modulation Input

EXTM

Voltage External Modulation

EXTM

Impedance Bypass Switch Voltage

Drop (MI to LNBA) Overload Flag Pin Logic

LOW

Overload Flag Pin OFF

State Leakage Current Control Input Pin Logic

LOW Control Input Pin Logic

HIGH Control Pins Input Current VIH=5V 20 µA

Supply Current Output Disabled (EN=L) 0.3 1 mA

Output Backward Current EN=L V

OBK

Temperature Shutdown

SHDN

Threshold

=16V, V

IN1

IN2

=23V I

=50mA, unless otherwise specified.)

OUT

Supply Voltage IO= 500 mA ENT=H, VSEL=L, LLC=L 15 25 V

= 500 mA ENT=H, VSEL=L, LLC=H 16 25 V

Supply Voltage IO= 500 mA ENT=H, VSEL=L, LLC=L 22 25 V

= 500 mA VSEL=L, LLC=H 23 25 V

= 500 mA ENT=H, VSEL=L, LLC=H 19 V

= 500 mA ENT=H, VSEL=L, LLC=H 14 V

=15 to 18V V

IN1

=22 to 25V V

IN2 IN1=VIN2

IN1=VIN2

=22V V

=50to500mA

=23± 0.5Vacfac= 120 Hz, 45 dB

Output Shorted C

OUT

/∆V

, f = 10Hz to 40KHz 5

EXTM

=13V 4 40 mV

OUT

=18V 4 40 mV

OUT

=13 or 18V

OUT

=4.7µF 1100 ms

EXT

=4.7µFt

EXT

80 180 mV

/15 ms

OFF

AC Coupling 400 mVpp

f = 10Hz to 40KHz 400 Ω

EN=L, ISW=300mA, V

CC2-VMI

=4V 0.35 0.6 V

IOL=8mA 0.28 0.5 V

VOH=6V 10 µA

0.8 V

2.5 V

ENT=H, I

IN1=VIN2

=500mA 3.1 6 mA

OUT

LNBA=VLNBB

= 18V

0.23mA

= 22V or floating

150 °C

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LNBP10 SERIES - LNBP20

TYPICAL CHARACTERISTICS Figure1 : Output Voltage vs Output Current

Figure2 : Tone Duty Cycle vs Temperature

(unless otherwise specified Tj= 25°C)

Figure4 : Tone Frequency v s Temperature

Figure5 : Tone Rise Time vs Temperature

Figure3 : Tone Fall Time vs Temperature

Figure6 : Tone Amplitude vs Temperature

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LNBP10 SERIES - LNBP20

Figure7 : S .V.R. vs Frequency

Figure8 : External Modulation vs Temperature

Figure10 : LNBA External Modulation gain vs

Frequency

Figure11 : Bypass switch Drop vs Output Current

Figure9 : B y pas s Switch Drop vs Output Current

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Figure12 : overload Flag pin Logic LOW v s Flag Current

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LNBP10 SERIES - LNBP20

Figure13 : Supply Voltage vs Temperature

Figure14 : Supply Current vs Temperature

Figure16 : Tone Enable

Figure17 : Tone Disable

Figure15 : Dynamic Overload protection (I

Time)

Figure18 : 22KHz Tone

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LNBP10 SERIES - LNBP20

Figure19 : Enable Time

Figure20 : Disable Time

Figure21 : 18V to 13V Change

Figure22 : 18V to 13V Change

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TYPICAL APPLICATION SCHEMATICS

TWO ANTENNA PORTS RECEIVER

10uF

AUX DATA

47K

4 9 5 7

EXTM

OLF

VSEL ENT EN OSEL LLC

LNBP20CR

VCC1 VCC2

LNBA LNBB

CEXT

GND

LNBP10 SERIES - LNBP20

17V 24VMCU+V

1 2

3 15 14

4.7µF

2x 0.1µF

C4 C6C5

2x 47nF

TUNER

ANT CONNECTORS

I/OsVcc

MCU

SINGLE ANTENNA RECEIVER WITH MASTER RECEIVER PORT

24V17V

C4 C5

47nF

AUX DATA

MCU+V

47K

10uF

EXTM

OLF

VSEL

ENT

OSEL

LLC LNBP20CR

I/OsVcc

VCC1 VCC2

LNBA LNBB

CEXT

GND

1 2

3 15 14

4.7µF

2x 0.1µF

MCU

I/Os

ANT

MASTER

TUNER

I/Os

11/20

Page 12

LNBP10 SERIES - LNBP20

USING SERIAL BUS TO SAVE MPU I/Os

1 2

3 15 14

4.7µF

17V

2x 0.1µF

MCU+V

47K

I/Os Vcc

AUX DATA

STR

CLK

4094

MCU+V

EXTM

10uF

OLF

9 5 7

MCU

VSEL ENT

EN OSEL LLC

LNBP20CR

VCC1 VCC2

LNBA LNBB

CEXT

GND

TWO ANTENNA PORTS RECEIVER: LOW COST SOLUTION

C4 C6C5

2x 47nF

SERIAL BUS

24V

TUNER

ANT CONNECTORS

MCU+V

17V 24V

VCC1

VCC2

LNBA

LNBB

VSEL

ENT

OSEL

LNBP10SP

I/OsVcc

CEXT

GND

C14.7µF C4 C6C5

MCU

2x 0.1µF

2x 47nF

TUNER

I/Os

ANT CONNECTORS

12/20

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LNBP10 SERIES - LNBP20

CONNECTING TOGETHER V

VSEL

ENT

OSEL

MCU+V

I/OsVcc

LNBP10SP

CC1

AND V

VCC1 VCC2

LNBA LNBB

CEXT

GND

1 2

3 10

4.7µF

MCU

CC2

24V

ANT CONNECTORS

TUNER

0.1µF

C6C5

2x 47nF

I/Os

SINGLE ANTENNA RECEIVER WITH MASTER RECEIVER PORT: LOW COST SOLUTION

AUX DATA

MCU+V

24V17V

EXTM

10µF

VSEL

ENT

LNBP13SP

I/OsVcc

VCC1 VCC2

LNBA

CEXT

GND

1 2

C4 C5

C14.7µF

2x 0.1µF

MCU

47nF

TUNER

I/Os

ANT

MASTER

13/20

Page 14

LNBP10 SERIES - LNBP20

SINGLE ANTENNA RECEIVER WITH OVERLOAD DIAGNOSTIC

AUX DATA

MCU+V

47K

Vcc I/Os

10µF

24V17V

4 7 5

EXTM

OLF

VSEL ENT EN

LNBP15SP

VCC1 VCC2

LNBA

CEXT

GND

1 2

C14.7µF

MCU

2x 0.1µF

C4 C5

47nF

TUNER

I/Os

ANT

14/20

Page 15

LNBP10 SERIES - LNBP20

MULTIWATT-15 MECHANICAL DATA

DIM.

A 5 0.197 B 2.65 0.104 C 1.6 0.063 D 1 0.039 E 0.49 0.55 0.019 0.022 F 0.66 0.75 0.026 0.030

G 1.02 1.27 1.52 0.040 0.050 0.060 G1 17.53 17.78 18.03 0.690 0.700 0.710 H1 19.6 0.772 H2 20.2 0.795

L 21.9 22.2 22.5 0.862 0.874 0.886

L1 21.7 22.1 22.5 0.854 0.870 0.886 L2 17.65 18.1 0.695 0.713 L3 17.25 17.5 17.75 0.679 0.689 0.699 L4 10.3 10.7 10.9 0.406 0.421 0.429 L7 2.65 2.9 0.104 0.114

M 4.25 4.55 4.85 0.167 0.179 0.191

M1 4.63 5.08 5.53 0.182 0.200 0.218

S 1.9 2.6 0.075 0.102

S1 1.9 2.6 0.075 0.102

Dia1 3.65 3.85 0.144 0.152

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

0016036

15/20

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LNBP10 SERIES - LNBP20

PowerSO-20 MECHANICAL DATA

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

A 3.60 0.1417 a1 0.10 0.30 0.0039 0.0118 a2 3.30 0.1299 a3 0 0.10 0 0.0039

b 0.40 0.53 0.0157 0.0209

c 0.23 0.32 0.0090 0.0013

D (1) 15.80

16.00

0.6220 0.630 E 13.90 14.50 0.5472 0.5710 e 1.27 0.0500

e3 11.43 0.4500

E1 (1) 10.90 11.10 0.4291 0.4370

E2 2.90 0.1141

G 0 0.10 0.0000 0.0039 h 1.10 0.0433 L 0.80 1.10 0.0314 0.0433 N0˚10˚

1 S0˚ 8˚0˚ 8˚ T 10.0 0.3937

(1) “D and E1” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006”)

h x45˚

DETAIL A

110

1120

DETAIL B

PSO20MEC

lead

Gage Plane

DETAIL B

0.35

DETAIL A

slug

-C-

SEATING PLANE

(COPLANARITY)

0056635

16/20

Page 17

LNBP10 SERIES - LNBP20

PowerSO-10 MECHANICAL DAT A

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

A 3.35 3.65 0.132 0.144

A1 0.00 0.10 0.000 0.004

B 0.40 0.60 0.016 0.024

c 0.35 0.55 0.013 0.022

D 9.40 9.60 0.370 0.378

D1 7.40 7.60 0.291 0.300

E 9.30 9.50 0.366 0.374

E1 7.20 7.40 0.283 0.291 E2 7.20 7.60 0.283 0.300 E3 6.10 6.35 0.240 0.250 E4 5.90 6.10 0.232 0.240

e 1.27 0.050 F 1.25 1.35 0.049 0.053 H 13.80 14.40 0.543 0.567 h 0.50 0.002 L 1.20 1.80 0.047 0.071 q 1.70 0.067

0˚ 8˚

= =

0.25

= =

610

= =

DETAIL "A"

0.10 A

E1E3

= =

SEATING

PLANE

= =

SEATING PLANE

= =

0068039-C

17/20

Page 18

LNBP10 SERIES - LNBP20

Tape & Reel PowerSO-20 MECHANICAL DATA

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 30.4 1.197

Ao 15.1 15.3 0.594 0.602 Bo 16.5 16.7 0.650 0.658 Ko 3.8 4.0 0.149 0.157 Po 3.9 4.1 0.153 0.161

P 23.9 24.1 0.941 0.949

W 23.7 24.3 0.933 0.957

mm. inch

18/20

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LNBP10 SERIES - LNBP20

Tape & Ree l PowerSO10 M ECHA NICAL DATA

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992

C 12.8 13.2 0.504 0.519 D20.2 0.795 N60 2.362

T 30.4 1.197

Ao 14.9 15.1 0.587 0.594 Bo 9.9 10.1 0.390 0.398 Ko 4.15 4.35 0.163 0.171 Po 3.9 4.1 0.153 0.161

P 23.9 24.1 0.941 0.949

W 23.7 24.3 0.933 0.957

mm. inch

19/20

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LNBP10 SERIES - LNBP20

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use o f suc h inf ormat ion n or f or an y infr ingeme nt of paten ts or oth er ri gh ts of third part ies whic h may resul t f rom its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to chang e without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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