Datasheet LNBH25 Datasheet (ST)

LNB supply and control IC with step-up and I²C interface

Features

■ Complete interface between LNB and I²C bus

■ Built-in DC-DC converter for single 12 V supply

operation and high efficiency (typ. 93 % @

0.5 A)

■ Selectable output current limit by external

resistor

■ Compliant with main satellite receivers output

voltage specification (15 programmable levels)

■ Accurate built-in 22 kHz tone generator suits

widely accepted standards

■ 22 kHz tone waveform integrity guaranteed

also at no load condition

■ Low-drop post regulator and high efficiency

step-up PWM with integrated power N-MOS
allowing low power losses

■ LPM function (low power mode) to reduce

dissipation

■ Overload and overtemperature internal

protections with I²C diagnostic bits

■ LNB short-circuit dynamic protection

■ +/- 4 kV ESD tolerant on output power pins

Applications

■ STB satellite receivers

■ TV satellite receivers

■ PC card satellite receivers

LNBH25

QFN24 (4 x 4 mm)

Description

Intended for analog and digital satellite
receivers/Sat-TV and Sat-PC cards, the LNBH25
is a monolithic voltage regulator and interface IC,
assembled in QFN24 4x4 specifically designed to
provide the 13/18 V power supply and the 22 kHz
tone signalling to the LNB down-converter in the
antenna dish or to the multi-switch box. In this
application field, it offers a complete solution with
extremely low component count and low power
dissipation together with a simple design and I²C
standard interfacing.

Table 1. Device summary

Order code Package Packaging

LNBH25PQR QFN24 (4 x 4) Tape and reel

February 2012 Doc ID 022433 Rev 4 1/34

www.st.com

34

Contents LNBH25

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 DiSEqC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4

2.3 Data encoding by external DiSEqC envelope control

through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 LPM (low power mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.5 DiSEqC 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.6 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.7 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.8 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.9 Surge protections and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.10 FLT: fault flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.11 VMON: output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.12 TMON: 22 kHz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.13 TDET: 22 kHz tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.14 IMON: minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.15 PDO: overcurrent detection on output pull-down stage . . . . . . . . . . . . . . . 8

2.16 Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 8

2.17 PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.18 ISW: inductor switching current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.19 COMP: boost capacitor ESR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.20 OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 9

2.21 OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2/34 Doc ID 022433 Rev 4

LNBH25 Contents

6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.3 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.4 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Doc ID 022433 Rev 4 3/34

Block diagram LNBH25

1 Block diagram

Figure 1. Block diagram

ADDR

SDASCL

DSQIN

DETIN

DSQOUT

FLT

BPSW

Tone

detector

Voltage

reference

LX

I2C Digital core

PWM CTRL

Isense

DAC
Drop control
Tone ctrl
Diagnostics
Protections

Current

Limit

selection

VCCGND BYP

ISEL

Linear

Regulator

Gate ctrl

PGND

VUP

VOUT

AM10400v1

4/34 Doc ID 022433 Rev 4

LNBH25 Application information

2 Application information

This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V),
generates the voltages (V
/18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) to work with a minimum
dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at
V

up-VOUT

tone output is disabled by setting the LPM bit to “1” (see
IC is also provided with an undervoltage lockout circuit that disables the whole circuit when
the supplied V
function reduces the inrush current during start-up. The SS time is internally fixed at 4 ms
typ. to switch from 0 to 13 V and 6 ms typ. switch from 0 to 18 V.

= 1 V typ.). The LDO power dissipation can be further reduced when the 22 kHz

drops below a fixed threshold (4.7 V typ.). The step-up converter soft-start

CC

2.1 DiSEqC data encoding (DSQIN pin)

The internal 22 kHz tone generator is factory trimmed in accordance to DiSEqC standards,
and can be activated in 3 different ways:

1. by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL

compatible). In this case the I²C Tone control bits must be set: EXTM = TEN = 1.

2. by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this

case the I²C Tone control bits must be set: EXTM = 0 and TEN = 1.

3. through the TEN I²C bit if a 22 kHz presence is requested in continuous mode. In this

case the DSQIN TTL pin must be pulled HIGH and EXTM bit set to “0”.

) that let the integrated LDO post-regulator (generating the 13 V

up

2.4: LPM (low power mode)

). The

Each of the above solutions requires that during the 22 kHz tone activation and/or DiSEqC
data transmission, the LPM bit must be set to “0” (see

2.4: LPM (low power mode)

2.2 Data encoding by external 22 kHz tone TTL signal

In order to improve design flexibility an external tone signal can be input to the DSQIN pin by
setting the EXTM bit to “1”.

The DSQIN is a logic input pin which activates the 22 kHz tone to the V
LNBH25 integrated tone generator.

The output tone waveforms are internally controlled by the LNBH25 tone generator in terms
of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is
used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz
signal is required for the proper control of the DSQIN pin function. Before sending the TTL
signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as
the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH25
activates the 22 kHz tone on the V
activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has
expired (refer to

Figure 2

).

output with about 1 µs delay from TTL signal

OUT

OUT

).

pin, by using the

Doc ID 022433 Rev 4 5/34

Application information LNBH25

Figure 2. Tone enable and disable timing (using external waveform)

DSQIN

Tone

~ 1 µs

Output

~ 60 µs

AM10426v1

2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin

If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz
generator activated during the tone transmission by connecting the DiSEqC envelope
source to the DSQIN pin. In this case the I²C Tone control bits must be set: EXTM = 0 and
TEN = 1. In this way, the internal 22 kHz signal is superimposed to the V
generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH,
the internal control circuit activates the 22 kHz tone output.

The 22 kHz tone on the V

pin is activated with about 6 µs delay from the DSQIN TTL

OUT

signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22
kHz TTL signal on DSQIN has expired (refer to

Figure 3

).

Figure 3. Tone enable and disable timing (using envelope signal)

DSQIN

Tone

~ 6 µs

Output

15 µs ~ 60 µs

DC voltage to

OUT

2.4 LPM (low power mode)

In order to reduce total power loss, the LNBH25 is provided with the LPM I²C bit that can be
activated (LPM=1) in applications where the 22 kHz tone can be disabled for long time
periods. The LPM bit can be set to “1” when the DiSEqC data transmission is not requested
(no 22 kHz tone output is present); at this condition the drop voltage across the integrated
LDO regulator (V

UP-VOUT

) is reduced to 0.6 V typ. and, consequently, the power loss inside
the LNBH25 linear regulator is reduced too. For example: at 500 mA load, LPM=1 allowing a
minimum LDO dissipated power of 0.3 W typ. It is recommended to set the LPM bit to “0”
before starting the 22 kHz DiSEqC data transmission; at this condition the drop voltage
across the LDO is kept to 1 V typ. Keep LPM=0 at all times in case the LPM function is not
used.

2.5 DiSEqC 2.0 implementation

The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC 2.0 interfacing.
The input pin (DETIN) must be AC coupled to the DiSEqC BUS, and extracted PWK data is
available on the DSQOUT pin. To comply with the bi-directional DiSEqC 2.0 bus hardware

6/34 Doc ID 022433 Rev 4

AM10427v1

LNBH25 Application information

requirements an output RL filter is needed. In order to avoid 22 kHz waveform distortion
during tone transmission, LNBH25 is provided with the BPSW pin to be connected to an
external transistor, which allows to bypass the output RL filter in DiSEqC 2.x applications
while in transmission mode. Before starting tone transmission by means of the DSQIN pin,
make sure that the TEN bit is preventively set to “1” and after ending tone transmission,
make sure that the TEN bit is set to “0”.

2.6 Output current limit selection

The linear regulator current limit threshold can be set by an external resistor connected to
the ISEL pin. The resistor value defines the output current limit by the equation:

Equation 1

13915

=

MAX

with ISET=0

Equation 2

.)typ(I

RSEL

111.1

6808

=

MAX

.)typ(I

RSEL

068.1

with ISET=1

(Refer also to the ISET bit description in

Ta bl e 9

).

where RSEL is the resistor connected between ISEL and GND expressed in kΩ and
I

(typ.) is the typical current limit threshold expressed in mA. I

MAX

2.7 Output voltage selection

The linear regulator output voltage level can be easily programmed in order to accomplish
application specific requirements, using 4 bits of an internal DATA 1 register (see

registers

and

Ta bl e 1 4

for exact programmable values). Register writing is accessible via the

I²C bus.

2.8 Diagnostic and protection functions

LNBH25 has 8 diagnostic internal functions provided via the I²C bus, by reading 8 bits on
two STATUS registers (in read mode). All the diagnostic bits are, in normal operation (that is
no failure detected), set to LOW. Two diagnostic bits are dedicated to the overtemperature
and overload protection status (OTF and OLF) while the remaining 6 bits are dedicated to
the output voltage level (VMON), to 22 kHz tone characteristics (TMON), to the minimum
load current (IMON), to external voltage source presence on the V
input voltage Power Not Good function (PNG) and to the 22 kHz tone presence on the
DETIN pin (TDET). Once the OLF (or OTF or PNG) bit has been activated (set to “1”), it is
latched to “1” until relevant cause is removed and a new register reading operation is done.

can be set up to 1 A.

MAX

pin (PDO), to the

OUT

7.3: Data

Doc ID 022433 Rev 4 7/34

Application information LNBH25

2.9 Surge protections and TVS diodes

The LNBH25 device is directly connected to the antenna cable in a set-top box. Atmospheric
phenomenon can cause high voltage discharges on the antenna cable causing damage to
the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an
external (outdoor) circuit. This leads to currents or electromagnetic fields causing high
voltage or current transients. Transient voltage suppressor (TVS) devices are usually
placed, as shown in the following schematic, to protect the STB output circuits where the
LNBH25 and other devices are electrically connected to the antenna cable.

Figure 4. Surge protection circuit

For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically
designed by ST. The selection of LNBTVS diodes should be made based on the maximum
peak power dissipation that the diode is capable of supporting (see Ppp (W) parameter in
the LNBTVS datasheet for further details).

2.10 FLT: fault flag

In order to get an immediate feedback on diagnostic status, LNBH25 is equipped with a
dedicated fault flag pin (FLT). In the case of overload (OLF bit=1) or overheating (OTF bit=1)
or if Power No Good (PNG bit=1) condition is detected, the FLT pin (open drain output) is set
to low and is kept low until the relevant activating diagnostic bit is cleared. Be aware that
diagnostic bits OLF, OTF and PNG, once activated, are kept latched to “1” until the cause
origin is removed and a new register reading operation is performed by the microprocessor.
The FLT pin must be connected to a positive voltage (5 V max.) by means of a pull-up
resistor.

2.11 VMON: output voltage diagnostic

When device output voltage is activated (V
long as the output voltage level is below the guaranteed limits, the VMON I²C bit is set to “1”.
See

Ta b le 1 7

for more details.

pin), its value is internally monitored and, as

OUT

2.12 TMON: 22 kHz tone diagnostic

The 22 kHz tone can be internally detected and monitored if the DETIN pin is connected to
the LNB output bus (see typical application circuit in
capacitor.
The tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz tone amplitude
and/or the tone frequency is out of the guaranteed limits (see
set to “1”.

Figure 7

) through a decoupling

Ta b le 1 9

), the TMON I²C bit is

8/34 Doc ID 022433 Rev 4

LNBH25 Application information

2.13 TDET: 22 kHz tone detection

When a 22 kHz tone presence is detected on the DETIN pin, the TDET I²C bit is set to “1”.

2.14 IMON: minimum output current diagnostic

In order to detect the output load absence (no LNB connected on the bus or cable not
connected to the IRD) the LNBH25 is provided with a minimum output current flag by the
IMON I²C bit, accessible in read mode, which is set to “1” if the output current is lower than
12 mA (typ.). It is recommended to use IMON function only with the 22 kHz tone
transmission deactivated, otherwise the IMON bit could be set to “0” even if the output
current is below the minimum current threshold. To activate IMON diagnostic function, set to
“1” the EN_IMON I²C bit in the DATA 4 register. Be aware that as soon as the IMON function
is activated by means of EN_IMON=1, the V
independently on the VSEL bit setting. This operation is applied in order to be sure that the
LNBH25 output has the higher voltage present in the LNB bus. Do not use this function in an
application environment where 21 V voltage level is not supported by other peripherals
connected to the LNB bus.

is immediately increased to 21 V (typ.)

OUT

2.15 PDO: overcurrent detection on output pull-down stage

When an overcurrent occurs on the pull-down output stage due to an external voltage
source greater than LNBH25 nominal V
ms typ.), the PDO I²C bit is set to “1”. This may happen due to an external voltage source
present on the LNB output (V

For current threshold and deglitch time details, see

OUT

pin).

and for a time longer than I

OUT

Ta bl e 1 3

.

SINK_TIME-OUT

2.16 Power-on I²C interface reset and undervoltage lockout

The I²C interface built into LNBH25 is automatically reset at power-on. As long as the VCC
stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not
respond to any I²C command and all DATA register bits are initialized to zeroes, therefore
keeping the power blocks disabled. Once the V
becomes operative and the DATA registers can be configured by the main microprocessor.

rises above 4.8 V typ. the I²C interface

CC

2.17 PNG: input voltage minimum detection

When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds,
the PNG I²C bit is set to “1” and the FLT pin is set low. Refer to

Ta bl e 1 3

for threshold details.

2.18 ISW: inductor switching current limit

(10

In order to allow low saturation current inductors to be used, the maximum DC-DC inductor
switching current limit threshold can be set by means of one I²C bit (ISW). Two values are
available: 2.5 A typ. (with ISW = 1) and 4 A typ. (with ISW = 0).

Doc ID 022433 Rev 4 9/34

Application information LNBH25

2.19 COMP: boost capacitor ESR

DC-DC converter compensation loop can be optimized in order to work well with high or low
ESR capacitors (on the V

pin). For this purpose, one I²C bit in the DATA 4 register

UP

(COMP) can be set to “1” or “0”. It is recommended to reset this bit to “0” unless using high
ESR capacitors.

2.20 OLF: overcurrent and short-circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short-circuit condition,
the device is provided with a dynamic short-circuit protection. It is possible to set the short­circuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I²C DATA 3 register. When the PCL (pulsed current limiting) bit is set Io LOW, the
overcurrent protection circuit works dynamically: as soon as an overload is detected, the
output current is provided for T
programmed in the DATA 3 register) and after that, the output is set in shutdown for T
time of typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the system register is
set to “1” and the FLT pin is set to low level. After this time has elapsed, the output is
resumed for a time T

. At the end of TON, if the overload is still detected, the protection

ON

circuit cycles again through T
detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW after a
register reading is done. Typical T
TIMER=1) and an internal timer determines it. This dynamic operation can greatly reduce
the power dissipation in short-circuit condition, still ensuring excellent power-on startup in
most conditions. However, there could be some cases in which a highly capacitive load on
the output may cause a difficult startup when the dynamic protection is chosen. This can be
solved by initiating any power startup in static mode (PCL=1) and, then, switching to the
dynamic mode (PCL=0) after a chosen amount of time depending on the output
capacitance. Also in static mode, the diagnostic OLF bit goes to “1” (and the FLT pin is set to
low) when the current clamp limit is reached and returns LOW when the overload condition
is cleared and register reading is done.
After the overload condition is removed, normal operation can be resumed in two ways,
according to the OLR I²C bit on the DATA 4 register.
If OLR=1, all VSEL 1..4 bits are reset to “0” and LNB output (V
enable output stage, the VSEL bits must be set again by the microprocessor, and the OLF
bit is reset to “0” after a register reading operation.
If OLR=0, output is automatically re-enabled as soon as the overload condition is removed,
and the OLF bit is reset to “0” after a register reading operation.

time (90 ms or 180 ms typ., according to the TIMER bit

ON

and TON. At the end of a full TON in which no overload is

OFF

+T

ON

time is 990 ms (if TIMER=0) or 1080 ms (if

OFF

pin) is disabled. To re-

OUT

OFF

2.21 OTF: thermal protection and diagnostic

The LNBH25 is also protected against overheating: when the junction temperature exceeds
150 °C (typ.), the step-up converter and the linear regulator are shut off, the diagnostic OTF
bit in the STATUS1 register is set to “1” and the FLT pin is set to low level. After the
overtemperature condition is removed, normal operation can be resumed in two ways,
according to the THERM I²C bit on the DATA 4 register.
If THERM=1, all VSEL 1..4 bits are reset to “0” and LNB output (V
enable output stage, the VSEL bits must be set again by the microprocessor, while the OTF
bit is reset to “0” after a register reading operation.
If THERM=0, output is automatically re-enabled as soon as the overtemperature condition is
removed, while the OTF bit is reset to “0” after a register reading operation.

10/34 Doc ID 022433 Rev 4

pin) is disabled. To re-

OUT

LNBH25 Pin configuration

3 Pin configuration

Figure 5. Pin connections (top view)

192021222324

192021222324

DSQIN/

DSQOUTNC

DSQOUTNC

DSQIN

EXTM

VUP

VUP

VOUT

VOUT

DETIN

DETIN

NC

1

NC

1

FLT

2

FLT

2

LX- A

3

LX

3

PGND

4

PGND

4

5

5

NC

NC

ADDR NC

6

ADDR NC

6

SDA ISEL NCNC

SCL

SDA ISEL NCNC

SCL

7 8 9 121110

7 8 9 121110

NC

NC

Table 2. Pin description

Pin n° Symbol Name Pin function

Open drain output for IC fault conditions. It is set low in case of

2FLT FLT

3 LX N-MOS drain Integrated N-channel Power MOSFET drain.

overload (OLF bit) or overheating status (OTF bit) or power not good
(PNG) is detected. To be connected to pull-up resistor (5 V max.).

BPSW

BPSW

VCC

VCC

VBYP

VBYP

GND

GND

NC

NC

AM09909v 1

18

18

17

17

16

16

15

15

14

14

13

13

4 P-GND Power ground

6 ADDR Address setting

DC-DC converter power ground. To be connected directly to the
Epad.

Two I²C bus addresses available by setting the address pin level
voltage. See

Ta bl e 16

.

7 SCL Serial clock Clock from I²C BUS.

8 SDA Serial data Bi-directional data from/to I²C BUS.

The resistor “RSEL” connected between ISEL and GND defines the

9 ISEL Current selection

linear regulator current limit threshold. Refer to
Application Information section. Also see the ISET bit description in

Section 2.6

in the

Tab l e 9.

15 GND Analog ground Analog circuits ground. To be connected directly to the Epad.

Needed for internal pre-regulator filtering. The BYP pin is intended

16 BYP Bypass capacitor

only to connect an external ceramic capacitor. Any connection of
this pin to external current or voltage sources may cause permanent
damage to the device.

17 V

CC

Supply input 8 to 16 V IC DC-DC power supply.

Doc ID 022433 Rev 4 11/34

Pin configuration LNBH25

Table 2. Pin description (continued)

Pin n° Symbol Name Pin function

To be connected to an external transistor to be used to bypass the

18 BPSW Switch control

output RL filter needed in DiSEqC 2.x applications during the
DiSEqC transmitting mode (see

Section 5

). Set to ground if not

used. Open drain pin.

19 DETIN

20 V

21 V

OUT

UP

Tone detector

LNB output port

Step-up voltage

DSQIN for

DiSEqC envelope

22 DSQIN

External 22 kHz

TTL input

23 DSQOUT DiSEqC output

Epad Epad Exposed pad

1, 5, 10, 11,

12, 13, 14, 24

N.C.

Not internally

connected

input

input

or

22 kHz tone decoder input open drain pin, must be AC coupled to
the DiSEqC 2.0 bus. Set to ground if not used.

Output of the integrated very low drop linear regulator. See

Ta bl e 1 4

for voltage selections and description.

Input of the linear post-regulator. The voltage on this pin is
monitored by the internal step-up controller to keep a minimum
dropout across the linear pass transistor.

It can be used as DiSEqC envelope input or external 22 kHz TTL
input depending on the EXTM I²C bit setting as follows:

EXTM=0, TEN=1: it accepts the DiSEqC envelope code from the
main microcontroller. The LNBH25 uses this code to modulate the
internally generated 22 kHz carrier.

If EXTM=TEN=1: it accepts external 22 kHz logic signals which
activate the 22 kHz tone output (refer to

Section 2.3

).

Pull-up high if the tone output is activated only by the TEN I²C bit.

Open drain output of the tone detector to the main microcontroller
for DiSEqC 2.0 data decoding. It is low when tone is detected to the
DETIN input pin. Set to ground if not used.

To be connected with power grounds and to the ground layer
through vias to dissipate the heat.

Not internally connected pins. These pins can be connected to GND
to improve thermal performances.

12/34 Doc ID 022433 Rev 4

LNBH25 Maximum ratings

4 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

V

I

OUT

V

V

V

BPSW

V

DETIN

CC

UP

OUT

V

I

O

DC power supply input voltage pins -0.3 to 20 V

DC input voltage -0.3 to 40 V

Output current Internally limited mA

DC output pin voltage -0.3 to 40 V

Logic input pins voltage (SDA, SCL, DSQIN, ADDR pins) -0.3 to 7 V

I

Logic output pins voltage (FLT, DSQOUT) -0.3 to 7 V

O

BPSW pin voltage -0.3 to 40 V

Detector input signal amplitude -0.6 to 2 V

Logic output pins current (FLT, DSQOUT, BPSW) 10 mA

LX LX input voltage -0.3 to 30 V

V

BYP

Internal reference pin voltage -0.3 to 4.6 V

ISEL Current selection pin voltage -0.3 to 3.5 V

T

STG

T

ESD

Storage temperature range -50 to 150 °C

Operating junction temperature range -25 to 125 °C

J

ESD rating with human body model (HBM) all pins, unless power output
pins

2

ESD rating with human body model (HBM) for power output pins 4

kV

Table 4. Thermal data

Symbol Parameter Value Unit

thJC Thermal resistance junction-case 2 °C/W

R

thJA

R

Thermal resistance junction-ambient with device soldered on 2s2p 4­layer PCB provided with thermal vias below exposed pad.

40 °C/W

Note: Absolute maximum ratings are those values beyond which damage to the device may occur.

These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to network ground terminal.

Doc ID 022433 Rev 4 13/34

Typical application circuits LNBH25

V

X

t

A

A

V

r

5 Typical application circuits

Figure 6. DiSEqC 1.x application circuit

D2

to LNB

21

Vup

D1

L1

C3

C2

3

L

LNBH25

Vou

20

C5

D3

in

12V

DiSEqC

22KHz TTL

DiSEqC

Envelope TTL

C1

o

R1 (RSEL)

C4

I2C Bus

cc

17

DSQIN

22

ADDR

6

8

SD

{

2

7

SCL

ISEL

9

P-GND

4

-

GND

FLT

16

Byp

15

C7

Table 5. DiSEqC 1.X bill of material

Component Notes

R1 (RSEL) SMD resistor. Refer to

Ta bl e 1 3

C1, C2 > 25 V electrolytic capacitor, 100 µF is suitable.

C3 From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise.

C5 From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise.

C4, C7 220 nF ceramic capacitors.

D1 STPS130A or similar schottky diode.

D3

BAT54, BAT43, 1N5818, or any low power schottky diode with I

> 25 V, VF < 0.5 V. To be placed as close as possible to V

V

RRM

D2 1N4001-07, S1A-S1M, or any similar general purpose rectifier.

and ISEL pin description in

Table 2

(AV) > 0.2 A,

F

pin.

OUT

AM10431v1

L1 10 µH inductor with I

sat

> I

peak

where I

is the boost converter peak current.

peak

14/34 Doc ID 022433 Rev 4

LNBH25 Typical application circuits

X

V

r

r

k

Figure 7. DiSEqC 2.x application circuit

D2

21

Vup

D1

L1

Vin
12V

DiSEqC
22KHz TTL

o

DiSEqC
Envelope TTL

C1

R1 (RSEL)

C3

C2

3

C4

I2C Bus

L

cc

17

DSQIN

22

ADDR

6

8

SDA

{

SCL

7

ISEL

9

P -GND A-GND

LNBH25

15

4

Table 6. DiSEqC 2.x bill of material

Component Notes

Vout

BPSW

DETIN

DSQOUT

FLT

Byp

20

D3

C5

18

4.7k

19

Open drains
to µControlle

23

2

16

L2

Ω

15

4.7

C7

TR1

C6

10k

to LNB

AM10432v1

R1 (RSEL) SMD resistors. Refer to

Ta bl e 1 3

and ISEL pin description in

Ta b l e 2

C1, C2 > 25 V electrolytic capacitor, 100 µF is suitable.

C3 From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise.

C5 From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise.

C4, C7 220 nF ceramic capacitors.

C6 10 nF ceramic capacitors.

D1 STPS130A or similar schottky diode.

D3

BAT54, BAT43, 1N5818, or any low power schottky diode with I
V

> 25 V, VF < 0.5 V. To be placed as close as possible to V

RRM

(AV) > 0.2 A,

F

pin.

OUT

D2 1N4001-07, S1A-S1M, or any similar general purpose rectifier.

L1 10 µH inductor with I

sat

> I

peak

where I

is the boost converter peak current.

peak

L2 220 µH inductor.

TR1

2STR2160 or 2STF2340 or any small power PNP with, IC > 250 mA, V
be used.

Also any small power PMOS with ID > 250 mA, R

DSON

< 0.5Ω, V

DS

> 30 V can

CE

> 20 V, can be

used.

Doc ID 022433 Rev 4 15/34

I²C bus interface LNBH25

6 I²C bus interface

Data transmission from the main microprocessor to the LNBH25 and vice versa takes place
through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors
to positive supply voltage must be externally connected).

6.1 Data validity

As shown in
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.

Figure 8

, the data on the SDA line must be stable during the high semi-period

6.2 Start and stop condition

As shown in
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.

Figure 9

, a start condition is a HIGH to LOW transition of the SDA line while

6.3 Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.

6.4 Acknowledge

The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see
must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA
line is stable LOW during this clock pulse. The peripheral which has been addressed has to
generate acknowledge after the reception of each byte, otherwise the SDA line remains at
the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH25 won't generate
acknowledge if the V

supply is below the undervoltage lockout threshold (4.7 V typ.).

CC

Figure 10

). The peripheral (LNBH25) which acknowledges

6.5 Transmission without acknowledge

Avoiding to detect the acknowledges of the LNBH25, the microprocessor can use a simpler
transmission: it simply waits one clock without checking the slave acknowledging, and sends
the new data. This approach is of course less protected from misworking and decreases
noise immunity.

16/34 Doc ID 022433 Rev 4

LNBH25 I²C bus interface

Figure 8. Data validity on the I²C bus

Figure 9. Timing diagram of I²C bus

Figure 10. Acknowledge on the I²C bus

Doc ID 022433 Rev 4 17/34

I²C interface protocol LNBH25

7 I²C interface protocol

7.1 Write mode transmission

The LNBH25 interface protocol comprises:

● a start condition (S)

● a chip address byte with the LSB bit R/W = 0

● a register address (internal address of the first register to be accessed)

● a sequence of data (byte to write in the addressed internal register + acknowledge)

● the following bytes, if any, to be written in successive internal registers

● a stop condition (P). The transfer lasts until a stop bit is encountered

● the LNBH25, as slave, acknowledges every byte transfer.

Figure 11. Example of writing procedure starting with first data address 0x2

CHIP ADDRESS

CHIP ADDRESS

LSB

MSB

MSB

S XX

MSB LSB MSB LSB

MSB LSB MSB LSB

N/A

N/A

N/A

N/A

N/A

N/A

LSB

001000S XX

01000

DATA 1

DATA 1

Add= 0x2

Add= 0x2

VSEL3

VSEL4

VSEL3

VSEL4

N/A

N/A

REGISTER ADDRESS

REGISTER ADDRESS

MSB LSB

MSB LSB

R/W = 0

R/W = 0

ACK

ACK

VSEL1

VSEL2

VSEL1

VSEL2

ACK

ACK

N/A

N/A

N/A

N/A

00X000X

00X000X

DATA 2

DATA 2

Add= 0x3

Add= 0x3

N/A

N/A

N/A

N/A

N/A

ACK

ACK

DATA 3

DATA 3

Add=0x4

Add=0x4

MSB LSB

MSB LSB

TIMER

EXTM

EXTM

ACK

ACK

LPM

TEN

TEN

N/A

N/A

TIMER

PCL

PCL

N/A

N/A

N/A

N/A

N/A

N/A

ACK

ACK

ISW

ISET

DATA 4

DATA 4
Add=0x5

Add=0x5

MSB LSB

MSB LSB

THERM

THERM

COMP

COMP

OLR

N/A

N/A

N/A

N/A

ACK = Acknowledge

S = Start

P = Stop

R/W = 1/0, Read/Write bit

(a)

EN_IMON

ACK

N/A

N/A

ACK

N/A

N/A

P

P

AM09913v2

X = 0/1, set the values to select the CHIP ADDRESS (see Chip Address in
selection) and to select the REGISTER Address (see

a. The writing procedure can start from any Register Address by simply setting the X values in the Register

Address byte (after the Chip Address). It can be also stopped from the master by sending a stop condition after
any acknowledge bit.

18/34 Doc ID 022433 Rev 4

Ta bl e 7

Ta bl e 1 6

for pin

).

LNBH25 I²C interface protocol

7.2 Read mode transmission

In Read mode the bytes sequence must be as follows:

● a start condition (S)

● a chip address byte with the LSB bit R/W=0

● the register address byte of the internal first register to be accessed

● a stop condition (P)

● a new master transmission with the chip address byte and the LSB bit R/W=1

● after the acknowledge the LNBH25 starts to send the addressed register content. As

long as the master keeps the acknowledge LOW, the LNBH25 transmits the next
address register byte content.

● the transmission is terminated when the master sets the acknowledge HIGH with a

following stop bit.

Figure 12. Example of reading procedure starting with first status address 0X0

CHIP ADDRESS

MSB LSB

S XX P00X000X

S XX P00X000X

MSB LSB

MSB LSB

N/A

N/A

N/A

N/A

01000

DATA 1

DATA 1

Add=0x2

Add=0x2

N/A

N/A

N/A

N/A

001000

VSEL4

VSEL4

VSEL3

VSEL2

VSEL3

VSEL2

REGISTER ADDRESS

MSB

R/W = 0

R/W = 0

ACK

ACK

STAT US 1

STAT US 1

Add= 0x0

Add= 0x0

MSB LSB

MSB LSB

PDO

PNG

PDO

PNG

OTF

OTF

N/A

N/A

N/A

N/A

MSB LSB

MSB LSB

VSEL1

VSEL1

ACK

ACK

N/A

N/A

N/A

N/A

N/A

N/A

VMON

VMON

N/A

N/A

DATA 2

DATA 2

Add=0x3

Add=0x3

N/A

N/A

N/A

LSB

ACK

ACK

MSB LSB

MSB LSB

ACK

ACK

OLF

OLF

EXTM

EXTM

N/A

N/A

N/A

N/A

MSB LSB

MSB LSB

ACK

ACK

TEN

TEN

LPM

CHIP ADDRESS

MSB LSB

R/W = 1

R/W = 1

ACK

SX

STAT US 2

STAT US 2

Add=0x1

Add=0x1

TMON

TDET

N/A

N/A

DATA 3

DATA 3

Add= 0x4

Add= 0x4

TIMER

TIMER

N/A

N/A

TDET

N/A

N/A

PCL

PCL

IMON

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

001000SX

01000

ACK

ACK

ACK

ACK

ISET

ISW

ACK

DATA 4

DATA 4
Add=0x5

Add=0x5

MSB LSB

MSB LSB

THERM

THERM

COMP

COMP

N/A

N/A

N/A

N/A

OLR

N/A

N/A

N/A

N/A

EN_IMON

ACK

ACK

(b)

P

P

AM09914v 2

ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the CHIP ADDRESS (see Chip Address in
selection) and to select the REGISTER Address (see

b. The reading procedure can start from any register address (Status 1, 2 or Data1..4) by simply setting the X

values in the register address byte (after the first Chip Address in the above figure). It can be also stopped from
the master by sending a stop condition after any acknowledge bit.

Doc ID 022433 Rev 4 19/34

Ta bl e 7

).

Ta bl e 1 6

for pin

I²C interface protocol LNBH25

7.3 Data registers

The DATA 1..4 registers can be addressed both in write and read mode. In read mode they
return the last writing byte status received in the previous write transmission.

The following tables provide the Register Address values of Data 1..4 and a function
description of each bit.

Table 7. DATA 1 (Read/Write register. Register address = 0X2)

BIT Name Value Description

Bit 0

(LSB)

Bit 1 VSEL2 0/1

Bit 2 VSEL3 0/1

Bit 3 VSEL4 0/1

Bit 4 N/A 0 Reserved. Keep to "0"

Bit 5 N/A 0 Reserved. Keep to "0"

Bit 6 N/A 0 Reserved. Keep to "0"

Bit 7

(MSB)

VSEL1 0/1

Output voltage selection bits. (Refer to

N/A 0 Reserved. Keep to "0"

Ta bl e 1 4

N/A = Reserved bit.

All bits reset to “0” at power-on.

Table 8. DATA 2 (Read/Write register. Register address = 0X3)

BIT Name Value Description

Bit 0

(LSB)

Bit 1 LPM

TEN

1 22 kHz tone enabled. Tone output controlled by DSQIN pin

0 22 kHz tone output disabled

1 Low power mode activated (used only with 22 kHz tone output disabled)

Low power mode deactivated (keep always LPM = 0 during 22 kHz tone

0

transmission)

)

Bit 2 EXTM

Bit 3 N/A 0 Reserved. Keep to “0”

Bit 4 N/A 0 Reserved. Keep to "0"

Bit 5 N/A 0 Reserved. Keep to "0"

Bit 6 N/A 0 Reserved. Keep to "0"

Bit 7

(MSB)

N/A 0 Reserved. Keep to "0"

1 DSQIN input pin is set to receive external 22 kHz TTL signal source

0 DSQIN input pin is set to receive external DiSEqC envelope TTL signal

N/A = Reserved bit.

All bits reset to 0 at power-on.

20/34 Doc ID 022433 Rev 4

LNBH25 I²C interface protocol

Table 9. DATA 3 (Read/Write register. Register address = 0X4)

BIT Name Value Description

Bit 0

(LSB)

ISET

Current limit of LNB output (V

1

Refer to

Current Limit of LNB output (V

0

Refer to

Section 2.6

Section 2.6

in Application Information section.

in Application Information section.

pin) set to lower current range.

OUT

pin) set to default range.

OUT

1 DC-DC, inductor switching current limit set to 2.5 A typ.

Bit 1 ISW

0 DC-DC, inductor switching current limit set to 4 A typ.

1 Pulsed (Dynamic) LNB output current limiting is deactivated

Bit 2 PCL

0 Pulsed (Dynamic) LNB output current limiting is activated

1 Pulsed (Dynamic) LNB output current TON time set to 180 ms typ.

Bit 3 TIMER

0 Pulsed (Dynamic) LNB output current TON time set to 90 ms typ.

Bit 4 N/A 0 Reserved. Keep to "0"

Bit 5 N/A 0 Reserved. Keep to "0"

Bit 6 N/A 0 Reserved. Keep to "0"

Bit 7

(MSB)

N/A 0 Reserved. Keep to "0"

N/A = Reserved bit.

All bits reset to 0 at power-on.

Table 10. DATA 4 (Read/Write register. Register address = 0X5)

BIT Name Value Description

Bit 0

(LSB)

Bit 1 N/A - Reserved

Bit 2 N/A - Reserved

Bit 3 OLR

Bit 4 N/A - Reserved

Bit 5 N/A - Reserved

EN_IMON

1 IMON Diagnostic function is enabled. (V

OUT

0 IMON Diagnostic function is disabled, keep always at “0” if IMON is not used

In case overload protection activation (OLF=1), all VSEL 1..4 bits are reset to “0”

1

and LNB output (V

pin) is disabled. The VSEL bits must be set again by the

OUT

master after the overcurrent condition is removed (OLF=0).

In case of overload protection activation (OLF=1) the LNB output (V
automatically enabled as soon as the overload conditions is removed (OLF=0)

0

with the previous VSEL bits setting.

is set to 21 V typ.)

OUT

pin) is

Doc ID 022433 Rev 4 21/34

I²C interface protocol LNBH25

Table 10. DATA 4 (Read/Write register. Register address = 0X5) (continued)

BIT Name Value Description

If Thermal protection is activated (OTF=1), all VSEL 1..4 bits are reset to “0” and

1

Bit 6 THERM

LNB output (V
after the overtemperature condition is removed (OTF=0).

In case of Thermal protection activation (OTF=1) the LNB output (V

0

automatically enabled as soon as the overtemperature condition is removed
(OTF=0) with the previous VSEL bits setting.

pin) is disabled. The VSEL bits must be set again by the master

OUT

pin) is

OUT

Bit 7

(MSB)

COMP

1 DC-DC converter compensation set to use HIGH ESR capacitors (V

0 DC-DC converter compensation set to use LOW ESR capacitors (V

N/A = Reserved bit.

All bits reset to 0 at power-on.

7.4 Status registers

The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic
functions described in the following tables.

Table 11. STATUS 1 (Read register. Register address = 0X0)

BIT Name Value Description

Bit 0

(LSB)

Bit 1 N/A - Reserved

Bit 2 VMON

Bit 3 N/A - Reserved

OLF

pin overload protection has been triggered (I

V

1

OUT

the overload operation settings (ISET, PCL, TIMER bits).

0 No overload protection has been triggered to the V

Output voltage (V

1

Ta bl e 1 7

.

0 Output voltage (V

pin) lower than VMON specification thresholds. Refer to

OUT

pin) is within the VMON specifications.

OUT

OUT

OUT

> I

MAX

pin (I

UP

UP

). Refer to

< I

OUT

MAX

pin)

pin)

Ta bl e 9

).

for

Overcurrent detected on output pull-down stage for a time longer than the deglitch

1

Bit 4 PDO

period. This may happen due to an external voltage source present on the LNB
output (V

OUT

pin).

0 No overcurrent detected on output pull-down stage.

Bit 5 N/A - Reserved

Junction overtemperature is detected, T

1

Ta bl e 1 0

.

Bit 6 OTF

Junction overtemperature not detected, TJ < 135 °C. TJ is below thermal

0

protection threshold.

Bit 7

(MSB)

PNG

1 Input voltage (VCC pin) lower than LPD minimum thresholds. Refer to

0 Input voltage (VCC pin) higher than LPD thresholds. Refer to

N/A = Reserved bit.

All bits reset to 0 at power-on.

22/34 Doc ID 022433 Rev 4

> 150 °C. See also THERM bit setting in

J

Ta b l e 1 3

Ta bl e 1 3

.

.

LNBH25 I²C interface protocol

Table 12. STATUS 2 (Read register. Register address = 0X1)

BIT Name Value Description

Bit 0

(LSB)

TDET

1 22 kHz tone presence is detected on the DETIN pin

0 No 22 kHz tone is detected on the DETIN pin

Bit 1 N/A - Reserved

22 kHz tone present on the DETIN pin is out of TMON specification thresholds.

1

That is: the tone frequency or the A

Bit 2 TMON

guaranteed in the TMON electrical characteristics table.

22 kHz tone present on the DETIN pin is within TMON specification thresholds.

0

Refer to

Bit 3 N/A - Reserved

Output current (from V

1

Ta bl e 1 8

to

Bit 4 IMON

Output current (from V

0

Ta b l e 1 8

to

Bit 5 N/A - Reserved

Bit 6 N/A - Reserved

Bit 7

(MSB)

N/A - Reserved

N/A = Reserved bit.

All bits reset to 0 at power-on.

Ta bl e 1 9

.

.

(tone Amplitude) are out of the thresholds

TONE

.

pin) is lower than IMON specification thresholds. Refer

OUT

pin) is higher than IMON specifications. Refer

OUT

Doc ID 022433 Rev 4 23/34

Electrical characteristics LNBH25

8 Electrical characteristics

Refer to
RSEL = 11.5 kΩ, DSQIN = LOW, V
values are referred to T
for I²C access to the system register (

Table 13. Electrical characteristics

Section 5

, TJ from 0 to 85 °C, all DATA 1..4 register bits set to 0 unless VSEL1 = 1,

= 25 °C. V

J

= 12 V, I

IN

= V

OUT

Section 6

= 50 mA, unless otherwise stated. Typical

OUT

pin voltage. See software description section

OUT

and

Section 7

).

Symbol Parameter Test conditions Min. Typ. Max. Unit

IN

IN

Supply voltage

Supply current

V

I

(1)

81216V

= 0 mA 6 mA

I

OUT

22 kHz Tone enabled (TEN=1),

DSQIN = High, I

OUT

= 0 mA

10 mA

VSEL1=VSEL2=VSEL3=VSEL4=0 1 mA

V

V

V

OUT

OUT

OUT

Output voltage total accuracy Valid at any V

Line regulation V

Load regulation I

= 8 to 16 V 40

IN

from 50 to 750 mA 100

OUT

selected level -3.5 +3.5 %

OUT

RSEL = 11.5 kΩ, ISET = 0 750 1100

I

MAX

Output current limiting
thresholds

RSEL = 22 kΩ, ISET = 0 350 550

RSEL = 11.5 kΩ, ISET = 1 500

I

MAX

Output current limiting
thresholds

RSEL = 22 kΩ, ISET = 1 250

I

SS Soft-start time V

SS Soft-start time V

T13-18 Soft transition rise time V

T18-13 Soft transition fall time V

T

OFF

T

Output short-circuit current RSEL = 11.5 kΩ, ISET= 0 500 mA

SC

from 0 to 13 V 4 ms

OUT

from 0 to 18 V 6 ms

OUT

from 13 to 18 V 1.5 ms

OUT

from 18 to 13 V 1.5 ms

OUT

Dynamic overload protection
OFF Time

Dynamic overload protection

ON

ON Time

PCL=0, Output Shorted 900

PCL = TIMER = 0, Output Shorted T

PCL = 0, TIMER = 1, Output Shorted T

OFF

OFF

/10

/5

DSQIN=High, EXTM=0, TEN=1

A

TONE

F

D

TONE

TONE

Tone amplitude

Tone frequency

Tone duty cycle 43 50 57 %

tr, tf Tone rise or fall time

Eff

DC/DC

DC-DC converter efficiency I

(2)

I

from 0 to 750 mA

OUT

from 0 to 750 nF

C

BUS

DSQIN=High, EXTM=0, TEN=1

= 500 mA 93 %

OUT

0.55 0.675 0.8 V

20 22 24 kHz

5815µs

mV

mARSEL = 16.2 kΩ, ISET = 0 500 750

mARSEL = 16.2 kΩ, ISET = 1 350

ms

PP

24/34 Doc ID 022433 Rev 4

LNBH25 Electrical characteristics

Table 13. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

F

SW

UVLO

V

V

V

I

IH

F

DETIN

V

DETIN

Z

DETIN

V

OL_BPS

W

V

OL

I

OZ

DC-DC converter switching
frequency

Undervoltage lockout
thresholds

Low power diagnostic (LPD)

LP

thresholds

DSQIN, pin logic low 0.8 V

IL

DSQIN, pin logic high 2 V

IH

DSQIN, pin input current V

Tone detector frequency
capture range

Tone detector input
amplitude

(3)

(3)

UVLO Threshold Rising 4.8

UVLO Threshold Falling 4.7

V

Threshold Rising 7.2

LP

VLP Threshold Falling 6.7

= 5 V 15 µA

IH

0.4VPP sine wave 19 22 25 kHz

Sine wave signal, 22 kHz 0.3 1.5 V

Tone detector input
impedance

BPSW pin low voltage

DSQOUT, FLT pins logic
LOW

DSQOUT, FLT pins leakage
current

I

OL_BPSW

EXTM=0, TEN=1

DETIN Tone present, I

DETIN Tone absent, V

= 5 mA, DSQIN = high,

= 2 mA 0.3 0.5 V

OL

= 6 V 10 µA

OH

440 kHz

150 kΩ

0.7 V

V

V

PP

I

OBK

I

SINK

I

SINK_

TIME-OUT

I

REV

T

SHDN

ΔT

SHDN

1. In applications where (VCC -V
account in the application thermal management design.

2. Guaranteed by design.

3. Frequency range in which the DETIN function is guaranteed. The V
capacitor. See typical application circuit for DiSEqC 2.x). I

Output backward current All VSELx=0, V

Output low-side sink current V

Low-side sink current time­out

Max. reverse current

forced at V

OUT

V

forced at V

OUT

PDO I²C bit is set to 1 after this time
is elapsed

V

forced at V

OUT

after PDO bit is set to 1
(I

SINK_TIME-OUT

Thermal shut-down
threshold

Thermal shut-down
hysteresis

) > 1.3 V the increased power dissipation inside the integrated LDO must be taken into

OUT

OUT

OBK

OUT_NOM

OUT_NOM

OUT_NOM

elapsed)

from 0 to 750 mA, C

= 30 V -3 -6 mA

+ 0.1 V 70 mA

+ 0.1 V

10 ms

+ 0.1 V

2mA

150 °C

15 °C

level is intended on the LNB bus (before the C6

PP

from 0 to 750 nF.

BUS

Doc ID 022433 Rev 4 25/34

Electrical characteristics LNBH25

Table 14. Output voltage selection table (Data1 register, write mode)

VSEL4 VSEL3 VSEL2 VSEL1

0000 0.000

V

V

OUT

min.

pin

OUT

voltage

V

OUT

max.

disabled. LNBH25 set in standby

V

OUT

mode

000112.54513.00013.455

001012.86713.33313.800

001113.18813.66714.145

010013.5114.00014.490

010113.83214.33314.835

011014.15314.66715.180

011114.47515.00015.525

100017.51518.15018.785

100117.83618.48319.130

101018.15818.81719.475

101118.4819.15019.820

110018.80119.48320.165

110119.12319.81720.510

(1)

Function

111019.44520.15020.855

111119.76620.48321.200

1. TJ from 0 to 85 °C, VI = 12 V.

TJ from 0 to 85 °C, VI = 12 V.

Table 15. I²C electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

IL

V

IH

I

IN

V

OL

F

MAX

1. Guaranteed by design.

LOW level input voltage SDA, SCL 0.8 V

HIGH level input voltage SDA, SCL 2 V

Input current SDA, SCL, V

Low level output voltage

(1)

SDA (open drain), IOL = 6 mA 0.6 V

= 0.4 to 4.5 V -10 10 µA

IN

Maximum clock frequency SCL 400 kHz

26/34 Doc ID 022433 Rev 4

LNBH25 Electrical characteristics

TJ from 0 to 85 °C, VI = 12 V.

Table 16. Address pin characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

V

ADDR-1

V

ADDR-2

“0001000(R/W)” Address pin
voltage range

“0001001(R/W)” Address pin
voltage range

Refer to
DSQIN = LOW, V
referred to T

Section 5

= 25 °C. V

J

, TJ from 0 to 85°C, All DATA 1..4 register bits set to “0”, RSEL = 11.5 kΩ,

= 12 V, I

IN

R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)

R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)

= 50 mA, unless otherwise stated. Typical values are

OUT

OUT

= V

pin voltage. See software description section for I²C

OUT

00.8V

25V

access to the system register.

Table 17. Output voltage diagnostic (VMON bit, STATUS 1 register) characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

V

TH-L

V

TH-L

Diagnostic low threshold at

= 13.0 V

V

OUT

Diagnostic low threshold at

= 18.15 V

V

OUT

VSEL1=1,
VSEL2 = VSEL3 = VSEL4 = 0

VSEL4=1,
VSEL1 = VSEL2 = VSEL3 = 0

80 90 95 %

80 90 95 %

Note: If the output voltage is lower than the min. value the VMON I²C bit is set to 1.

If VMON=0 then V

If VMON=1 then V

Refer to

Section 5

otherwise stated. Typical values are referred to T

> 80 % of V

OUT

< 95 % of V

OUT

OUT

OUT

typical

typical

, TJ from 0 to 85 °C, RSEL = 11.5 kΩ, DSQIN = LOW, VIN = 12 V, unless

= 25 °C. V

J

OUT

= V

pin voltage. See

OUT

software description section for I²C access to the system register.

Table 18. Output current diagnostic (IMON bit, STATUS 2 register) characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

I

Minimum current diagnostic

TH

threshold

EN_IMON = 1 (V

is set to 21 V typ.) 5 12 20 mA

OUT

Note: If the output current is lower than the min. threshold limit, the IMON I²C bit is set to 1. If the

output current is higher than the max. threshold limit, the IMON I²C bit is set to 0.

Doc ID 022433 Rev 4 27/34

Electrical characteristics LNBH25

Refer to
VSEL1 = 1, TEN=1, RSEL = 11.5 kΩ, DSQIN = HIGH, V
otherwise stated. Typical values are referred to T

Section 5

, TJ from 0 to 85 °C, All DATA 1..4 register bits set to “0” unless

= 25 °C. V

J

= 12 V, I

IN

OUT

= 50 mA, unless

OUT

= V

pin voltage. See

OUT

software description section for I²C access to the system register.

Table 19. 22 kHz tone diagnostic (TMON bit, STATUS 2 register) characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

A

TH-L

A

TH-H

F

TH-L

F

TH-H

Amplitude diagnostic low threshold DETIN pin AC coupled 200 300 400 mV

Amplitude diagnostic high
threshold

Frequency diagnostic low
thresholds

Frequency diagnostic high
thresholds

DETIN pin AC coupled 900 1100 1200 mV

DETIN pin AC coupled 13 16.5 20 kHz

DETIN pin AC coupled 24 29.5 38 kHz

Note: If the 22 kHz Tone parameters are lower or higher than the above limits, the TMON I²C bit is

set to “1”.

28/34 Doc ID 022433 Rev 4

LNBH25 Package mechanical data

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK
specifications, grade definitions and product status are available at:

packages, depending on their level of environmental compliance. ECOPACK

www.st.com

. ECOPACK

is an ST trademark.

Table 20. QFN24L (4 x 4 mm) mechanical data

(mm)

Dim.

Min. Typ. Max.

A 0.80 0.90 1.00

A1 0.00 0.02 0.05

b 0.18 0.25 0.30

D 3.90 4.00 4.10

D2 2.55 2.70 2.80

E 3.90 4.00 4.10

E2 2.55 2.70 2.80

e 0.45 0.50 0.55

L 0.25 0.35 0.45

Doc ID 022433 Rev 4 29/34

Package mechanical data LNBH25

Figure 13. QFN24L (4 x 4 mm) package dimensions

30/34 Doc ID 022433 Rev 4

7596209_D

LNBH25 Package mechanical data

Tape & reel QFNxx/DFNxx (4x4) mechanical data

mm. inch.

Dim.

Min. Typ. Max. Min. Typ. Max.

A 330 12.992

C 12.8 13.2 0.504 0.519

D 20.2 0.795

N 99 101 3.898 3.976

T 14.4 0.567

Ao 4.35 0.171

Bo 4.35 0.171

Ko 1.1 0.043

Po 4 0.157

P 8 0.315

Doc ID 022433 Rev 4 31/34

Package mechanical data LNBH25

Figure 14. QFN24L (4 x 4) footprint recommended data (mm.)

32/34 Doc ID 022433 Rev 4

LNBH25 Revision history

10 Revision history

Table 21. Document revision history

Date Revision Changes

09-Nov-2011 1 Initial release.

01-Dec-2011 2

13-Jan-2012 3 Modified: header

15-Feb-2012 4 Modified: D1, D3

Updated mechanical data
Added

Section 2.9

Table 20 on page 29

and

Figure 4 on page 8

Table 14 on page 26

Table 5 on page 14

and

Table 13 on page 30

.

and test condition

and

Table 6 on page 15

.

Table 17 on page 27

.

.

Doc ID 022433 Rev 4 33/34

LNBH25

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34/34 Doc ID 022433 Rev 4