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LMX5080 PLLatinum 2.7 GHz Low Power Dual Modulus Prescaler for RF Personal
Communications
LMX5080
PLLatinum
™
2.7 GHz Low Power Dual Modulus
Prescaler for RF Personal Communications
General Description
The LMX5080 integrated dual modulus prescaler, is designed to be used in a synthesized local oscillator for
2.5 GHz wireless transceivers. It is fabricated using National’s 0.5µABiCV silicon BiCMOS process. The LMX5080 contains three dual modulus prescalers. Either a 128/130,
256/158 or a 512/514 prescaler can be selected for up to
2.7 Gz RF input frequencies. The prescaler inputs can be
driven either differentially, or single ended with the use of a
coupling capacitor on one of the inputs to ground. The
LMX5080 CMOS output is optimized to generate very stable,
low switching noise output signals. The LMX5080 prescaler
can be used in conjunction with a low frequency Phase Lock
Loop to form a frequency synthesizer suitable for UHF transceivers. Supply voltage can range from 2.7V to 5.5V. The
LMX5080 features low current consumption; typically 7.0 mA
at 5V V
CC
The LMX5080 is available in a 8-pin Small Outline (SOP)
surface mount plastic package.
Functional Block Diagram
Features
n 2.7V to 5.5V operation
n Low current consumption: 7 mA (typ)
n −40˚C to +85˚C low noise CMOS output
n Selectable dual modulus prescaler
128/130
256/258
512/514
n 8-pin small package outline (SOP)
Applications
n 2.5 GHz wireless communications systems (ISM)
n Direct Broadcast Satellite systems (DBS)
n Cable TV tuners (CATV)
PRELIMINARY
April 1999
@
5V
DS100940-1
PLLatinum™is a trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100940 www.national.com
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Connection Diagram
Small Outline Package (SOP)
DS100940-2
NS Package Number M08A
Order Number LMX5080M, LMX5080MX
Pin Descriptions
Pin
No.
1 IN I RF small signal prescaler input. Small signal input from the voltage controlled
2V
3 SW1 I Divide Ratio Control. CMOS logic input. Pin functionality is described in the
4 OUT O Prescaler Output. CMOS level output for connection to low frequency PLL
5 GND — Ground for analog and digital signals.
6 MC I Modulus Control Input. High impedance CMOS logic input. Pin functionality is
7 SW2 I Divide Ratio Control. High impedance CMOS logic input. Pin functionality is
8IN
Pin
Name
CC
I/O Description
oscillator
— Power Supply voltage input may range from 2.7V to 5.5V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly
to the ground plane.
Modulus Control Truth Table.
input.
described in the Modulus Control Truth Table.
described in the Modulus Control Truth Table.
I RF small signal prescaler complementary input. In single-ended mode, a
bypass capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane. The IN and IN can be driven
differentially when the bypass capacitor is omitted.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Recommended Operating
Conditions
Distributors for availability and specifications.
Parameter Symbol
Power Supply
Voltage V
Operating
Temperature T
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur. Recommended Operating Conditions indicate conditions for which the deviceisintendedtobe functional, but do not guarantee
specific performance limits. Electrical Characteristics document specific minimum and/or maximum performance values at specified test conditions and
are guaranteed. Typ or Typical values are for informational purposes only
which are based on design parameters or device characterization and are not
guaranteed.
Note 2: This device is a high performance RF integrated circuit and is ESD
sensitive. Handling and assembly of this device should only be done on ESDfree workstations.
Parameter Symbol
Power Supply
Voltage V
Voltage on any
pin with
GND=0V V
Storage
Temperature
Range T
Lead Temp.
(solder 4 sec) T
Value
−0.3 6.5 V
CC
−0.3 VCC+0.3 V
i
−65 +1.50 ˚C
S
L
UnitsMin Typ Max
+2.60 ˚C
Electrical Characteristics
(VCC= 5.0V, T
Symbol Parameter Condition
I
CC
V
OH
V
OL
f
in
Pf
in
f
out
V
IH
V
IL
I
IH
I
IL
t
Set
IM Input/Output Intermodulation (Note 4) −10 dBm / 50Ω AC coupled
Note 3: See Timing Diagram.
Note 4: Guaranteed by design and characterization, not tested. Output frequency measured at input.
=
−40˚C to +85˚C except as specified) (Note 1)
A
Power Supply Current 7mA
Output Amplitude Z
Input Frequency AC coupled. V
Operational Input Signal Amplitude V
=
100 kΩ//10 pF
L
=
2.7V to 5.5V
V
CC
=
2.7V to 5.5V 100 2700 MHz
=
CC
CC
2.7V to 5.5V −15 +4 dBm
Output Frequency 0.1 25 MHz
High-level Input Voltage (MC, SW1,
SW2)
Low-level Input Voltage (MC, SW1,
SW2)
High-level Input Current (MC, SW1,
SW2)
Low-level Input Current (MC, SW1,
SW2)
=
V
0.7xV
IH
=
V
IL
0.3xV
CC
CC
Modulus Control Set-up time. (Note 3) SW1=H, SW2=H
=
2.7 GHz
f
in
signal delivered to input.
=
2.7V to 5.5V.
V
CC
MC=0, MC=1.
Fin=2.3 GHz to 2.5 GHz.
(Note 1)
2.7 5.5 V
CC
−40 +85 ˚C
A
Value
Min Typ Max
0.9xV
CC
0.7xV
CC
±
±
15 20 ns
−35 −30 dBc
Value
UnitsMin Typ Max
Units
V
0.1xV
V
CC
V
0.3xV
V
CC
1uA
1uA
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Functional Description
The basic phase-lock-loop (PLL) configuration using an external prescaler consists of a high-stability crystal reference
oscillator, a prescaler such as the National Semiconductor
LMX5080, a low frequency synthesizer, a voltage controlled
oscillator (VCO), and a loop filter. The frequency synthesizer
typically includes programmable reference [R] and feedback
[N] frequency dividers, a phase detector, as well as a charge
pump. The MC signal is fed back to the prescaler from either
Block Diagram
the low frequency synthesizer, or a controller to set the prescaler divide ratio to N or N+2. The prescaler output frequency is established by dividing the VCO signal down via
the prescaler modulus. The RF inputs to the prescalar consist of the Fin and /Fin input pins which are complementary
inputs to a differential pair amplifier. This configuration can
operate to 2 GHz with an input sensitivity of −15 dBm.
DS100940-3
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Modulus Control Truth Table
SW1 SW2 MC Divide Ratio
H H H 1/128
H H L 1/130
H L H 1/256
L H H 1/256
H L L 1/258
L H L 1/258
L L H 1/512
L L L 1/514
Note: SW1, SW2, MC: H=0.7xVCC,L=0.3xVCC.
Timing Diagram
DS100940-4
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Typical Performance Characteristics
ICCvs V
CC
N=1/128, T
=
25˚C
A
RF Input Sensitivity vs Frequency
Input Impedance (S11) vs Frequency
=
V
2.7V to 5.5V, f
CC
Marker 1=100 MHz, Real=364, I
Marker 2=1 GHz, Real=104, I
Marker 3=2 GHz, Real=26, I
Marker 4=2.7 GHz, Real=36, I
=
100 MHz to 2.7 GHz
in
=
−253
mag
=
−136
mag
=
−53
mag
=
−23
mag
DS100940-7
DS100940-6
DS100940-8
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Physical Dimensions inches (millimeters) unless otherwise noted
LMX5080 PLLatinum 2.7 GHz Low Power Dual Modulus Prescaler for RF Personal
Communications
8 Lead (0.150” Wide) Molded Small Outline Package, JEDEC
Order Number LMX5080M
For Tape and Reel
Order Number LMX5080MX
NS Package Number M08A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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whose failure to perform when properly used in
accordance with instructions for use provided in the
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support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
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