Page 1
LMX3161
Single Chip Radio Transceiver
General Description
The LMX3161 Single Chip Radio Transceiverisamonolithic,
integrated radio transceiver optimized for use in a Digital Enhanced Cordless Telecommunications (DECT) system. It is
fabricated using National’s ABiC V BiCMOS process
=
(f
18 GHz).
T
The LMX3161 contains phase locked loop (PLL), transmit
and receive functions. The 1.1 GHz PLL block is shared between transmit and receive section. The transmitter includes
a frequency doubler, and a high frequency buffer. The receiver consists of a 2.0 GHz lownoisemixer,anintermediate
frequency (IF) amplifier, a high gain limiting amplifier, a frequency discriminator, a received signal strength indicator
(RSSI), and an analog DC compensation loop. The PLL,
doubler, and buffers can be used to implement open loop
modulation along with an external VCO and loop filter. The
circuit features on-chip voltage regulation to allow supply
voltages ranging from 3.0V to 5.5V. Two additional voltage
regulators provide a stable supply source to external discrete stages in the Tx and Rx chains.
The IF amplifier, high gain limiting amplifier, and discriminator are optimized for 110 MHz operation, with a total IF gain
of 85 dB. The single conversion receiver architecture pro-
LMX3161 Single Chip Radio Transceiver
PRELIMINARY
November 1999
vides a low cost, high performance solution for communications systems. The RSSI output may be used for channel
quality monitoring.
The Single Chip Radio Transceiver is available in a 48-pin
7mm X 7mm X 1.4mm PQFP surface mount plastic package.
Features
n Single chip solution for DECT RF transceiver
n RF sensitivity to −93 dBm; RSSI sensitivity to −100 dBm
n Two regulated voltage outputs for discrete amplifiers
n High gain (85 dB) intermediate frequency strip
n Allows unregulated 3.0V–5.5V supply voltage
n Power down mode for increased current savings
n System noise figure 6.5 dB (typ)
Applications
n Digital Enhanced Cordless Telecommunications (DECT)
n Personal wireless communications (PCS/PCN)
n Wireless local area networks (WLANs)
n Other wireless communications systems
Block Diagram
DS012815-1
MICROWIRE™is a trademark of National Semiconductor Corporation.
®
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012815 www.national.com
Page 2
LMX3161 Pin Diagram
LMX3161
DS012815-2
Top View
Order Number LMX3161VBH or LMX3161VBHX
See NS Package Number VBH48A
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Page 3
LMX3161 Pin Diagram (Continued)
Pin No. Pin Name I/O Description
1V
2 MIXER
3V
CC
OUT
CC
4 GND — Ground.
5RF
IN
6 GND — Ground.
7TxV
8V
REG
CC
9 GND — Ground.
10 Tx
OUT
11 GND — Ground.
12 V
CC
13 GND — Ground.
14 GND — Ground.
15 f
IN
16 CE I Chip Enable. Pulling LOW powers down entire chip. Taking CE HIGH powers up the
17 V
18 D
19 V
P
o
CC
20 GND — Ground.
21 OUT 0 O Programmable CMOS output. Refer to Function Register Programming Description section
22 Rx PD/OUT 1 I/O Receiver power down control input or programmable CMOS output. Refer to Function
23 Tx PD/OUT 2 I/O Transmitter power down control input or programmable CMOS output. Refer to Function
24 PLL PD I PLL power down control input. LOW for PLL normal operations, and HIGH for PLL power
25 CLOCK I MICROWIRE
26 DATA I MICROWIRE data input. High impedance CMOS input with Schmitt Trigger.
27 LE I MICROWIRE load enable input. High impedance CMOS input with Schmitt Trigger.
28 OSC
IN
29 S FIELD
30 RSSI
OUT
31 THRESH O Threshold level to external comparator.
32 DC COMP
33 DISC
OUT
34 GND — Ground.
35 V
CC
36 QUAD
37 V
CC
38 GND — Ground.
39 V
CC
40 GND — Ground.
41 V
CC
— Power supply for CMOS section of PLL and ESD bussing.
O IF output from the mixer.
— Power supply for mixer section.
I RF input to the mixer.
— Regulated power supply for external PA gain stage.
— Power supply for analog sections of PLL and doubler.
O Frequency doubler output.
— Power supply for analog sections of PLL and doubler.
I RF Input to PLL and frequency doubler.
appropriate functional blocks depending on the state of bits F6, F7, F11, and F12
programmed in F-latch. It is necessary to initialize the internal registers once, after the
power up reset. The registers’ contents are kept even in power-down condition.
— Power supply for charge pump.
O Charge pump output. For connection to a loop filter for driving the input of an external VCO.
— Power supply for CMOS section of PLL and ESD bussing.
for details.
Register Programming Description section for details.
Register Programming Description section for details.
saving.
™
clock input. High impedance CMOS input with Schmitt Trigger.
I Oscillator input. High impedance CMOS input with feedback.
I DC compensation circuit enable. While LOW, the DC compensation circuit is enabled and
the threshold is updated through the DC compensation loop. While HIGH, the switch is
opened, and the comparator threshold is held by the external capacitor.
O Received signal strength indicator (RSSI) output.
I Input to DC compensation circuit.
IN
O Demodulated output of discriminator.
— Power supply for the discriminator circuit.
IN
I Quadrature input for tank circuit.
— Power supply for limiter output stage.
— Power supply for limiter gain stages.
— Power supply for IF amplifier gain stages.
LMX3161
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Page 4
LMX3161 Pin Diagram (Continued)
Pin No. Pin Name I/O Description
LMX3161
42 LIM
IN
43 GND — Ground.
44 IF
45 V
OUT
CC
46 GND — Ground.
47 IF
48 Rx V
IN
REG
I IF input to the limiter.
O IF output from IF amplifier.
— Power supply for IF amplifier output.
I IF input to IF amplifier.
— Regulated power supply for external LNA stages.
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Page 5
Absolute Maximum Ratings (Notes 1, 2)
Power Supply Voltage (V
V
P
Voltage on Any Pin with
GND=0V (V
) −0.3V to VCC+0.3V
I
Storage Temperature Range (T
Lead Temp. (solder, 4 sec)(T
) −0.3V to +6.5V
CC
−0.3V to +6.5V
) −65˚C to +150˚C
S
) +260˚C
L
Recommended Operating
Conditions
Supply Voltage (VCC) 3.0V to 5.5V
Operating Temperature (T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics section. The guaranteed specifications apply only for the test conditions listed.
Note 2: This device is a high performance RFintegrated circuit with an ESD
<
KeV and is ESD sensitive. Handling and assembly of this device
rating
should only be done at ESD work stations.
)V
(V
P
) −10˚C to +70˚C
A
CC
to 5.5V
Electrical Characteristics
The following specifications are guaranteed for V
CC
=
3.6V and T
Symbol Parameter Conditions Min Typ Max Unit
Current Consumption
I
DD, RX
I
DD, TX
I
DD, PLL
I
PD
MIXER f
f
RF
f
IF
Z
Z
-Open-Loop Receive Mode PLL & TX chain powered down — 50 60 mA
-Open-Loop Transmit Mode PLL & RX chain powered down — 27 37 mA
-Closed-Loop PLL Mode RX & TX chain powered down — 6 8 mA
-Power Down Mode — — 70 µA
=
RF
RF Frequency Range (Note 3) 1.7 — 2.0 GHz
IF Frequency (Note 4) — 110 — MHz
Input Impedance, RF
IN
Output Impedance, Mixer Out —
OUT
IN
NF Noise Figure (Single Side Band) (Notes 5, 6) — 10 14 dB
G
P
Conversion Gain (Note 5) 14 17 — dB
C
Input 1dB Compression Point (Note 5) −24 −20 — dBm
1dB
OIP3 Output 3rd Order Intercept Point (Note 5) — 7.5 — dBm
F
-RF Fin to RF Isolation F
IN
F
-IF Fin to IF Isolation f
IN
RF–IF RF to IF Isolation P
IF AMPLIFIER f
=
890 MHz — −30 — dB
IN
=
f
1780 MHz — −10.6 — dB
IN
=
f
2670 MHz — −30 — dB
IN
=
890 MHz — −30 — dB
IN
=
f
1780 MHz — −30 — dB
IN
=
f
2670 MHz — −30 — dB
IN
=
0 to −85 dB — −30 — dB
IN
=
110 MHz
IN
NF Noise Figure (Note 7) — 8 11 dB
A
Z
Z
IF LIMITER f
Gain (Note 7) 15 24 — dB
V
Input Impedance —
IN
Output Impedance —
OUT
IN
=
110 MHz
Sens Limiter/Discriminator Sensitivity BER=10
IF
DISCRIMINATOR f
IF Limiter Input Impedance —
IN
IN
=
110 MHz
Disc Gain 1X Mode — 10 — mV/˚
(mV/˚ of Phase Shift from Tank Circuit) 3X Mode — 33 — mV/˚
V
Discriminator Output Peak to Peak 1X Mode (Note 8) 80 160 — mV
OUT
Voltage 3X Mode (Note 8) 400 580 — mV
V
DISC
Disc. Output DC Voltage Nominal (Note 10) 1.2 1.82 V
OS
Disc. Output Impedance — 300 — Ω
OUT
A
1.89 GHz, f
−3
=
25˚C, unless otherwise specified.
=
IF
110 MHz, f
=
LO
1780 MHz (f
=
890 MHz)
IN
15-j5
—
160-j70
150–j120
190–j20
— Ω
— Ω
— Ω
— Ω
— −65 — dBm
100–j300
— Ω
LMX3161
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Page 6
Electrical Characteristics (Continued)
The following specifications are guaranteed for V
LMX3161
Symbol Parameter Conditions Min Typ Max Unit
RSSI (Note 11) f
RSSI
Output Voltage P
out
Slope P
RSSI Dynamic Range P
=
3.6V and T
CC
=
110 MHz
IN
=
−80 dBm
IN
=
P
−20 dBm
IN
=
−90 to −30 dBm
IN
min=−90 dBm@LIMINinput pin — 60 — dB
IN
DC COMPENSATION CIRCUIT
V
V
R
FREQUENCY SYNTHESIZER P
f
IN
P
f
OSC
V
I
Do-source
I
Do-sink
I
Do-source
I
Do-sink
I
Do-Tri
FREQUENCY DOUBLER f
f
OUT
P
Z
Input Offset Voltage −5 — +5 mV
OS
Input/Output Voltage Swing Centered at 1.5V — 1.0 — V
I/O
Sample and Hold Resistor 2000 3000 3600 Ω
SH
=
IN
Input Frequency Range (Note 9) 500 — 1200 MHz
Input Signal Level Z
IN
=
200Ω (Note 15) — −11.5 — dBm
IN
Oscillator Frequency Range (Note 12) 5 — 20 MHz
Oscillator Sensitivity (Note 12) 0.5 1.0 — V
OSC
Charge Pump Output Current V
=
do
(Note 14)
=
V
do
(Note 14)
=
V
do
(Note 14)
=
V
do
(Note 14)
0.5 ≤ Vdo≤ Vp− 0.5
=
25˚C
T
A
=
945 MHz, f
IN
Output Frequency Range (Note 13) 1770 — 1900 MHz
Output Signal Level P
OUT
Fundamental Output Power P
Harmonic Output Power P
Output Impedance TX chain powered up — 25+j60 — Ω
OUT
=
IN
=
IN
=
IN
TX chain powered down — 15-j30 — Ω
VOLTAGE REGULATOR
V
Output Voltage I
O
LOAD
DIGITAL INPUT/OUTPUT PINS
V
V
I
IH
V
V
High Level Input Voltage 2.4 — V
IH
Low Level Input Voltage 0.0 — 0.8 V
IL
Input Current GND<V
High Level Output Voltage I
OH
Low Level Output Voltage I
OL
Note 3: The mixer section is tested at 1.89 GHz, and it is guaranteed by design to operate within 1.7 — 2.0 GHz range.
Note 4: The IF section of this device is designed for optimum operating performance at 110 MHz to meet the DECT specifications.
Note 5: The matching network used on RF
nH inductance and a shunt 12 pF capacitance into the pin.
Note 6: Noise Figure measurements are made with 890 MHz BPF on the F
Note 7: The matching network used on IF
Note 8: The discriminator is with the DC level centered at 1.5V. The unloaded Q of the tank is 40.
Note 9: The frequency synthesizer section is guaranteed by design to operate within 500 - - 1200 MHz range.
Note 10: Nominal refers to zero DC offsets programmed for the discriminator.
Note 11: It depends on loss of inter-stage filter. These specifications are for an inter-stage filter with a loss of 8 dB.
Note 12: The frequency synthesizer section is guaranteed by design to operate for OSC
.
V
pp
consists of a series 3.3 pF capacitance into the pin. The matching circuit used on MIXER
IN
consists of a series 33 nH inductance and a shunt 1.8 pF capacitance into the pin.
IN
=
−0.5 mA 2.4 — — V
OH
=
0.5 mA — — 0.4 V
OL
=
25˚C, unless otherwise specified.
A
@
IFINinput pin 0.12 0.2 0.6 V
@
IFINinput pin 0.9 1.2 — V
@
LIMINinput pin 11 18 25 mV/d
−14 to −9 dBm
V
P
V
P
V
P
V
P
/2, I
/2, I
/2, I
cpo
cpo
cpo
CPO
=
=
LOW
LOW
HIGH
=
HIGH
— −1.5 — mA
— 1.5 — mA
— −6.0 — mA
— 6.0 — mA
=
/2, I
−1.0 — 1.0 nA
=
1.89 GHz
OUT
−11.5 dBm, f
−11.5 dBm, f
−11.5 dBm, f
=
5 mA 2.55 2.75 2.90 V
<
IN
input and matching networks on RFINand MIXER
IN
=
1.89 GHz −10 −3 — dBm
OUT
=
945 MHz — −22 −13.5 dBm
OUT
=
2.835 GHz — −24 −15 dBm
OUT
CC
V
CC
input frequency within 5 — 20 MHz range and minimun amplitude of 0.5
IN
−10 — 10 µA
consists of a series 100
OUT
.
OUT
B
PP
pp
V
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Page 7
Electrical Characteristics (Continued)
Note 13: The doubler section is tested at 1.89 GHz, and it is guaranteed by design to operate within 1.7 — 1.9 GHz range.
Note 14: See Function Register Programming Description for Icp
Note 15: Tested in a 50Ω environment.
description.
o
AC Timing Characteristics
Serial Data Input Timing
TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has
an skew rate of 0.6V/ns.
LMX3161
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
DS012815-3
Symbol Parameter Conditions Min Typ Max Unit
MICROWIRE
t
CS
t
CH
t
CWH
t
CWL
t
ES
t
EW
™
Interface
Data to Clock Set Up Time Refer to Test Condition. 50 — — ns
Data to Clock Hold Time Refer to Test Condition. 10 — — ns
Clock Pulse Width High Refer to Test Condition. 50 — — ns
Clock Pulse Width Low Refer to Test Condition. 50 — — ns
Clock to Load Enable Set Up Time Refer to Test Condition. 50 — — ns
Load Enable Pulse Width Refer to Test Condition. 50 — — ns
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Page 8
PLL Functional Description
The simplified block diagram below shows the building blocks of frequency synthesizer and all internal registers, which are 20-bit
LMX3161
data register, 18-bit F-latch, 12-bit N-counter, and 6-bit R-counter.
DS012815-4
The DATAstream is clocked into the data register on the rising edge of CLOCK signal, MSB first. The last two bits are the control
bits to indicate which register to be written. Upon the rising edge of the LE (Load Enable) signal, the rest of data bits is transferred
to the addressed register accordingly. The decoding scheme of the two control bits is as follows:
Control Bits Register
C2 C1
0 0 N-Counter
1 0 R-Counter
X 1 F-Latch
Note: X=Don’t Care Condition
Programmable Feedback Divider (N-Counter)
The N-counter consists of the 6-bit swallow counter (A-counter) and the 6-bit programmable counter (B-counter). When the control bits are “00”, data is transferred from the 20-bit shift register into two 6-bit latches. One latch sets the A-counter while the other
sets the B-counter. The serial data format is shown below.
MSB REGISTER’S BIT MAPPING LSB
19 1817 1615 1413121110 9 8 7 6 543210
RESERVED N-COUNTER’s Divide Ratio C2 C1
X XXXXXN12N11N10N9N8N7N6N5N4N3N2N100
Note: X=Don’t Care Condition
Swallow Counter Divide Ratio (A-Counter)
Divide Ratio, A N6 N5 N4 N3 N2 N1
0 000000
1 000001
* ******
63 111111
Note: Divide ratio must be from 0 to 63, and B must be ≥ A.
Programmable Counter Divide Ratio (B-Counter)
Divide Ratio, B N12 N11 N10 N9 N8 N7
3 000011
4 000100
* ******
63 111111
Note: Divide ratio must be from 3 to 63, and B must be ≥ A.
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Page 9
Programmable Reference Divider (R-Counter)
If the control bits are “10”, data is transferred from the 20-bit shift register into a latch, which sets the 6-bit R-counter. The serial
data format is shown below.
MSB REGISTER’S BIT MAPPING LSB
19 1817161514131211109876543210
RESERVED R-COUNTER’s Divide Ratio C2 C1
X XXXXXXXXXXXR6R5R4R3R2R110
Note: X=Don’t Care Condition
Reference Counter Divide Ratio (R-Counter)
Divide Ratio, R R6 R5 R4 R3 R2 R1
3 000011
4 000100
* ******
63 111111
Note: Divide ratio must be from 3 to 63.
Pulse Swallow Function
f
:
Output frequency of external voltage controlled oscillator (VCO)
vco
B:
Preset divide ratio of binary 6-bit programmable counter (3 to 63)
A:
Preset divide ratio of binary 6-bit swallow counter (0 ≤ A ≤ P, A ≤ B)
f
:
Output frequency of the external reference frequency oscillator
OSC
R:
Preset divide ratio of binary 6-bit programmable reference counter (3 to 63)
P:
Preset modulus of dual modulus prescaler (32 or 64)
LMX3161
Receiver Functional Description
The simplified block diagram below shows the mixer, IF amplifier, limiter,and discriminator. In addition, the DC compensation circuit, doubler, and voltage regulator for an external LNA stage are shown.
Note: The receiver can be powered down, either by hardware through the Rx PD pin, or by software through the programming of F6 bit in F-Latch. The power
down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.)
DS012815-5
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Page 10
Transmitter Functional Description
The simplified block diagram below shows the doubler and voltage regulator for an external transmit gain stage.
LMX3161
Note: The transmitter can be powered down, either by hardware through the Tx PD pin, or by software through the programming of F7 bith in F-Latch. The
power down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.)
DS012815-6
Function Register Programming Description (F-Latch)
If the control bits are “1X”, data is transferred from the 20-bit shift register into the 18-bit F-latch. Serial data format is shown
below.
MSB REGISTER’S BIT MAPPING LSB
19 1817161514131211109876543210
MODE CONTROL WORD C2 C1
F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 X 1
Note: X=Don’t Care Condition
Various modes of operation can be programmed with the function register bits F1–F18, including the phase detector polarity,
charge pump TRI-STATE
F11 and F12.
Mode
Control
Bit
F1 Prescaler modules select. 32/33 64/65
F2 Phase detector polarity. It is used to reverse the polarity of
the phase detector according to the VCO characteristics.
F3 Charge pump current gain select. LOW Charge Pump
F4 TRI-STATE charge pump output. Normal Operation Force to TRI-STATE
F5 Reserved. Setting to “0” always. — —
F6 Receive chain power down control. Software power down
can only be activated when both F11 and F12 are set to “0”.
F7 Transmit chain power down control. Software power down
can only be activated when both F11 and F12 are set to “0”.
F8 Out 0 CMOS output. OUT 0=LOW OUT 0=HIGH
F9 Out 1 CMOS output. Functions only in software power down
mode, when both F11 and F12 are set to “0”.
F10 Out 2 CMOS output. Functions only in software power down
mode, when both F11 and F12 are set to “0”.
F11
F12
Power down mode select.
Set both F11 and F12 to “0” for software power down mode.
Set both F11 and F12 to “1” for hardwire power down mode.
Other combinations are reserved for test mode.
F13 Demodulator gain select 1X Gain Mode 3X Gain Mode
F14 Demodulator DC level shift +/− level shifting polarity Set Negative Polarity Set Positive Polarity
®
and CMOS outputs. In addition, software or hardwire power down modes can be specified with bits
Model Control Description
Setting to
“0” to Select
Negative VCO
Characteristics
Setting to
“1” to Select
Positive VCO
Characteristics
HIGH Charge Pump
Current (1X I
).
cpo
Current (4X I
Power Up RX Chain Power Down RX Chain
Power Up TX Chain Power Down TX Chain
OUT 1=LOW OUT 1=HIGH
OUT 2=LOW OUT 2=HIGH
Software
Power Down
Hardware
Power Down
).
cpo
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Page 11
Function Register Programming Description (F-Latch) (Continued)
LMX3161
Mode
Control
Bit
F15 Demodulator DC level shift of 1.000V No Shift Shift the DC Level
F16 Demodulator DC level shift of 0.500V No Shift Shift the DC Level
F17 Demodulator DC level shift of 0.250V No Shift Shift the DC Level
F18 Demodulator DC level shift of 0.125V No Shift Shift the DC Level
Model Control Description
Setting to
“0” to Select
Setting to
“1” to Select
by 1.000V
by 0.500V
by 0.250V
by 0.125V
Power Down Mode/Control Table
Software Power Down Mode (F11=F12=0) Hardwire Power Down Mode (F11=F12=1)
Pin/Bit Setting to “0”
means
F6 Receiver ON Receiver OFF Rx PD Receiver OFF Receiver ON
F7 Transmitter ON Transmitter OFF Tx PD Transmitter OFF Transmitter ON
PLL PD PLL ON PLL OFF PLL PD PLL ON PLL OFF
CE LMX3161 OFF LMX3161 ON CE LMX3161 OFF LMX3161 ON
Setting to “1”
means
Pin/Bit Setting to “0”
means
Setting to “1”
means
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Page 12
Typical Application
LMX3161
DECT System Calculation for 3.6V Operation
DS012815-7
Note: Assumes 50 dB attenuation of interferer by the SAW filter and 8 dB attenuation by the LC filter. Cascaded totals in Input IP3 are calculated at the output
of the interstage filter.
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DS012815-11
Page 13
Loop Filter Design Consideration
FIGURE 1. Conventional PLL Architecture
LMX3161
DS012815-8
Loop Gain Equations
A linear control system model of the phase feedback for a
PLL in the locked state is shown in
gain is the product of the phase comparator gain (K
VCO gain (K
gain of the feedback counter modulus (N). The passive loop
/s), and the loop filter gain Z(s) divided by the
vco
filter configuration used is displayed in
complex impedance of the filter is given in
FIGURE 2. PLL Linear Model
FIGURE 3. Passive Loop Filter
Figure 2
Figure 3
DS012815-10
. The open loop
), the
φ
, while the
Equation (2)
.
DS012815-9
PASSIVE LOOP FILTER
Open loop gain=H(s) G(s)
θi/θe=K
Z(s)K
φ
=
/Ns (1)
VCO
(2)
The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as
(3)
and
T2=R2•C2
(4)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time constants T1 and T2,
and the design constants K
φ,Kvco
, and N.
(5)
Equations (3), (4)
From
we can see that the phase term will
be dependent on the single pole and zero such that the
phase margin is determined in
φ (ω)=tan
−1
(ω
T
2) − tan−1(ω
•
Equation (6)
.
T
1) + 180˚ (6)
•
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Page 14
Physical Dimensions inches (millimeters) unless otherwise noted
LMX3161 Single Chip Radio Transceiver
48-Lead (7mm x 7mm) Molded Plastic Quad Flat Package, JEDEC
For Tape and Reel (2500 Units per Reel)
Order Number LMX3161VBH or LMX3161VBHX
NS Package Number VBH48A
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can be reasonably expected to cause the failure of
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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