LMX2330L/LMX2331L/LMX2332L
October 2001
LMX2330L/LMX2331L/LMX2332L PLLatinum Low Power Dual Frequency Synthesizer for RF
Personal Communications
PLLatinum
™
Low Power Dual Frequency Synthesizer for
RF Personal Communications
LMX2330L 2.5 GHz/510 MHz
LMX2331L 2.0 GHz/510 MHz
LMX2332L 1.2 GHz/510 MHz
General Description
The LMX233XL family of monolithic, integrated dual frequency synthesizers, including prescalers, is to be used as a
local oscillator for RF and first IF of a dual conversion
transceiver. It is fabricated using National’s 0.5µ ABiC V
silicon BiCMOS process.
The LMX233XL contains dual modulus prescalers. A 64/65
or a 128/129 prescaler (32/33 or 64/65 in the 2.5 GHz
LMX2330L) can be selected fortheRFsynthesizeranda8/9
or a 16/17 prescaler can be selected for the IF synthesizer.
LMX233XL, which employs a digitalphase locked looptechnique, combined with a high quality reference oscillator,
provides the tuning voltages for voltage controlled oscillators
to generate very stable, low noise signals for RFand IF local
oscillators. Serial data is transferred into the LMX233XL via
a three wire interface (Data, Enable, Clock). Supply voltage
can range from 2.7V to5.5V.The LMX233XL family features
very low current consumption;
LMX2330L—5.0 mA at 3V, LMX2331L —4.0 mA at 3V,
LMX2332L—3.0 mA at 3V.
The LMX233XL are available in a TSSOP 20-pin, CSP
24-pin surface mount plastic package, and thin CSP 20-pin
surface mount plastic package.
Features
n Ultra low current consumption
n 2.7V to 5.5V operation
n Selectable synchronous or asynchronous powerdown
mode:
I
= 1 µA typical at 3V
CC
n Dual modulus prescaler:
LMX2330L (RF) 32/33 or 64/65
LMX2331L/32L (RF) 64/65 or 128/129
LMX2330L/31L/32L (IF) 8/9 or 16/17
n Selectable charge pump TRI-STATE
n Selectable charge pump current levels
n Selectable Fastlock
n Upgrade and compatible to LMX233XA family
™
mode
®
mode
Applications
n Portable Wireless Communications
(PCS/PCN, cordless)
n Cordless and cellular telephone systems
n Wireless Local Area Networks (WLANs)
n Cable TV tuners (CATV)
n Other wireless communication systems
Functional Block Diagram
01280601
© 2001 National Semiconductor Corporation DS012806 www.national.com
Connection Diagrams
Chip Scale Package (SLB)
(Top View)
LMX2330L/LMX2331L/LMX2332L
Order Number LMX2330LSBX, LMX2331LSLBX or
LMX2332LSLBX
NS Package Number SLB24A
20-Pin Thin Chipscale Package (SLD)
(Top View)
Thin Shrink Small Outline Package (TM)
(Top View)
01280602
Order Number LMX2330LTM, LMX2331LTM or
LMX2332LTM
Order Number LMX2330LTMX, LMX2331LTMX, or
LMX2332LTMX
NS Package Number MTC20
01280639
Order Number LMX2330LSLDX, LMX2331LSLDX, or
01280640
LMX2332LSLDX
NS Package Number SLD20A
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Pin Descriptions
LMX2330L/LMX2331L/LMX2332L
Pin No.
LMX233XLSLD
20-pin Thin
CSP Package
20 24 1 V
Pin No.
LMX233XLSLB
24-pin CSP
Package
Pin No.
LMX233XLTM
20-pin TSSOP
Package
Pin
Name
CC
I/O Description
1 — Power supply voltage input for RF analog and RF digital circuits.
Input may range from 2.7V to 5.5V. V
1 must equal VCC2.
CC
Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.
122V
233D
1 — Power Supply for RF charge pump. Must be ≥ VCC.
P
RF O Internal charge pump output. For connection to a loop filter for
o
driving the input of an external VCO.
3 4 4 GND — Ground for RF digital circuitry.
455f
566f
RF I RF prescaler input. Small signal input from the VCO.
IN
RF I RF prescaler complementary input. A bypass capacitor should
IN
be placed as close as possible to this pin and be connected
directly to the ground plane. Capacitor is optional with some loss
of sensitivity.
6 7 7 GND — Ground for RF analog circuitry.
788OSC
I Oscillator input. The input has a VCC/2 input threshold and can
in
be driven from an external CMOS or TTL logic gate.
8 10 9 GND — Ground for IF digital, MICROWIRE
™
,FoLD, and oscillator
circuits.
91110F
LD O Multiplexed output of the RF/IF programmable or reference
o
dividers, RF/IF lock detect signals and Fastlock mode. CMOS
(see Programmable Modes).
output
10 12 11 Clock I High impedance CMOS Clock input. Data for the various
counters is clocked in on the rising edge, into the 22-bit shift
register.
11 14 12 Data I Binary serial data input. Data entered MSB first. The last two bits
are the control bits. High impedance CMOS input.
12 15 13 LE I Load enable high impedance CMOS input. When LE goes HIGH,
data stored in the shift registers is loaded into one of the 4
appropriate latches (control bit dependent).
13 16 14 GND — Ground for IF analog circuitry.
14 17 15 f
IF I IF prescaler complementary input. A bypass capacitor should be
IN
placed as close as possible to this pin and be connected directly
to the ground plane. Capacitor is optional with some loss of
sensitivity.
15 18 16 f
16 19 17 GND — Ground for IF digital, MICROWIRE, F
17 20 18 D
RF I IF prescaler input. Small signal input from the VCO.
IN
LD, and oscillator circuits.
o
IF O IF charge pump output. For connection to a loop filter for driving
o
the input of an external VCO.
18 22 19 V
19 23 20 V
2 — Power Supply for IF charge pump. Must be ≥ VCC.
P
2 — Power supply voltage input for IF analog, IF digital,
CC
MICROWIRE, F
2.7V to 5.5V. V
LD, and oscillator circuits. Input may range from
o
2 must equal VCC1. Bypass capacitors should
CC
be placed as close as possible to this pin and be connected
directly to the ground plane.
X 1, 9, 13, 21 X NC — No connect.
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Block Diagram
LMX2330L/LMX2331L/LMX2332L
Note: The RF prescaler for the LMX2331L/32L is either 64/65 or 128/129, while the prescaler for the LMX2330L is 32/33 or 64/65.
Note: V
R-counter along with the OSC
Note: V
1 supplies power to the RF prescaler, N-counter, R-counter and phase detector. VCC2 supplies power to the IF prescaler, N-counter, phase detector,
CC
1 and VP2 can be run separately as long as VP≥ VCC.
P
buffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same voltage level.
in
01280603
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LMX2330L/LMX2331L/LMX2332L
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
V
CC
V
P
Voltage on Any Pin
with GND = 0V (V
Storage Temperature Range (T
) −0.3V to VCC+0.3V
I
) −65˚C to +150˚C
S
Lead Temperature (solder 4 sec.)
(T
) +260˚C
L
−0.3V to +6.5V
−0.3V to +6.5V
Recommended Operating Conditions
Power Supply Voltage
V
CC
V
P
Operating Temperature (T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD
<
2 keV and is ESD sensitive. Handling and assembly of this device
rating
should only be done at ESD protected work stations.
) −40˚C to +85˚C
A
2.7V to 5.5V
VCCto +5.5V
Electrical Characteristics
VCC= 3.0V, VP= 3.0V; −40˚C<T
Symbol Parameter Conditions
I
CC
Power LMX2330L RF + IF VCC= 2.7V to 5.5V 5.0 6.6
Supply LMX2330L RF Only 4.0 5.2
Current LMX2331L RF + IF 4.0 5.4
I
CC-PWDN
f
IN
Powerdown Current (Note 3) 1 10 µA
RF Operating LMX2330L 0.5 2.5
Frequency LMX2331L 0.2 2.0 GHz
f
IF Operating LMX233xL 45 510 MHz
IN
Frequency
f
f
OSC
φ
Oscillator Frequency 5 40 MHz
Maximum Phase Detector 10 MHz
Frequency
Pf
RF RF Input Sensitivity VCC= 3.0V −15 0 dBm
IN
Pf
IF IF Input Sensitivity VCC= 2.7V to 5.5V −10 0 dBm
IN
V
OSC
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
V
OH
V
OL
t
CS
t
CH
Oscillator Sensitivity OSC
High-Level Input Voltage (Note 4) 0.8 V
Low-Level Input Voltage (Note 4) 0.2 V
High-Level Input Current VIH=VCC= 5.5V (Note
Low-Level Input Current VIL= 0V, VCC= 5.5V
Oscillator Input Current VIH=VCC= 5.5V 100 µA
Oscillator Input Current VIL= 0V, VCC= 5.5V −100 µA
High-Level Output Voltage (for
LD, pin number 10)
F
o
Low-Level Output Voltage (for
LD, pin number 10)
F
o
Data to Clock Set Up Time See Data Input Timing 50 ns
Data to Clock Hold Time See Data Input Timing 10 ns
<
85˚C, except as specified
A
Value
Min Typ Max
LMX2331L RF Only 3.0 4.0 mA
LMX2332L IF + RF 3.0 4.1
LMX2332L RF Only 2.0 2.7
LMX233xL IF Only 1.0 1.4
LMX2332L 0.1 1.2
V
= 5.0V −10 0 dBm
CC
in
0.5 V
CC
−1.0 1.0 µA
4)
−1.0 1.0 µA
(Note 4)
I
= −500 µA VCC− 0.4 V
OH
I
= 500 µA 0.4 V
OL
CC
Units
PP
V
V
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Electrical Characteristics (Continued)
VCC= 3.0V, VP= 3.0V; −40˚C<T
Symbol Parameter Conditions
t
CWH
t
CWL
t
ES
t
EW
Note 3: Clock, Data and LE = GND or Vcc.
Note 4: Clock, Data and LE does not include f
Clock Pulse Width High See Data Input Timing 50 ns
Clock Pulse Width Low See Data Input Timing 50 ns
Clock to Load Enable Set Up Time See Data Input Timing 50 ns
Load Enable Pulse Width See Data Input Timing 50 ns
LMX2330L/LMX2331L/LMX2332L
<
85˚C, except as specified
A
RF, fINIF and OSCIN.
IN
Value
Min Typ Max
Charge Pump Characteristics
VCC= 3.0V, VP= 3.0V; −40˚C<TA≤ 85˚C, except as specified
Symbol Parameter Conditions
I
-SOURCE Charge Pump Output VDo=VP/2, I
Do
I
-SINK Current VDo=VP/2, I
Do
I
-SOURCE VDo=VP/2, I
Do
I
-SINK VDo=VP/2, I
Do
I
-TRI Charge Pump 0.5V ≤ VDo≤ VP− 0.5V −2.5 2.5
Do
<
= 25˚C
A
T
TRI-STATE Current −40˚C
I
-SINK vs CP Sink vs VDo=VP/2 3 10 %
Do
I
SOURCE Source Mismatch (Note 7) TA= 25˚C
Do-
I
vs V
Do
Do
CP Current vs Voltage 0.5 ≤ VDo≤ VP− 0.5V 10 15 %
(Note 6) T
I
vs T
Do
A
CP Current vs VDo=VP/2 10 %
Temperature (Note 8) −40˚C ≤ T
Note 5: See PROGRAMMABLE MODES for I
description.
CPo
= HIGH (Note 5) −4.0 mA
CPo
= HIGH (Note 5) 4.0 mA
CPo
= LOW (Note 5) −1 mA
CPo
= LOW (Note 5) 1 mA
CPo
<
85˚C
A
≤ 85˚C
A
Min Typ Max
Value
Units
Units
nA
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Charge Pump Current Specification Definitions
LMX2330L/LMX2331L/LMX2332L
I1 = CP sink current at VDo=VP−∆V
I2 = CP sink current at V
I3 = CP sink current at V
I4 = CP source current at V
I5 = CP source current at V
I6 = CP source current at V
Do=VP
= ∆V
Do
Do=VP
Do=VP
Do
/2
−∆V
/2
= ∆V
∆V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V
Note 6: I
Note 7: I
Note 8: I
vs VDo= Charge Pump Output Current magnitude variation vs Voltage =
Do
1
*
[
⁄
2
{|I1| − |I3|}]/[1⁄
vs I
Do-sink
[|I2| − |I5|]/[
vs TA= Charge Pump Output Current magnitude variation vs Temperature =
Do
@
[|I2
temp| − |I2@25˚C|]/|I2@25˚C|*100% and [|I5@temp| − |I5@25˚C|]/|I5@25˚C|*100%
*
2
{|I1| + |I3|}]*100% and [1⁄
= Charge Pump Output Current Sink vs Source Mismatch =
Do-source
1
*
⁄
2
{|I2| + |I5|}]*100%
*
2
{|I4| − |I6|}]/[1⁄
*
2
{|I4| + |I6|}]*100%
01280637
and ground. Typical values are between 0.5V and 1.0V.
CC
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RF Sensitivity Test Block Diagram
LMX2330L/LMX2331L/LMX2332L
Note 1: N = 10,000 R = 50 P = 64
Note 2: Sensitivity limit is reached when the error of the divided RF output, F
Typical Performance Characteristics
ICCvs V
LMX2330L
ICCvs V
LMX2332L
CC
01280619 01280620
CC
LD, is ≥ 1 Hz.
o
vs V
I
CC
LMX2331L
TRI-STATE
I
Do
vs D
o
01280638
CC
Voltage
01280621
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01280622
Typical Performance Characteristics (Continued)
LMX2330L/LMX2331L/LMX2332L
Charge Pump Current vs D
I
= HIGH
CP
Voltage
o
Charge Pump Current Variation
(See (Note 6) under Charge Pump Current
Specification Definitions)
01280623
Charge Pump Current vs D
I
= LOW
CP
Voltage
o
Sink vs Source Mismatch
(See (Note 7) under Charge Pump Current
Specification Definitions)
01280624
01280625
01280626
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Typical Performance Characteristics (Continued)
RF Input Impedance
V
= 2.7V to 5.5V, fIN= 50 MHz to 3 GHz
CC
LMX2330L/LMX2331L/LMX2332L
IF Input Impedance
VCC= 2.7V to 5.5V, fIN= 50 MHz to 1000 MHz
01280627
01280628
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Typical Performance Characteristics (Continued)
LMX2330L/LMX2331L/LMX2332L
LMX233xSLD RF Input Impedance
V
= 2.7V to 5.5V, fIN= 500 MHz to 3 GHz, fINRF CAP =
CC
100 pF
Marker 1 = 500 MHz, Real = 202.98, Imaginary = −200.09
Marker 2 = 1.8 GHz, Real = 32.36, Imaginary = −91.42
Marker 3 = 2.5GHz, Real = 25.51, Imaginary = −46.41
Marker 4 = 3.0 GHz, Real = 30.46, Imaginary = −9.50
01280641
LMX233xSLD IF Input Impedance
V
= 2.7V to 5.5V, fINIF = 100 MHz to 400 MHz, fINIF
CC
CAP = 100 pF
Marker 1 = 100 MHz, Real = 374.33, Imaginary = −301.45
Marker 2 = 200 MHz, Real = 257.14, Imaginary = −245.79
Marker 3 = 300 MHz, Real = 194.08, Imagniary = −224.24
Marker 4 = 400 MHz, Real = 89.03, Imaginary = −131.21
01280642
LMX2330L RF Sensitivity vs Frequency LMX2331L RF Sensitivity vs Frequency
01280629 01280630
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Typical Performance Characteristics (Continued)
LMX2332L RF Sensitivity vs Frequency IF Input Sensitivity vs Frequency
LMX2330L/LMX2331L/LMX2332L
01280631 01280632
Oscillator Input Sensitivity vs Frequency
01280633
Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit N Counters
(intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first.
The data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE. The last two bits are the
Control Bits. The DATA is transferred into the counters as follows:
Control Bits DATA Location
C1 C2
0 0 IF R Counter
0 1 RF R Counter
1 0 IF N Counter
1 1 RF N Counter
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Functional Description (Continued)
01280606
PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
LMX2330L/LMX2331L/LMX2332L
01280607
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide RRRRRRRRRRRRRRR
Ratio 15 14 13 12 11 10 987654321
3 000000000000011
4 000000000000100
• •••••••••••••••
32767 111111111111111
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 forIF counter and 11 for RF counter) data is transferred fromthe 22-bit shift register intoa 4-bit or 7-bit latch
(which sets the Swallow (A) Counter) and an11-bitlatch (which sets the 11-bit programmable (B) Counter),MSB first. Serial data
format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter does not have don’t care
bits.
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Functional Description (Continued)
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
LMX2330L/LMX2331L/LMX2332L
Divide N7N6N5N4N3N2N
Ratio
A
0 0000000
1 0000001
• •••••••
127 1111111
Notes: Divide ratio: 0 to 127
B ≥ A
RF
1
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
Divide N18N17N16N15N14N13N12N11N10N9N
Ratio
B
3 00000000011
4 00000000100
• •••••••••••
2047 11111111111
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
B ≥ A
01280608
IF
Divide N7N6N5N4N3N2N
Ratio
A
0 XXX0000
1 XXX0001
• •••••••
15 XXX1111
X = DON’T CARE condition
8
1
PULSE SWALLOW FUNCTION
f
=[(PxB)+A]xf
VCO
f
: Output frequency of external voltage controlled oscillator (VCO)
VCO
OSC
/R
B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter
(0 ≤A ≤ 127 {RF}, 0 ≤A ≤ 15 {IF}, A ≤ B)
f
: Output frequency of the external reference frequency oscillator
OSC
R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual moduIus prescaler (for IF; P = 8 or 16;
for RF; LMX2330L: P = 32 or 64 LMX2331L/32L: P = 64 or 128)
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Functional Description (Continued)
PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump
TRI-STATE and the output of the F
programmable modes are shownin
Table 3
.
C1 C2 R16 R17 R18 R19 R20
0 0 IF Phase IF I
0 1 RF Phase RF I
Phase Detector Polarity DoTRI-STATE I
(Note 11) (Note 9) (Note 10) Prescaler Prescaler Prescaler (Note 9)
0 Negative Normal Operation LOW 8/9 32/33 64/65 Pwrd Up
1 Positive TRI-STATE HIGH 16/17 64/65 128/129 Pwrd Dn
Note 9: Refer to POWERDOWN OPERATION in Functional Description.
Note 10: The I
Note 11: PHASE DETECTOR POLARITY
Depending upon VCO characteristics, R16 bit should be set accordingly: (see figure right)
When VCO characteristics are positive like (1), R16 should be set HIGH;
When VCO characteristics are negative like (2), R16 should be set LOW.
LOW current state = 1/4 x I
CPo
LD pin. The prescaler and powerdown modes are selected with bits N19 and N20. The
o
Table 1
. Truth table for the programmablemodes and FoLD output are shownin
TABLE 1. Programmable Modes
CPo
IF D
o
IF LD IF F
o
Detector Polarity TRI-STATE
CPo
RF D
o
RF LD RF F
o
Detector Polarity TRI-STATE
C1 C2 N19 N20
1 0 IF Prescaler Pwdn IF
1 1 RF Prescaler Pwdn RF
TABLE 2. Mode Select Truth Table
IF 2330L RF 2331L/32L RF Pwdn
HIGH current.
CPo
CPo
VCO Characteristics
Table 2
and
LMX2330L/LMX2331L/LMX2332L
01280609
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Functional Description (Continued)
TABLE 3. The F
RF R[19] IF R[19] RF R[20] IF R[20]
(RF LD) (IF LD) (RF F
LD (Pin 10) Output Truth Table
o
) (IF Fo)
o
Output State
F
o
0 0 0 0 Disabled (Note 12)
0 1 0 0 IF Lock Detect (Note 13)
1 0 0 0 RF Lock Detect (Note 13)
1 1 0 0 RF/IF Lock Detect (Note 13)
X 0 0 1 IF Reference Divider Output
X 0 1 0 RF Reference Divider Output
LMX2330L/LMX2331L/LMX2332L
X 1 0 1 IF Programmable Divider Output
X 1 1 0 RF Programmable Divider Output
0 0 1 1 Fastlock (Note 14)
0 1 1 1 IF Counter Reset (Note 15)
1 0 1 1 RF Counter Reset (Note 15)
1 1 1 1 IF and RF Counter Reset (Note 15)
X = don’t care condition
Note 12: When the F
Note 13: Lock detect output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.
Note 14: The Fastlock mode utilizes the F
occurs whenever the RF loop’s lcpo magnitude bit
Note 15: The IF Counter Reset mode resets IF PLL’s R and N counters and brings IF charge pump output to a TRI-STATEcondition. The RF Counter Reset mode
resets RF PLL’s R and N counters and brings RF charge pump output to a TRI-STATEcondition. The IF and RF Counter Reset mode resets all counters and brings
both charge pump outputs to a TRI-STATE condition. Upon removal of the Reset bits then N counter resumes counting in “close” alignment with the R counter. (The
maximum error is one prescaler cycle.)
LD output is disabled, it is actively pulled to a low logic state.
o
LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
o
#
17 is selected HIGH (while the#19 and#20 mode bits are set for Fastlock).
POWERDOWN OPERATION
Synchronous and asynchronous powerdown modes are both available by MICROWIRE selection. Synchronously powerdown
occurs if the respective loop’s R18 bit (Do TRI-STATE) is LOW when its N20 bit (Pwdn) becomes HI. Asynchronous powerdown
occurs if the loop’s R18 bit is HI when its N20 bit becomes HI.
In the synchronous powerdown mode, the powerdown function is gated by the charge pump to prevent unwanted frequency
jumps. Once the powerdown program bit N20 is loaded, the part will go into powerdown mode when the charge pump reaches
a TRI-STATE condition.
In the asynchronous powerdown mode, the device powers down immediately after the LE pin latches in a HI condition on the
powerdown bit N20.
Activation of either the IF or RF PLL powerdown conditions in either synchronous or asynchronous modes forces the respective
loop’s R and N dividers to their load state condition and debiasing of its respective f
input to a high impedance state. The
IN
oscillator circuitry function does not become disabled until both IF and RF powerdown bits are activated. The MICROWIRE
control register remains active and capable of loading and latching data during all of the powerdown modes.
The device returns to an actively powered up condition in either synchronous or asynchronous modes immediately upon LE
latching LOW data into bit N20.
Powerdown Mode Select Table
R18 N20 Powerdown Status
0 0 PLL Active
1 0 PLL Active
(Charge Pump Output TRI-STATE)
0 1 Synchronous Powerdown Initiated
1 1 Asynchronous Powerdown Initiated
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Functional Description (Continued)
SERIAL DATA INPUT TIMING
LMX2330L/LMX2331L/LMX2332L
Note 1: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Note 2: t
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V
amplitudes of 2.2V
= Data to Clock Set-Up Time
cs
t
= Data to Clock Hold Time
CH
t
= Clock Pulse Width High
CWH
t
= Clock Pulse Width Low
CWL
t
= Clock to Load Enable Set-Up Time
ES
t
= Load Enable Pulse Width
EW
@
VCC= 2.7V and 2.6V@VCC= 5.5V.
/2. The test waveform has an edge rate of 0.6 V/ns with
CC
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
Notes: Phase difference detection range: −2π to +2π
The minimum width pump up and pump down current pulses occur at the D
R16 = HIGH
pin when the loop is locked.
o
01280610
01280611
www.national.com17
Typical Application Example
LMX2330L/LMX2331L/LMX2332L
Operational Notes:
*
VCO is assumed AC coupled.
**
RINincreases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to 200Ω depending on the VCO
power level. f
***
Adding RC filters to the VCClines is recommended to reduce loop-to-loop noise coupling.
Application Hints:
RF impedance ranges from 40Ω to 100Ω.fINIF impedances are higher.
IN
01280613
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful
board layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.
01280612
www.national.com 18
Application Information
A block diagram of the basic phase locked loop is shown in
Figure 1
LOOP GAIN EQUATIONS
A linear control system model of the phase feedback for a
PLL in the locked state is shown in
gain is the product of the phase comparator gain (Kφ), the
VCO gain (K
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in
the complex impedance of the filter is given in
.
01280614
FIGURE 1. Basic Charge Pump Phase Locked Loop
Figure 2
/s), and the loop filter gain Z(s) divided by
VCO
. The open loop
Figure 3
, while
Equation (1)
LMX2330L/LMX2331L/LMX2332L
and
T2=R2
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time constants T1 and T2,
and the design constants K
.
C2 (3)
•
, and N.
φ,KVCO
01280615
FIGURE 2. PLL Linear Model
01280616
FIGURE 3. Passive Loop Filter
(1)
The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as
(2)
(4)
From
Equations (2), (3)
we can see that the phase term will
be dependent on the single pole and zero such that the
phase margin is determined in
φ(ω) = tan
−1
(ω•T2) − tan−1(ω•T1) + 180˚ (5)
Equation (5)
.
A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in
φ
shows the amount of phase margin that exists at thepoint
p
Figure 4
with a solid trace. The parameter
the gain drops below zero (the cutoff frequency wp of the
loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop bandwidth, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison
frequency also diminishes, the spurs would have increased
by approximately 6 dB. In the proposed Fastlock scheme,
the higher spur levels and wider loop filter conditions would
exist only during theinitial lock-on phase—just longenough
to reap the benefits of lockingfaster. The objective would be
to open up the loop bandwidth but not introduce any additional complications or compromises related to our original
design criteria. We would ideally liketo momentarily shift the
curve of
Figure 4
over to a different cutoff frequency, illustrated by the dotted line, without affecting the relative open
loop gain and phase relationships. To maintain the same
gain/phase relationship at twice the original cutoff frequency,
other terms in the gain and phase
(5)
will have to compensate by the corresponding “1/w” or
2
“1/w
” factor. Examination of equations
and
Equation (5)
indicates the damping resistor variable R2
Equation (4)
Equations (2), (3)
and
Equation
could be chosen to compensate the “w”’ terms for the phase
www.national.com19
Application Information (Continued)
margin. This implies that another resistor of equal value to
R2 will need to be switched in parallel with R2 during the
initial lock period. We must alsoinsure that the magnitudeof
the open loop gain, H(s)G(s) is equal to zero at wp’ = 2wp.
K
,Kφ, N, or the net product of these terms can be
vco
LMX2330L/LMX2331L/LMX2332L
FIGURE 4. Open Loop Response Bode Plot
FASTLOCK CIRCUIT IMPLEMENTATION
A diagram of the Fastlock scheme as implemented in National Semiconductors LMX233XLPLL is shown in
When a new frequency is loaded, and the RF Icp
high the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2resistor
element to ground. The user calculates the loop filter component values for the normal steady state considerations.
The device configuration ensures that as long as a second
Figure 5
bit is set
o
2
changed by a factor of 4, to counteract the w
in the denominator of
Equation (2)
and
Equation (3)
term present
. The Kφ
term was chosen to complete the transformation because it
can readily be switched between 1X and 4X values. This is
accomplished by increasing the charge pump output current
from 1 mA in the standard mode to 4 mA in Fastlock.
01280617
identical damping resistor is wired in appropriately, the loop
will lock faster without any additional stability considerations
.
to account for. Once locked on the correct frequency, the
user can return the PLL to standard low noise operation by
sending a MICROWIRE instruction with the RF Icp
bit set
o
low. This transition does not affect the charge on the loop
filter capacitors and is enacted synchronous with the charge
pump output. This creates a nearly seamless change between Fastlock and standard mode.
FIGURE 5. Fastlock PLL Architecture
www.national.com 20
01280618
Physical Dimensions inches (millimeters)
unless otherwise noted
LMX2330L/LMX2331L/LMX2332L
20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM)
Order Number LMX2330LTM, LMX2331LTM or LMX2332LTM
Order Number LMX2330LTMX, LMX2331LTMX or LMX2332LTMX
*
For Tape and Reel (2500 units per reel)
NS Package Number MTC20
www.national.com21
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LMX2330L/LMX2331L/LMX2332L
24-Pin Chip Scale Package
For Tape and Reel (2500 Units per Reel)
Order Number LMX2330LSLBX, LMX2331LSLBX or LMX2332LSLBX
NS Package Number SLB24A
www.national.com 22
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LMX2330L/LMX2331L/LMX2332L PLLatinum Low Power Dual Frequency Synthesizer for RF
Personal Communications
20-Pin Thin Chip Scale Package (SLD)
Order Number LMX2330LSLDX, LMX2331LSLDX or LMX2332LSLDX
NS Package Number SLD20A
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