Datasheet LMX2331ATM, LMX2330ATM, LMX2332ATM Datasheet (NSC)

LMX2330A/LMX2331A/LMX2332A
PLLatinum

™

Dual Frequency Synthesizer for RF

Personal Communications

LMX2330A 2.5 GHz/510 MHz
LMX2331A 2.0 GHz/510 MHz
LMX2332A 1.2 GHz/510 MHz

General Description

The LMX233xA family of monolithic, integrated dual fre­quency synthesizers, including prescalers, is to be used as a
local oscillator for RF and first IF of a dual conversion trans­ceiver. It is fabricated using National’s ABiC IV silicon
BiCMOS process.

The LMX233xA contains dual modulus prescalers. A 64/65
or a 128/129 prescaler (32/33 or 64/65 in the 2.5 GHz
LMX2330A) can be selected for the RF synthesizer and a
8/9 or a 16/17 prescaler can be selected for the IF synthe­sizer.LMX233XA,whichemploysadigitalphaselockedloop
technique, combined with a high quality reference oscillator
and loop filters, provides the tuning voltages for voltage con­trolled oscillators to generate very stable low noise RF and
IF local oscillator signals. Serial data is transferred into the
LMX233xA via a three wire interface (Data, Enable, Clock).
Supply voltage can range from 2.7V to 5.5V.The LMX233xA
family features very low current consumption;
LMX2330A—13 mA at 3V, LMX2331A—12 mA at 3V,
LMX2332A— 8 mA at 3V.

The LMX233xA are available in a TSSOP 20-pin surface
mount plastic package.

Features

n 2.7V to 5.5V operation
n Low current consumption
n Selectable powerdown mode: I
n Dual modulus prescaler:

n Selectable charge pump TRI-STATE
n Selectable FastLock
n Small outline, plastic, surface mount TSSOP 0.173"

wide package

Applications

n Portable Wireless Communications (PCS/PCN, cordless)
n Cordless and cellular telephone systems
n Wireless Local Area Networks (WLANs)
n Cable TV tuners (CATV)
n Other wireless communication systems

=

1 µA typical at 3V

CC

LMX2330A (RF) 32/33 or 64/65
LMX2331A/32A (RF) 64/65 or 128/129
LMX2330A/31A/32A (IF) 8/9 or 16/17

™

mode

®

mode

May 1999

LMX2330A/LMX2331A/LMX2332A PLLatinum Dual Frequency Synthesizer for RF Personal

Communications

Functional Block Diagram

DS012331-1

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

™

Fastlock

, MICROWIRE™and PLLatinum™are trademarks of National Semiconductor Corporation.

© 1999 National Semiconductor Corporation DS012331 www.national.com

Connection Diagram

Order Number LMX2330ATM, LMX2331ATM or LMX2332ATM

Pin Description

Thin Shrink Small Outline Package (TM)

DS012331-2

NS Package Number MTC20

Pin
No.

1V

2V
3D

Pin

Name

I/O Description

1 — Power supply voltage input for RF analog and RF digital circuits. Input may range from 2.7V to

CC

5.5V. V
pin and be connected directly to the ground plane.

1 — Power Supply for RF charge pump. Must be ≥ VCC.

P

RF O Internal charge pump output. For connection to a loop filter for driving the input of an external

o

VCO.

1 must equal VCC2. Bypass capacitors should be placed as close as possible to this

CC

4 GND — Ground for RF digital circuitry.
5f
6f

RF I RF prescaler input. Small signal input from the VCO.

IN

RF I RF prescaler complementary input. A bypass capacitor should be placed as close as possible to

IN

this pin and be connected directly to the ground plane. Capacitor is optional with some loss of

sensitivity.
7 GND — Ground for RF analog circuitry.
8 OSC

9 GND — Ground for IF digital, MICROWIRE

10 F

LD O Multiplexed output of the RF/IF programmable or reference dividers, RF/IF lock detect signals

o

I Oscillator input. The input has a VCC/2 input threshold and can be driven from an external CMOS

in

or TTL logic gate.

and Fastlock mode. CMOS output

™

,FoLD, and oscillator circuits.

(see Programmable Modes)

.

11 Clock I High impedance CMOS Clock input. Data for the various counters is clocked in on the rising

edge, into the 22-bit shift register.

12 Data I Binary serial data input. Data entered MSB first. The last two bits are the control bits. High

impedance CMOS input.

13 LE I Load enable high impedance CMOS input. When LE goes HIGH, data stored in the shift registers

is loaded into one of the 4 appropriate latches (control bit dependent(.

14 GND — Ground for IF analog circuitry.
15 f

IF I IF prescaler complementry input. A bypass capacitor should be placed as close as possible to

IN

this pin and be connected directly to the ground plane. Capacitor is optional with some loss of

sensitivity.

16 f
17 GND — Ground for IF digital, MICROWIRE, F
18 D
19 V

IF I IF prescaler input. Small signal input from the VCO.

IN

IF O IF charge pump output. For connection to a loop filter for driving the input of an external VCO.

o

2 — Power Supply for IF charge pump. Must be ≥ VCC.

P

LD, and oscillator circuits.

o

www.national.com 2

(Continued)

Pin Description (Continued)

Pin
No.

20 V

Pin

Name

I/O Description

2 — Power supply voltage input for IF analog, IF digital, MICROWIRE, FoLD, and oscillator circuits.

CC

Input may range from 2.7V to 5.5V. V
as close as possible to this pin and be connected directly to the ground plane.

Block Diagram

2 must equal VCC1. Bypass capacitors should be placed

CC

Notes:

The RF prescaler for the LMX2331A/32A is either 64/65 or 128/129, while the prescaler for the LMX2330A is 32/33 or 64/65.

1 supplies power to the RF prescaler, N-counter, R-counter and phase detector. VCC2 supplies power to the IF prescaler, N-counter, phase detector,

V

CC

R-counter along with the OSCinbuffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same voltage
level.

1 and VP2 can be run separately as long as VP≥ VCC.

V

P

DS012331-27

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Power Supply Voltage

V

CC

V

P

Voltage on Any Pin

with GND=0V (V

) −0.3V to VCC+0.3V

I

Storage Temperature Range (T

) −65˚C to +150˚C

S

−0.3V to +6.5V

−0.3V to +6.5V

Lead Temperature (solder 4 sec.) (T

) +260˚C

L

Recommended Operating
Conditions

Power Supply Voltage

V

CC

V

P

Operating Temperature (T

) −40˚C to +85˚C

A

2.7V to 5.5V

VCCto +5.5V

Electrical Characteristics

=

V

CC

Symbol Parameter Conditions

I

CC

I

CC-PWDN

f

RF Operating

IN

f

IF Operating Frequency LMX233XA 45 510 MHz

IN

f

OSC

fφ Phase Detector Frequency 10 MHz
Pf

RF RF Input Sensitivity VCC= 3.0V −15 +4 dBm

IN

Pf

IF IF Input Sensitivity VCC= 2.7V to 5.5V −10 +4 dBm

IN

V

OSC

V

IH

V

IL

I

IH

I

IL

I

IH

I

IL

V

OH

V

OL

t

CS

t

CH

t

CWH

t

CWL

t

ES

t

EW

*

Clock, Data and LE. Does not include fINRF, fINIF and OSCIN.

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Recommended OperatingConditions indicateconditions for which
the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Char­acteristics. The guaranteed specifications apply only for the test conditions listed.

Note 2: This device is a high performance RF integrated circuit with an ESD rating
be done at ESD protected workstations.

3.0V, V

Power
Supply
Current

=

3.0V; −40˚C

P

<

<

T

85˚C, except as specified

A

LMX2330A RF + IF V
LMX2330A RF Only 10 13
LMX2331A RF + IF 12 15.5
LMX2331A RF Only 9 12

Value

Min Typ Max

= 2.7V to 5.5V 13 16.5

CC

Units

mA
LMX2332A IF + RF 8 10.5
LMX2332A RF Only 5 7
LMX233XA IF Only 3 3.5

Powerdown Current 125 µA

LMX2330A 0.5 2.5

Frequency

GHzLMX2331A 0.2 2.0

LMX2332A 0.1 1.2

Oscillator Frequency 5 40 MHz

V

= 5.0V −10 +4 dBm

CC

Oscillator Sensitivity OSC

in

High-Level Input Voltage * 0.8 V
Low-Level Input Voltage * 0.2 V

0.5 V

CC

CC

PP

V

V
High-Level Input Current VIH=VCC= 5.5V* −1.0 1.0 µA
Low-Level Input Current VIL= 0V, VCC= 5.5V* −1.0 1.0 µA
Oscillator Input Current VIH=VCC= 5.5V 100 µA
Oscillator Input Current VIL= 0V, VCC= 5.5V −100 µA
High-Level Output Voltage IOH= −500 µA VCC− 0.4 V
Low-Level Output Voltage IOL= 500 µA 0.4 V
Data to Clock Set Up Time See Data Input Timing 50 ns
Data to Clock Hold Time See Data Input Timing 10 ns
Clock Pulse Width High See Data Input Timing 50 ns
Clock Pulse Width Low See Data Input Timing 50 ns
Clock to Load Enable Set Up Time See Data Input Timing 50 ns
Load Enable Pulse Width See Data Input Timing 50 ns

<

2 keV and is ESD sensitive. Handling and assembly of this device should only

www.national.com 4

Charge Pump Characteristics

=

V

CC

Symbol Parameter Conditions

I

Do-SOURCE

I

Do-SINK

I

Do-SOURCE

I

Do-SINK

I

Do-TRI

I

Do-SINK

I

Do-SOURCE

I

vs V

D

D

o

I

vs T

D

A

o

**

See PROGRAMMABLE MODES for I

Note 3: See charge pump current specification definitions below.
Note 4: See charge pump current specification definitions below.
Note 5: See charge pump current specification definitions below.

3.0V, V

vs

o

=

3.0V; −40˚C

P

<

<

T

85˚C, except as specified

A

Charge Pump Output Current V

Charge Pump TRI-STATE
Current

CP Sink vs
Source Mismatch (Note 4)

CP Current vs Voltage
(Note 3)

CP Current vs Temperature
(Note 5)

description.

CPo

=VP/2, I

D

o

V

=VP/2, I

D

o

V

=VP/2, I

D

o

V

=VP/2, I

D

o

0.5V ≤ V

−40˚c
V

=VP/2

D

o

= 25˚C

T

A

0.5V ≤ V
=

25˚C

T

A

V

=VP/2

D

o

−40˚C

D

o

<

T

A

D

o

<

T

Value

Min Typ Max

= HIGH** −4.5 mA

CP

o

= HIGH** 4.5 mA

CP

o

= LOW** −1.125 mA

CP

o

= LOW** 1.125 mA

CP

o

≤ VP− 0.5V

<

85˚C

−2.5 2.5 nA

310

≤ VP− 0.5V

<

85˚C

A

10 15

10

Units

%

%

%

www.national.com5

Charge Pump Current Specification Definitions

I1=CP sink current at V
I2=CP sink current at V
I3=CP sink current at V
I4=CP source current at V
I5=CP source current at V
I6=CP source current at V
∆V=Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V

3. I

4. I

5. I

=

vs V

Do

Do

1

*

[

⁄

2

{|I1| − |I3|}]/[1⁄

vs I

Do-sink

Do-source

1

[|I2| − |I5|]/[

⁄

2

=

vs T

Do

A

@

[|I2

temp| − |I2@25˚C|]/|I2@25˚C|*100%and [|I5@temp| − |I5@25˚C|]/|I5@25˚C|*100

=

− ∆V

V

Do

P

=

/2

V

Do

P

=

∆V

Do

=

− ∆V

V

Do

P

=

/2

V

Do

P

=

∆V

Do

Charge Pump Output Current magnitude variation vs Voltage

*

2

{|I1| + |I3|}]*100%and [1⁄

=

Charge Pump Output Current Sink vs Source Mismatch

*

{|I2| + |I5|}]*100

Charge Pump Output Current magnitude variation vs Temperature

%

*

2

{|I4| − |I6|}]/[1⁄

*

2

{|I4| + |I6|}]*100

=

%

=

=

RF Sensitivity Test Block Diagram

Note: N=10,000 R=50 P=64
Note: Sensitivity limit is reached when the error of the divided RF output, F

LD, is ≥ 1 Hz.

o

DS012331-25

and ground. Typical values are between 0.5V and 1.0V.

CC

%

DS012331-28

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Typical Performance Characteristics

ICCvs V

CC

LMX2330A

ICCvs V

CC

LMX2332A

DS012331-31

ICCvs V

CC

LMX2331A

IDoTRI-STATE
vs D

Voltage

o

DS012331-32

Charge Pump Current vs DoVoltage

=

I

HIGH

CP

DS012331-33

DS012331-34

Charge Pump Current vs DoVoltage

=

I

LOW

CP

DS012331-4

DS012331-35

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Typical Performance Characteristics (Continued)

Charge Pump Current Variation
(See Note 3 under Charge Pump Current Specification
Definitions)

DS012331-36

RF Input Impedance

=

V

CC

2.7V to 5.5V, f

=

50 MHz to 3 GHz

IN

Sink vs Source Mismatch
(See Note 4 under Charge Pump Current Specification
Definitions)

DS012331-37

IF Input Impedance

=

V

CC

2.7V to 5.5V, f

=

10 MHz to 1000 MHz

IN

Marker 1=1 GHz, Real=101, Imag.=−144
Marker 2=2 GHz, Real=37, Imag.=−54
Marker 3=3 GHz, Real=22, Imag.=−2
Marker 4=500 MHz, Real=209, Imag.=−232

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DS012331-38

Marker 1=100 MHz, Real=589, Imag.=−209
Marker 2=200 MHz, Real=440, Imag.=−286
Marker 3=300 MHz, Real=326, Imag.=−287
Marker 4=500 MHz, Real=202, Imag.=−234

DS012331-39

Typical Performance Characteristics (Continued)

LMX2330A RF Sensitivity vs Frequency

LMX2332A RF Sensitivity vs Frequency

DS012331-40

LMX2331A RF Sensitivity vs Frequency

DS012331-41

IF Input Sensitivity vs Frequency

Oscillator Input Sensitivity vs Frequency

DS012331-42

DS012331-44

DS012331-43

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Functional Description

The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit N Counters (in­termediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATAregister, MSB first. The
data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE. The last two bits are the Con­trol Bits. The DATA is transferred into the counters as follows:

Control Bits DATA Location

C1 C2

0 0 IF R Counter
0 1 RF R Counter
1 0 IF N Counter
1 1 RF N Counter

DS012331-1

PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS)

If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.

DS012331-14

15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)

Divide

RatioR15R14R13R12R11R10R9R8R7R6R5R4R3R2R1

3 000000000000011
4 000000000000100

• •••••••••••••••

32767 111111111111111

Notes:

Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.

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Functional Description (Continued)

PROGRAMMABLE DIVIDER (N COUNTER)

The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data
format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter does not have don’t care
bits.

DS012331-15

7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
RF

Divide

N7N6N5N4N3N2N

Ratio

A

1

0 0000000
1 0000001

• •••••••

127 1111111

Note: Divide ratio: 0 to 127
B ≥ A

11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)

Divide

Ratio

B

N

18

N

17

N

16

N

15

3 00000000011
4 00000000100

• •••••••••••

2047 11111111111

Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
B ≥ A

PULSE SWALLOW FUNCTION

=

f

[(PxB)+A]xf

VCO

: Output frequency of external voltage controlled oscillator (VCO)

f

VCO

OSC

/R

B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter

(0 ≤ A ≤ 127 {RF}, 0 ≤ A ≤ 15 {IF}, A ≤ B)

: Output frequency of the external reference frequency oscillator

f

OSC

R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual moduIus prescaler (for IF ;P=8or16;

for RF ; LMX2330A: P=32 or 64 LMX2331A/32A: P=64 or 128)

PROGRAMMABLE MODES

Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump
TRI-STATE and the output of the F
grammable modes are shown in

Table 3

.

LD pin. The prescaler and powerdown modes are selected with bits N19 and N20. The pro-

o

Table 1

. Truth table for the programmable modes and FoLD output are shown in

IF

Divide

N7N6N5N4N3N2N

Ratio

A

1

0 XXX0000
1 XXX0001

• •••••••

15 XXX1111

X=DON’T CARE condition

N

14

N

13

N

12

N

11

N

10

N

9

Table 2

N
8

and

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Functional Description (Continued)

TABLE 1. Programmable Modes

C1 C2 R16 R17 R18 R19 R20

00

01

IF Phase

Detector Polarity

RF Phase

Detector Polarity

IF I

RF I

CP

CP

C1 C2 N19 N20

1 0 IF Prescaler Pwdn IF
1 1 RF Prescaler Pwdn RF

TABLE 2. Mode Select Truth Table

I

CP

Phase Detector Polarity DoTRI-STATE

0 Negative

Operation

Normal

o

(Note 6)IFPrescaler

LOW 8/9 32/33 64/65

1 Positive TRI-STATE HIGH 16/17 64/65 128/129

Note 6: The I
Note 7: Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective f

(to a high impedance state). The powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program mode is
loaded, the part will go into powerdown mode when the charge pump reaches a TRI-STATE condition. The R counter functionality does not become disabled until

both

IF and RF powerdown bits are activated. The MICROWIRE control register remains active and capable of loading and latching data during all of the powerdown

modes.

LOW current state=1/4xI

CPo

HIGH current.

CPo

TABLE 3. The FoLD (Pin 10) Output Truth Table

RF R[19]

(RF LD)

IF R[19]

(IF LD)

RF R[20]

(RF F

o

)

0000Disabled (Note 8)
0100IFLock Detect (Note 9)
1000RFLock Detect (Note 9)
1100RF/IF Lock Detect (Note 9)
X 0 0 1 IF Reference Divider Output
X 0 1 0 RF Reference Divider Output
X 1 0 1 IF Programmable Divider Output
X 1 1 0 RF Programmable Divider Output
0011Fastlock (Note 10)
0111ForInternal Use Only
1011ForInternal Use Only
1111Counter Reset (Note 11)

X=don’t care condition

Note 8: When the F
Note 9: Lock detect output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and a lock detect mode is selected, the pins output

is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.
Note 10: The Fastlock mode utilizes the F

occurs whenever the RF loop’s lcpo magnitude bit
Note 11: The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits then N counter resumes counting in “close”

alignment with the R counter. (The maximum error is one prescaler cycle.) If the Reset bits are activated the R counter is also forced to Reset, allowing smooth ac­quisition upon powering up.

LD output is disabled, it is actively pulled to a low logic state.

o

LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock

o

#

17 is selected HIGH (while the#19 and#20 mode bits are set for Fastlock).

o

o

IF D

o

TRI-STATE

RF D

o

TRI-STATE

IF R[20]

(IF Fo)

IF LD IF F

RF LD RF F

2330A RF
Prescaler

o

o

2331A/32A RF

Prescaler

Output State

F

o

Pwdn

(Note 7)

Pwrd

Up

Pwrd

Dn

IN

inputs

www.national.com 12

Functional Description (Continued)

PHASE DETECTOR POLARITY

Depending upon VCO characteristics, R16 bit should be set
accordingly: (see figure right)

When VCO characteristics are positive like (1), R16 should
be set HIGH;

When VCO characteristics are negative like (2), R16 should
be set LOW.

SERIAL DATA INPUT TIMING

VCO Characteristics

DS012331-16

Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V

amplitudes of 2.2V@V

=

2.7V and 2.6V

CC

=

@

V

5.5V.

CC

/2. The test waveform has an edge rate of 0.6V/ns with

CC

PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS

Notes: Phase difference detection range: −2π to +2π

The minimum width pump up and pump down current pulses occur at the D
R16=HIGH

pin when the loop is locked.

o

DS012331-17

DS012331-18

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Typical Application Example

Operational Notes:

*

VCO is assumed AC coupled.

**

RINincreases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to
200Ω depending on the VCO power level. f

***

50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products a
CMOS clock is used and no terminating resistor is required. OSC
mended because the input circuit provides its own bias. (See

****

Adding RC filters to the VCCline is recommended to reduce loop-to-loop noise coupling.

Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board
layout.

This is an electrostatic sensitive device. It should be handled only at static free work stations.

www.national.com 14

RF impedance ranges from 40Ω to 100Ω.fINIF impedances are higher.

IN

may be AC or DC coupled. AC coupling is recom-

in

Figure

below)

DS012331-20

DS012331-19

Application Information

A block diagram of the basic phase locked loop is shown in

FIGURE 1. Basic Charge Pump Phase Locked Loop

LOOP GAIN EQUATIONS

A linear control system model of the phase feedback for a
PLL in the locked state is shown in
gain is the product of the phase comparator gain (Kφ), the
VCO gain (K
the gain of the feedback counter modulus (N). The passive

/s), and the loop filter gain Z(s) divided by

VCO

loop filter configuration used is displayed in
the complex impedance of the filter is given in

FIGURE 2. PLL Linear Model

FIGURE 3. Passive Loop Filter

The time constants which determine the pole and zero fre­quencies of the filter transfer function can be defined as

and

T2=R2

The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time constants T1 and T2,
and the design constants K

Figure 2

. The open loop

DS012331-22

C2 (4)

•

, and N.

φ,KVCO

Figure 3

Equation (2)

DS012331-23

, while

(1)

(2)

(3)

Figure 1

.

DS012331-21

From

Equation (3)

we can see thatthe phase term will be de­pendent on the single pole and zero such that the phase
margin is determined in

.

φ(ω)=tan

Equation (6)

−1

(ω•T2) − tan−1(ω•T1) + 180˚ (6)

.

A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in

φ

shows the amount of phase margin that exists at the point

p

the gain drops below zero (the cutoff frequency wp of the

Figure 4

with a solid trace. The parameter

loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.

If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band­width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison fre­quency also diminishes, the spurs would have increased by
approximately 6 dB. In the proposed Fastlock scheme, the
higher spur levels and wider loop filter conditions would exist
only during the initial lock-on phase— just long enough to
reap the benefits of locking faster. The objective would be to
open up the loop bandwidth but not introduce any additional
complications or compromises related to our original design
criteria. We would ideally like to momentarily shift the curve
of

Figure 4

over to a different cutoff frequency, illustrated by
the dotted line, without affecting the relative open loop gain
and phase relationships. To maintain the same gain/phase
relationship at twice the original cutofffrequency, other terms
in the gain and phase
sate by the corresponding “1/w”or “1/w
of

Equations (3), (4), (6)

Equations (5), (6)

will have to compen-

2

” factor.Examination

indicates the damping resistor vari­able R2 could be chosen to compensate the “w”’ terms for
the phase margin. This implies that another resistor of equal
value to R2will need to be switched in parallel withR2 during
the initial lock period. We must also ensure that the magni­tude of the open loop gain, H(s)G(s) is equal to zero at wp’
2wp. K

,Kφ, N, or the net product of these terms can be

vco

changed by a factor of 4, to counteract the w
in the denominator of

Equations (3), (4)

chosen to complete the transformation because it can
readily be switch between 1X and 4X values. This is accom­plished by increasing the charge pump output current from 1
mA in the standard mode to 4 mA in Fastlock.

(5)

2

term present

. The Kφ term was

=

www.national.com15

Application Information (Continued)

FIGURE 4. Open Loop Response Bode Plot

FASTLOCK CIRCUIT IMPLEMENTATION

A diagram of the Fastlock scheme as implemented in Na­tional Semiconductors LMX233xAPLL is shown in
When a new frequency is loaded, and the RF Icp
high the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2 resistor
element to ground. The usercalculates the loop filter compo­nent values for the normal steady state considerations. The
device configuration ensures that as long as a second iden-

Figure 5

bit is set

o

DS012331-29

tical damping resistor is wired in appropriately, the loop will
lock faster without any additional stability considerations to

.

account for. Once locked on the correct frequency, the user
can return the PLL to standard low noise operation by send­ing a MICROWIRE instruction with the RF Icp
This transition does not affect the charge on the loop filter
capacitors and is enacted synchronous with the charge
pump output. This creates a nearly seamless change be­tween Fastlock and standard mode.

bit set low.

o

FIGURE 5. Fastlock PLL Architecture

www.national.com 16

DS012331-30

Physical Dimensions inches (millimeters) unless otherwise noted

LMX2330A/LMX2331A/LMX2332A PLLatinum Dual Frequency Synthesizer for RF Personal

Communications

20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM)

Order Number LMX2330ATM, LMX2331ATM or LMX2332ATM

*

For Tape and Reel (2500 units per reel)

Order Number LMX2330ATMX, LMX2331ATMX or LMX2332ATMX

NS Package Number MTC20

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support device or system whose failure to perform
can be reasonably expected to cause the failure of
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labeling, can be reasonably expected to result in a
significant injury to the user.

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