Datasheet LMX2315WG-MLS, LMX2315TM Datasheet (NSC)

TL/W/12339

LMX2315/LMX2320/LMX2325 PLLatinum Frequency

Synthesizer for RF Personal Communications

LMX2325 2.5 GHz LMX2320 2.0 GHz LMX2315 1.2 GHz

September 1996

LMX2315/LMX2320/LMX2325 PLLatinum

TM

Frequency Synthesizer for RF Personal Communications LMX2325 2.5 GHz LMX2320 2.0 GHz LMX2315 1.2 GHz

General Description

The LMX2315/2320/2325’s are high performance frequency synthesizers with integrated prescalers designed for RF operation up to 2.5 GHz. They are fabricated using National’s ABiC IV BiCMOS process.

A 64/65 or a 128/129 divide ratio can be selected for the LMX2315 and LMX2320 RF synthesizer at input frequencies of up to 1.2 GHz and 2.0 GHz, while 32/33 and 64/65 divide ratios are available in the 2.5 GHz LMX2325. Using a proprietary digital phase locked loop technique, the LMX2315/ 2320/2325’s linear phase detector characteristics can generate very stable, low noise signals for controlling a local oscillator.

Serial data is transferred into the LMX2320 and the LMX2325 via a three line MICROWIRE

TM

interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The LMX2315, LMX2320 and the LMX2325 feature very low current consumption, typically 6 mA, 10 mA and 11 mA respectively.

The LMX2315, LMX2320 and the LMX2325 are available in a TSSOP 20-pin surface mount plastic package.

Features

Y

RF operation up to 2.5 GHz

Y

2.7V to 5.5V operation

Y

Low current consumption

Y

Dual modulus prescaler: LMX2325 32/33 or 64/65 LMX2320/LMX2315 64/65 or 128/129

Y

Internal balanced, low leakage charge pump

Y

Power down feature for sleep mode: I

CC

e

30 mA (typ) at V

CC

e

3V

Y

Small-outline, plastic, surface mount TSSOP, 0.173

×

wide

Applications

Y

Cellular telephone systems (GSM, IS-54, IS-95, (RCR-27)

Y

Portable wireless communications (DECT, PHS)

Y

CATV

Y

Other wireless communication systems

Block Diagram

TL/W/12339– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation. MICROWIRE

TM

and PLLatinumTMare trademarks of National Semiconductor Corporation.

C

1996 National Semiconductor Corporation RRD-B30M106/Printed in U. S. A.

http://www.national.com

Connection Diagrams

LMX2315/LMX2320/LMX2325

TL/W/12339– 2

20-Lead (0.173×Wide) Thin Shrink Small Outline Package (TM)

Order Number LMX2315TM, LMX2315TMX, LMX2325TM, LMX2325TMX, LMX2320TM or LMX2320TMX

See NS Package Number MTC20

Pin Descriptions

Pin No. Pin Name I/O Description

1 OSC

IN

I Oscillator input. A CMOS inverting gate input intended for connection to a crystal resonator for

operation as an oscillator. The input has a V

CC

/2 input threshold and can be driven from an external

CMOS or TTL logic gate. May also be used as a buffer for an externally provided reference oscillator.

3 OSC

OUT

O Oscillator output.

4V

P

Power supply for charge pump. Must betVCC.

5V

CC

Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane.

6DoO Internal charge pump output. For connection to a loop filter for driving the input of an external VCO.

7 GND Ground.

8 LD O Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’. When the loop is

locked, the pin’s output is HIGH with narrow low pulses.

10 f

IN

I Prescaler input. Small signal input from the VCO.

11 CLOCK I High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various counters

and registers.

13 DATA I Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input.

14 LE I Load enable input (with internal pull-up resistor). When LE transitions HIGH, data stored in the shift

registers is loaded into the appropriate latch (control bit dependent). Clock must be low when LE toggles high or low. See Serial Data Input Timing Diagram.

15 FC I Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of the phase

comparator and charge pump combination is reversed.

16 BISW O Analog switch output. When LE is HIGH, the analog switch is ON, routing the internal charge pump

output through BISW (as well as through D

o

).

17 f

OUT

O Monitor pin of phase comparator input. CMOS output.

18 w

p

O Output for external charge pump. wpis an open drain N-channel transistor and requires a pull-up

resistor.

19 PWDN I Power Down (with internal pull-up resistor).

PWDN

e

HIGH for normal operation.

PWDN

e

LOW for power saving.

Power down function is gated by the return of the charge pump to a TRI-STATE

É

condition.

20 w

r

O Output for external charge pump. wris a CMOS logic output.

2,9,12 NC No connect.

http://www.national.com 2

Functional Block Diagram

TL/W/12339– 3

Note 1: The prescalar for the LMX2315 and LMX2320 is either 64/65 or 128/129, while the prescalar for the LMX2325 is 32/33 or 64/65.

Note 2: The power down function is gated by the charge pump to prevent unwanted frequency jumps. Once the power down pin is brought low the part will go into

power down mode when the charge pump reaches a TRI-STATE condition.

http://www.national.com3

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Power Supply Voltage

V

CC

b

0.3V toa6.5V

V

P

b

0.3V toa6.5V

Voltage on Any Pin

with GND

e

0V (VI)

b

0.3V toa6.5V

Storage Temperature Range (TS)

b

65§Ctoa150§C

Lead Temperature (TL) (solder, 4 sec.)

a

260§C

Recommended Operating Conditions

Power Supply Voltage

V

CC

2.7V to 5.5V

V

P

VCCtoa5.5V

Operating Temperature (TA)

b

40§Ctoa85§C

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.

Note 2: This device is a high performance RF integrated circuit with an ESD rating

k

2 kV and is ESD sensitive. Handling and assembly of this device

should be done at ESD workstations.

Electrical Characteristics

LMX2325 and LMX2320 V

CC

e

V

P

e

3.0V; LMX2315 V

CC

e

V

P

e

5.0V;b40§CkT

A

k

85§C, except as specified

Symbol Parameter Conditions Min Typ Max Units

I

CC

Power Supply Current LMX2315 V

CC

e

3.0V 6.0 8.0 mA

V

CC

e

5.0V 6.5 8.5 mA

LMX2320 V

CC

e

3.0V 10 13.5 mA

LMX2325 V

CC

e

3.0V 11 15 mA

I

CC-PWDN

Power Down Current V

CC

e

3.0V 30 180 mA

V

CC

e

5.0V 60 350 mA

f

IN

Maximum Operating Frequency LMX2315 1.2

LMX2320 2.0 GHz

LMX2325 2.5

f

OSC

Oscillator Frequency 5 20 MHz

No Load on OSC

out

5 40 MHz

f

w

Phase Detector Frequency 10 MHz

Pf

IN

Input Sensitivity V

CC

e

2.7V to 3.3V

b

15

a

6

dBm

V

CC

e

3.3V to 5.5V

b

10

a

6

V

OSC

Oscillator Sensitivity OSC

IN

0.5 V

PP

V

IH

High-Level Input Voltage * 0.7 V

CC

V

IL

Low-Level Input Voltage * 0.3 V

CC

V

I

IH

High-Level Input Current (Clock, Data) V

IH

e

V

CC

e

5.5V

b

1.0 1.0 mA

I

IL

Low-Level Input Current (Clock, Data) V

IL

e

0V, V

CC

e

5.5V

b

1.0 1.0 mA

I

IH

Oscillator Input Current V

IH

e

V

CC

e

5.5V 100 mA

I

IL

V

IL

e

0V, V

CC

e

5.5V

b

100 mA

I

IH

High-Level Input Current (LE, FC) V

IH

e

V

CC

e

5.5V

b

1.0 1.0 mA

I

IL

Low-Level Input Current (LE, FC) V

IL

e

0V, V

CC

e

5.5V

b

100 1.0 mA

*Except fINand OSC

IN

http://www.national.com 4

Electrical CharacteristicsLMX2325 and LMX2320 V

CC

e

V

P

e

3.0V; LMX2315 V

CC

e

V

P

e

5.0V;b40§C

k

T

A

k

85§C, except as specified (Continued)

Symbol Parameter Conditions Min Typ Max Units

I

Do-source

Charge Pump Output Current V

CC

e

V

P

e

3.0V, V

D

o

e

VP/2

b

2.5 mA

I

Do-sink

V

CC

e

V

P

e

3.0V, V

D

o

e

VP/2 2.5 mA

I

Do-source

Charge Pump Output Current V

CC

e

V

P

e

5.0V, V

D

o

e

VP/2

b

5.0 mA

I

Do-sink

V

CC

e

V

P

e

5.0V, V

D

o

e

VP/2 5.0 mA

I

Do-Tri

Charge Pump TRI-STATEÉCurrent 0.5VsV

D

o

s

V

P

b

0.5V

b

2.5 2.5 nA

T

e

85§C

I

D

o

vs V

D

o

Charge Pump Output Current 0.5VsV

D

o

s

V

P

b

0.5V

Magnitude Variation vs Voltage T

e

25§C15%

(Note 1)

I

Do-sink

vs Charge Pump Output Current V

D

o

e

VP/2

I

Do-source

Sink vs Source Mismatch Te25§C10% (Note 2)

I

D

o

vs T Charge Pump Output Current

b

40§CkTk85§C

Magnitude Variation vs Temperature V

D

o

e

VP/2 10 %

(Note 3)

V

OH

High-Level Output Voltage I

OH

eb

1.0 mA** V

CC

b

0.8 V

V

OL

Low-Level Output Voltage I

OL

e

1.0 mA** 0.4 V

V

OH

High-Level Output Voltage (OSC

OUT

)I

OH

eb

200 mAV

CC

b

0.8 V

V

OL

Low-Level Output Voltage (OSC

OUT

)I

OL

e

200 mA 0.4 V

I

OL

Open Drain Output Current (wp)V

CC

e

5.0V, V

OL

e

0.4V 1.0 mA

I

OH

Open Drain Output Current (wp)V

OH

e

5.5V 100 mA

R

ON

Analog Switch ON Resistance (2315) 100 X

t

CS

Data to Clock Set Up Time See Data Input Timing 50 ns

t

CH

Data to Clock Hold Time See Data Input Timing 10 ns

t

CWH

Clock Pulse Width High See Data Input Timing 50 ns

t

CWL

Clock Pulse Width Low See Data Input Timing 50 ns

t

ES

Clock to Enable Set Up Time See Data Input Timing 50 ns

t

EW

Enable Pulse Width See Data Input Timing 50 ns

**Except OSC

OUT

Notes 1, 2, 3: See related equations in Charge Pump Current Specification Definitions

http://www.national.com5

Typical Performance Characteristics

ICCvs VCCLMX2320/25

TL/W/12339– 4

ICCvs VCCLMX2315

TL/W/12339– 51

Charge Pump Current vs DoVoltage

TL/W/12339– 40

Charge Pump Current vs DoVoltage

TL/W/12339– 7

Charge Pump Current Variation

TL/W/12339– 8

Sink vs Source Mismatch vs DoVoltage

TL/W/12339– 9

http://www.national.com 6

Typical Performance Characteristics (Continued)

I

D

o

TRI-STATE vs DoVoltage

TL/W/12339– 5

Oscillator Input Sensitivity

TL/W/12339– 14

LMX2320/25 Input Sensitivity vs Frequency

TL/W/12339– 10

LMX2320/25 Input Sensitivity vs Frequency

TL/W/12339– 11

LMX2315 Input Sensitivity vs Frequency

TL/W/12339– 41

LMX2315 Input Sensitivity vs Frequency

TL/W/12339– 42

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Typical Performance Characteristics (Continued)

LMX2320/25 Input Sensitivity at Temperature Variation, V

CC

e

3V

TL/W/12339– 12

LMX2320/25 Input Sensitivity at Temperature Variation, V

CC

e

5V

TL/W/12339– 13

LMX2315 Input Sensitivity at Temperature Variation, V

CC

e

5V

TL/W/12339– 43

LMX2315 Input Sensitivity at Temperature Variation, V

CC

e

3V

TL/W/12339– 44

LMX2315 Input Impedance vs Frequency

V

CC

e

2.7V to 5.5V, f

IN

e

100 MHz to 1,600 MHz

TL/W/12339– 45

Marker 1e500 MHz, Reale69, Imag.eb330 Marker 2

e

900 MHz, Reale36, Imag.eb193

Marker 3

e

1 GHz, Reale35, Imag.eb172

Marker 4

e

1,500 MHz, Reale30, Imag.eb106

LMX2320/25 Input Impedance vs Frequency

V

CC

e

2.7V to 5.5V, f

IN

e

500 MHz to 3000 MHz

TL/W/12339– 15

1e1.5 GHz, Reale48, Imeb128 2

e

1.8 GHz, Reale44, Imeb102

3

e

2.0 GHz, Reale42, Imeb90

4

e

2.5 GHz, Reale36, Imeb72

http://www.national.com 8

Charge Pump Current Specification Definitions

TL/W/12339– 16

I1eCP sink current at V

D

o

e

V

P

b

DV

I2

e

CP sink current at V

D

o

e

VP/2

I3

e

CP sink current at V

D

o

e

DV

I4

e

CP source current at V

D

o

e

V

P

b

DV

I5

e

CP source current at V

D

o

e

VP/2

I6

e

CP source current at V

D

o

e

DV

e

Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCCand ground. Typical values are between 0.5V and 1.0V.

1. I

D

o

vs V

D

o

e

Charge Pump Output Current magnitude variation vs Voltage

e

[

(/2 *

lI1lblI3l

]/[

(/2 *

À

lI1lalI3l

Ó

]

* 100% and[(/2 *

lI4lblI6l

]/[

(/2 *

À

lI4lalI6l

Ó

]

* 100%

2. I

D

o-sink

vs I

D

o-source

e

Charge Pump Output Current Sink vs Source Mismatch

e

[

lI2lblI5l

]/[

(/2 *

À

lI2lalI5l

Ó

]

* 100%

3. I

D

o

vs T

A

e

Charge Pump Output Current magnitude variation vs Temperature

e

[

l

I2@temp

lbl

I2@25§C

l

]

/

l

I2@25§Cl* 100% and

[

l

I5@temp

lbl

I5@25§C

l

]

/

l

I5@25§Cl* 100%

4. Kw

e

Phase detector/charge pump gain constant

e

(/2 *

À

lI2lalI5l

Ó

RF Sensitivity Test Block Diagram

TL/W/12339– 17

Note 1: Ne10,000 Re50 Pe64

Note 2: Sensitivity limit is reached when the error of the divided RF output, f

OUT

, is greater than or equal to 1 Hz.

http://www.national.com9

Functional Description

The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the S Latch, and the 18-bit N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first. If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the S Latch (prescaler select: LMX2315 and LMX2320: 64/65 or 128/129; LMX2325 32/33 or 64/65). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter (programmable divider).

TL/W/12339– 18

PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (S LATCH)

If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit latch (which sets the 14-bit R Counter) and the 1-bit S Latch (S15, which sets the prescaler: 64/65 or 128/129 for the LMX2315/20 or 32/33 or 64/65 for the LMX2325). Serial data format is shown below.

TL/W/12339– 6

14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)

Divide

14S13S12S11S10

SS9S8S7S6S5S4S3S2S

1

Ratio

R

3 00000000000011

4 00000000000100

# ##############

16383 1 1111111111111

Notes: Divide ratios less than 3 are prohibited.

Divide ratio: 3 to 16383

S1 to S14: These bits select the divide ratio of the programmable reference divider.

C: Control bit (set to HIGH level to load R counter and S Latch)

Data is shifted in MSB first.

Prescaler Select

15

S

LMX2315/20 LMX2325

128/129 64/65 0

64/65 32/33 1

http://www.national.com 10

Functional Description (Continued)

PROGRAMMABLE DIVIDER (N COUNTER)

The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bit (last bit shifted into the Data Register) is LOW, data is transferred from the 19-bit shift register into a 7-bit latch (which sets the 7-bit Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter). Serial data format is shown below.

TL/W/12339– 20

Note: S8 to S18: Programmable counter divide ratio control bits (3 to 2047)

7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)

Divide

S7S6S5S4S3S2S

1

Ratio

A

0 0000000

1 0000001

# #######

127 1111111

Note: Divide ratio: 0 to 127

B

t

A

11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)

Divide

18S17S16S15S14S13S12S11S10

SS9S

8

Ratio

B

3 00000000011

4 00000000100

# ###########

2047 1 1 1 1 1 1 1 1 1 1 1

Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)

B

t

A

PULSE SWALLOW FUNCTION

f

VCO

e

[

(P

c

B)aA

]

c

f

OSC

/R

f

VCO

: Output frequency of external voltage controlled oscil-

lator (VCO)

B: Preset divide ratio of binary 11-bit programmable

counter (3 to 2047)

A: Preset divide ratio of binary 7-bit swallow counter

(0

sAs

127, AsB)

f

OSC

: Output frequency of the external reference frequency

oscillator

R: Preset divide ratio of binary 14-bit programmable ref-

erence counter (3 to 16383)

P: Preset modulus of dual moduIus prescaler (64 or 128

for 2315/20 or 32 or 64 for 2325)

http://www.national.com11

Functional Description (Continued)

SERIAL DATA INPUT TIMING

TL/W/12339– 21

Notes: Parenthesis data indicates programmable reference divider data.

Data shifted into register on clock rising edge.

Data is shifted in MSB first.

Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V

CC

/2. The test waveform has an edge rate of 0.6 V/ns with

amplitudes of 2.2V

@

V

CC

e

2.7V and 2.6V@V

CC

e

5.5V.

Phase Characteristics

In normal operation, the FC pin is used to reverse the polarity of the phase detector. Both the internal and any external charge pump are affected.

Depending upon VCO characteristics, FC pin should be set accordingly:

When VCO characteristics are like (1), FC should be set HIGH or OPEN CIRCUIT;

When VCO characteristics are like (2), FC should be set LOW.

When FC is set HIGH or OPEN CIRCUIT, the monitor pin of the phase comparator input, f

out

, is set to the reference

divider output, f

r

. When FC is set LOW, f

out

is set to the

programmable divider output, f

p

.

VCO Characteristics

TL/W/12339– 22

PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS

TL/W/12339– 23

Notes: Phase difference detection range:b2q toa2q

The minimum width pump up and pump down current pulses occur at the Dopin when the loop is locked.

FC

e

HIGH

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Analog Switch

The analog switch is useful for radio systems that utilize a frequency scanning mode and a narrow band mode. The purpose of the analog switch is to decrease the loop filter time constant, allowing the VCO to adjust to its new frequency in a shorter amount of time. This is achieved by adding another filter stage in parallel. The output of the charge pump is normally through the D

o

pin, but when LE is set HIGH, the charge pump output also becomes available at BISW. A typical circuit is shown below. The

second filter stage (LPF-2) is effective only when the switch is closed (in the scanning mode).

TL/W/12339– 24

Typical Crystal Oscillator Circuit

A typical circuit which can be used to implement a crystal oscillator is shown below.

TL/W/12339– 52

Typical Lock Detect Circuit

A lock detect circuit is needed in order to provide a steady LOW signal when the PLL is in the locked state. A typical circuit is shown below.

TL/W/12339– 26

http://www.national.com13

Typical Application Example

Operational Notes:

TL/W/12339– 27

* VCO is assumed AC coupled.

** R

IN

increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10X to 200X depending on the VCO power

level. f

IN

RF impedance ranges from 40X to 100 X.

*** 50X termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating

resistor is required. OSC

IN

may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See

Figure

below)

Layout Hints:

TL/W/12339– 28

Proper use of grounds and bypass capacitors is essential to achieve a high level of performance.

Crosstalk between pins can be reduced by careful board layout.

This is a static sensitive device. It should be handled only at static free work stations.

http://www.national.com 14

Application Information

LOOP FILTER DESIGN

A block diagram of the basic phase locked loop is shown.

TL/W/12339– 29

FIGURE 1. Basic Charge Pump Phase Locked Loop

An example of a passive loop filter configuration, including the transfer function of the loop filter, is shown in

Figure 2

.

TL/W/12339– 30

Z(s)

e

s (C2#R2)a1

s2(C1#C2#R2)asC1asC2

FIGURE 2. 2nd Order Passive Filter

Define the time constants which determine the pole and zero frequencies of the filter transfer function by letting

T2

e

R2#C2 (1a)

and

T1

e

R2

#

C1#C2

C1aC2 (1b)

The PLL linear model control circuit is shown along with the open loop transfer function in

Figure 3

. Using the phase

detector and VCO gain constants[Kw and K

VCO

]

and the loop filter transfer function[Z(s)], the open loop Bode plot can be calculated. The loop bandwidth is shown on the Bode plot (

0p) as the point of unity gain. The phase margin

is shown to be the difference between the phase at the unity gain point and

b

180§.

TL/W/12339– 32

Open Loop Gaineii/i

e

H(s) G(s)

e

Kw Z(s) K

VCO

/Ns

Closed Loop Gaineio/i

i

e

G(s)/[1aH(s) G(s)

]

TL/W/12339– 31

FIGURE 3. Open Loop Transfer Function

Thus we can calculate the 3rd order PLL Open Loop Gain in terms of frequency

G(s)

#

H(s)

l

sej

#

0

e

b

Kw#K

VCO

(1aj0#T2)

0

2

C1#N(1aj0#T1)

#

T1

T2 (2)

From equation 2 we can see that the phase term will be dependent on the single pole and zero such that

w(

0)

e

tan

b

1

(0#T2)btan

b

1

(0#T1)a180§(3)

By setting

dw d0

e

T2

1a(0#T2)

2

b

T1

1a(0#T1)

2

e

0

(4)

we find the frequency point corresponding to the phase inflection point in terms of the filter time constants T1 and T2. This relationship is given in equation 5.

0

p

e

1/0T2#T1 (5)

For the loop to be stable the unity gain point must occur before the phase reaches

b

180 degrees. We therefore want the phase margin to be at a maximum when the magnitude of the open loop gain equals 1. Equation 2 then gives

C1

e

Kw#K

VCO

#

T1

0

p

2

#N#

T2

Ó

(1aj0

p

#

T2)

(1aj0

p

#

T1)

Ó

(6)

http://www.national.com15

Application Information (Continued)

Therefore, if we specify the loop bandwidth,

0

p

, and the

phase margin, w

p

, Equations 1 through 6 allow us to calculate the two time constants, T1 and T2, as shown in equations 7 and 8. A common rule of thumb is to begin your design with a 45

§

phase margin.

T1

e

secw

p

b

tanw

p

0

p

(7)

T2

e

1

0

p

2

#

T1 (8)

From the time constants T1, and T2, and the loop bandwidth,

0

p

, the values for C1, R2, and C2 are obtained in

equations 9 to 11.

C1

e

T1

T2

#

Kw#K

VCO

0

p

2

#

N

0

1a(0

p

#

T2)

2

1a(0

p

#

T1)

2

(9)

C2

e

C1

#

T2

T1

b

1

J

(10)

R2

e

T2

C2 (11)

K

VCO

(MHz/V) Voltage Controlled Oscillator (VCO)

Tuning Voltage constant. The frequency vs voltage tuning ratio.

Kw (mA) Phase detector/charge pump gain

constant. The ratio of the current output to the input phase differential.

N Main divider ratio. Equal to RF

opt/fref

RF

opt

(MHz) Radio Frequency output of the VCO at

which the loop filter is optimized.

f

ref

(kHz) Frequency of the phase detector in-

puts. Usually equivalent to the RF channel spacing.

In choosing the loop filter components a trade off must be made between lock time, noise, stability, and reference spurs. The greater the loop bandwidth the faster the lock time will be, but a large loop bandwidth could result in higher reference spurs. Wider loop bandwidths generally improve close in phase noise but may increase integrated phase noise depending on the reference input, VCO and division ratios used. The reference spurs can be reduced by reducing the loop bandwidth or by adding more low pass filter stages but the lock time will increase and stability will decrease as a result.

THIRD ORDER FILTER

A low pass filter section may be needed for some applications that require additional rejection of the reference sidebands, or spurs. This configuration is given in

Figure 4

.In order to compensate for the added low pass section, the component values are recalculated using the new open loop unity gain frequency. The degradation of phase margin caused by the added low pass is then mitigated by slightly increasing C1 and C2 while slightly decreasing R2.

The added attenuation from the low pass filter is:

ATTEN

e

20 log[(2qf

ref

#R3#

C3)

2

a

1](12)

Defining the additional time constant as

T3eR3#C3 (13)

Then in terms of the attenuation of the reference spurs added by the low pass pole we have

T3

e

0

10

ATTEN/20

b

1

(2q#f

ref

)

2

(14)

We then use the calculated value for loop bandwidth

0

c

in equation 11, to determine the loop filter component values in equations 15 –17.

0

c

is slightly less than 0p, therefore

the frequency jump lock time will increase.

T2

e

1

0

c

2

#

(T1aT3) (15)

0

c

e

tanw#(T1aT3)

[

(T1

a

T3)

2

a

T1#T3

]

#

Ð0

1

a

(T1aT3)

2

a

T1#T3

[

tanw

#

(T1aT3)

]

2

b

1

(

(16)

C1

e

T1

T2

#

Kw#K

VCO

0

c

2

#

N

#

Ð

(1

a

0

c

2

#

T22)

(1

a

0

c

2

#

T12)(1

a

0

c

2

#

T32)

(

(/2

(17)

http://www.national.com 16

Application Information (Continued)

Consider the following application examples:

Example

Ý

1

K

VCO

e

20 MHz/V

Kw

e

5 mA (Note 1)

RF

opt

e

900 MHz

F

ref

e

200 kHz

NeRF

opt/fref

e

4500

0

p

e

2q * 20 kHze1.256e5

w

p

e

45

§

ATTENe20 dB

T1

e

secw

p

b

tanw

p

0

p

e

3.29eb6

T3

e

0

10

(20/20)

b

1

(2q#200e3)

2

e

2.387eb6

0

c

e

(3.29eb6a2.387eb6)

[

(3.29e

b6a

2.387eb6)

2

a

3.29eb6#2.387eb6

]

#

Ð0

1

a

(3.29eb6a2.387eb6)

2

a

3.29eb6#2.387eb6

[

(3.29e

b6a

2.387eb6)

]

2

b

1

(

e

7.045e4

T2

e

1

(7.045e4)

2

#

(3.29eb6a2.387eb6)

e

3.549eb5

C1

e

3.29eb6

3.549eb5

(5e

b

3)#20e6

(7.045e4)

2

#

4500

#

Ð

[

1

a

(7.045e4)

2

#

(3.549eb5)

2

]

[

1

a

(7.045e4)

2

#

(3.29eb6)

2

][

1

a

(7.045e4)

2

#

(2.387eb6)

2

]

(

(/2

e

1.085 nF

C2

e

1.085 nF

#

3.55eb5

3.29eb6

b

1

J

e

10.6 nF;

R2

e

3.55eb5

10.6eb9

e

3.35 kX;

if we choose R3

e

22k; then C3

e

2.34eb6

22e3

e

106 pF.

Converting to standard component values gives the following filter values, which are shown in

Figure 4

.

C1

e

1000 pF

R2

e

3.3 kX

C2

e

10 nF

R3

e

22 kX

C3

e

100 pF

Note 1: See related equation for K w in Charge Pump Current Specification

Definitions. For this example V

P

e

5.0V. The value of Kw can then be approximated using the curves in the Typical Peformance Characteristics for Charge Pump Current vs. D

o

Voltage. The units for

Kw are in mA. You may also use Kw

e

(5 mA/2q rad), but in this

case you must convert K

VCO

to (rad/V) multiplying by 2q.

TL/W/12339– 46

FIGURE 4.E20 kHz Loop Filter

http://www.national.com17

Application Information (Continued)

MEASUREMENT RESULTS (Example

Ý

1)

TL/W/12339– 47

FIGURE 5. PLL Reference Spurs

The reference spurious level is

k

b

74 dBc, due to the loop filter attenuation and the low spurious noise level of the LMX2315.

TL/W/12339– 49

FIGURE 6. PLL Phase Noise 10 kHz Offset

The phase noise level at 10 kHz offset is

b

80 dBc/Hz.

TL/W/12339– 48

FIGURE 7. PLL Phase Noise@1 kHz Offset

The phase noise level at 1 kHz offset isb79.5 dBc/Hz.

TL/W/12339– 50

FIGURE 8. Frequency Jump Lock Time

Of concern in any PLL loop filter design is the time it takes to lock in to a new frequency when switching channels.

Fig-

ure 8

shows the switching waveforms for a frequency jump of 865 MHz to 915 MHz. By narrowing the frequency span of the HP53310A Modulation Domain Analyzer enables evaluation of the frequency lock time to within

g

500 Hz. The lock time is seen to be less than 500 ms for a frequency jump of 50 MHz.

http://www.national.com 18

Application Information (Continued)

Example

Ý

2

K

VCO

e

34 MHz/V

Kwe2.8 mA (Note 1)

RF

opt

e

1665 MHz

F

ref

e

300 kHz

N

e

RF

opt/fref

e

5550

0

p

e

2q * 20 kHze1.256e5

w

p

e

43

ATTENe12 dB

T1

e

secwbtanw

0

p

e

3.462eb6

T3

e

0

10

(12/20)

b

1

(2q#300e3)

2

e

9.16eb7

0

c

e

tan43 (3.862eb6a9.16eb7)

(3.462eb6a9.16eb7)

2

a

3.462eb6#9.16eb7)

#

Ð0

1

a

(3.462eb6a9.16eb7)

2

a

3.462eb6#9.16eb7

[

tan43 (3.462e

b6a

9.16eb7)

]

2

b

1

(

T2

e

1

(9.682e4)2(3.462eb6a9.16eb7)

e

2.437eb5

C1

e

3.462eb6

2.437eb5

(2.8e

b

3)#34e6

(9.682e4)

2

#

5550

#

Ð

[

1

a

(9.682e4)

2

#

(2.437eb5)

2

]

[

1

a

(9.682e4)2(3.462eb6)

2

][

1

a

(9.682e4)

2

#

(9.16eb7)

2

]

(

(/2

e

0.63 nF

C2

e

0.63 nF

#

2.437eb5

3.402eb6

b

1

J

e

3.88 nF;

R2

e

2.437eb5

3.88eb9

e

6.28 kX;

if we choose R3

e

27k; then C3

e

9.16eb7

27e3

e

34 pF.

Converting to standard component values gives the following filter values, which are shown in

Figure 4

.

C1

e

560 pF

R2

e

6.8 kX

C2

e

2700 pF

R3

e

27 kX

C3

e

56 pF

Note 1: See related equation for K w in Charge Pump Current Specification

Definitions. For this example V

P

e

3.3V. The value for Kw can then be approximated using the curves in the Typical Performance Characteristics for Charge Pump Current vs. D

o

Voltage. The units for

Kw are in mA. You may also use K w

e

(2.8 mA/2q rad), but in this

case you must convert K

VCO

to (rad/V) multiplying by 2q.

TL/W/12339– 33

FIGURE 9.E20 kHz Loop Filter

http://www.national.com19

Application Information (Continued)

MEASUREMENT RESULTS (Example

Ý

2)

TL/W/12339– 34

FIGURE 10. PLL Reference Spurs

The reference spurious level is

k

b

65 dBc, due to the loop filter attenuation and the low spurious noise level of the LMX2320.

TL/W/12339– 36

FIGURE 12. PLL Phase Noise 20 kHz Offset

The phase noise level at 20 kHz offset is

b

80 dBc/Hz.

TL/W/12339– 35

FIGURE 11. PLL Phase Noise@150 Hz Offset

The phase noise level at 150 Hz offset isb81.1 dBc/Hz. The spurs at 60 and 180 Hz offset are due to 60 Hz line noise from the power supply.

TL/W/12339– 37

FIGURE 13. Frequency Jump Lock Time

Of concern in any PLL loop filter design is the time it takes to lock in to a new frequency when switching channels.

Fig-

ure 13

shows the switching waveforms for a frequency jump of 1650.9 MHz to 1683.9 MHz. By narrowing the frequency span of the HP53310A Modulation Domain Analyzer enables evaluation of the frequency lock time to within

g

1 kHz. The lock time is seen to be less than 500 ms for a

frequency jump of 33 MHz.

http://www.national.com 20

Application Information (Continued)

EXTERNAL CHARGE PUMP

The LMX PLLatinum series of frequency synthesizers are equipped with an internal balanced charge pump as well as outputs for driving an external charge pump. Although the superior performance of NSC’s on board charge pump eliminates the need for an external charge pump in most applications, certain system requirements are more stringent. In these cases, using an external charge pump allows the designer to take direct control of such parameters as charge pump voltage swing, current magnitude, TRI-STATE leakage, and temperature compensation.

One possible architecture for an external charge pump current source is shown in

Figure 14

. The signals wpand wrin the diagram, correspond to the phase detector outputs of the 2315/20/25 frequency synthesizers. These logic signals are converted into current pulses, using the circuitry shown in

Figure 14

, to enable either charging or discharging of the loop filter components to control the output frequency of the PLL.

Referring to

Figure 14

, the design goal is to generate a 5 mA current which is relatively constant to within 5V of the power supply rail. To accomplish this, it is important to establish as large of a voltage drop across R5, R8 as possible without saturating Q2, Q4. A voltage of approximately 300 mV provides a good compromise. This allows the current source reference being generated to be relatively repeatable in the absence of good Q1, Q2/Q3, Q4 matching. (Matched transistor pairs is recommended.) The wp and wr outputs are rated for a maximum output load current of 1 mA while 5 mA current sources are desired. The voltages developed across R4, 9 will consequently be approximately 258 mV, or 42 mV less than R8, 5, due to the current density differences

À

0.026*1n (5 mA/1 mA)Óthrough the Q1,

Q2/Q3, Q4 pairs.

In order to calculate the value of R7 it is necessary to first estimate the forward base to emitter voltage drop (Vfn,p) of the transistors used, the V

OL

drop of wp, and the VOHdrop

of wr’s under 1 mA loads. (wp’s V

OL

k

0.1V and (wr,s V

OH

k

0.1V).

Knowing these parameters along with the desired current allow us to design a simple external charge pump. Separating the pump up and pump down circuits facilitates the nodal analysis and give the following equations.

R

4

e

V

R5

b

V

T

#

1n

#

i

source

i

p max

J

i

source

R

9

e

V

R8

b

V

T

#

1n

#

i

sink

i

n max

J

i

sink

R

5

e

V

R5

#

(b

p

a

1)

i

p max

#

(b

p

a1)b

i

source

R

8

e

V

R8

#

(b

n

a

1)

i

r max

#

(b

n

a

1) i

sink

R

6

e

(V

p

b

V

VOLwp

)b(V

R5

a

Vfp)

i

p max

R

7

e

(V

P

b

V

VOHwp

)b(V

R8

a

Vfn)

i

max

EXAMPLE

Typical Device Parameters b

n

e

100, b

p

e

50

Typical System Parameters V

P

e

5.0V;

V

cntl

e

0.5V–4.5V;

V

wp

e

0.0V, V

wr

e

5.0V

Design Parameters I

SINK

e

I

SOURCE

e

5.0 mA;

VfneVfpe0.8V

I

r

max

e

I

p

max

e

1mA

V

R8

e

V

R5

e

0.3V

V

OLwp

e

V

OHwp

e

100 mV

TL/W/12339– 39

FIGURE 14

Therefore select

R

4

e

R

9

e

0.3Vb0.026#1n(5.0 mA/1.0 mA)

5mA

e

51.6X

R

5

e

0.3V#(50a1)

1.0 mA#(50a1)b5.0 mA

e

332X

R

8

e

0.3V#(100a1)

1.0 mA#(100a1)b5.0 mA

e

315.6X

R

6

e

R

7

e

(5Vb0.1V)b(0.3Va0.8V)

1.0 mA

e

3.8 kX

http://www.national.com21

LMX2315/LMX2320/LMX2325 PLLatinum Frequency

Synthesizer for RF Personal Communications

LMX2325 2.5 GHz LMX2320 2.0 GHz LMX2315 1.2 GHz

Physical Dimensions millimeters

NS Package Number MTC20

20-Lead (0.173

×

Wide) Thin Shrink Small Outline Package (TM)

Order Number LMX2315TM, LMX2320TM or LMX2325TM

For Tape and Reel Order Number LMX2315TMX, LMX2320TMX or LMX2325TMX (2500 Units per Reel)

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