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October 6, 2008
LMV831 Single/ LMV832 Dual/ LMV834 Quad
3.3 MHz Low Power CMOS, EMI Hardened Operational
Amplifiers
LMV831 Single/ LMV832 Dual/ LMV834 Quad 3.3 MHz Low Power CMOS, EMI Hardened
Operational Amplifiers
General Description
National’s LMV831, LMV832, and LMV834 are CMOS input,
low power op amp IC's, providing a low input bias current, a
wide temperature range of −40°C to 125°C and exceptional
performance making them robust general purpose parts. Additionally, the LMV831/LMV832/LMV834 are EMI hardened
to minimize any interference so they are ideal for EMI sensitive applications.
The unity gain stable LMV831/LMV832/LMV834 feature
3.3 MHz of bandwidth while consuming only 0.24 mA of current per channel. These parts also maintain stability for capacitive loads as large as 200 pF. The LMV831/LMV832/
LMV834 provide superior performance and economy in terms
of power and space usage.
This family of parts has a maximum input offset voltage of
1 mV, a rail-to-rail output stage and an input common-mode
voltage range that includes ground. Over an operating range
from 2.7V to 5.5V the LMV831/LMV832/LMV834 provide a
PSRR of 93 dB, and a CMRR of 91 dB. The LMV831 is offered
in the space saving 5-Pin SC70 package, the LMV832 in the
8-Pin MSOP and the LMV834 is offered in the 14-Pin TSSOP
package.
Typical Application
EMI Hardened Sensor Application
Features
Unless otherwise noted, typical values at TA= 25°C,
V+ = 3.3V
Supply voltage 2.7V to 5.5V
■
Supply current (per channel) 240 µA
■
Input offset voltage 1 mV max
■
Input bias current 0.1 pA
■
GBW 3.3 MHz
■
EMIRR at 1.8 GHz 120 dB
■
Input noise voltage at 1 kHz 12 nV/√Hz
■
Slew rate 2 V/µs
■
Output voltage swing Rail-to-Rail
■
Output current drive 30 mA
■
Operating ambient temperature range −40°C to 125°C
■
Applications
Photodiode preamp
■
Piezoelectric sensors
■
Portable/battery-powered electronic equipment
■
Filters/buffers
■
PDAs/phone accessories
■
30024101
© 2008 National Semiconductor Corporation 300241 www.national.com
Page 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2)
Human Body Model 2 kV
Charge-Device Model 1 kV
Machine Model 200V
V
Differential
IN
Supply Voltage (VS = V+ – V−)
Voltage at Input/Output Pins V++0.4V,
± Supply Voltage
6V
V− −0.4V
Storage Temperature Range −65°C to 150°C
Junction Temperature (Note 3) 150°C
Soldering Information
Infrared or Convection (20 sec) 260°C
Operating Ratings (Note 1)
Temperature Range (Note 3) −40°C to 125°C
Supply Voltage (VS = V+ – V−)
Package Thermal Resistance (θJA (Note 3))
5-Pin SC-70 302°C/W
8-Pin MSOP 217°C/W
14-Pin TSSOP 135°C/W
3.3V Electrical Characteristics (Note 4)
Unless otherwise specified, all limits are guaranteed for at TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, and RL =10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min
LMV831 Single/ LMV832 Dual/ LMV834 Quad
V
OS
TCV
I
B
I
OS
CMRR Common-Mode Rejection Ratio
PSRR Power Supply Rejection Ratio
EMIRR EMI Rejection Ratio, IN+ and IN-
CMVR Input Common-Mode Voltage Range
A
VOL
Input Offset Voltage
±0.25 ±1.00
(Note 9)
Input Offset Voltage Temperature Drift
OS
(Notes 9, 10)
LMV831,
LMV832
LMV834 ±0.5 ±1.7
Input Bias Current
0.1 10
(Note 10)
Input Offset Current 1
0.2V ≤ VCM ≤ V+ - 1.2V
(Note 9)
2.7V ≤ V+ ≤ 5.5V,
(Note 9)
(Note 8)
V
= 1V
OUT
V
=100 mVP (−20 dBP),
RF_PEAK
f = 400 MHz
V
=100 mVP (−20 dBP),
RF_PEAK
f = 900 MHz
V
=100 mVP (−20 dBP),
RF_PEAK
f = 1800 MHz
V
=100 mVP (−20 dBP),
RF_PEAK
f = 2400 MHz
CMRR ≥ 65 dB
Large Signal Voltage Gain
(Note 11)
RL = 2 kΩ,
V
= 0.15V to 1.65V,
OUT
V
= 3.15V to 1.65V
OUT
RL = 10 kΩ,
V
= 0.1V to 1.65V,
OUT
V
= 3.2V to 1.65V
OUT
LMV831,
LMV832
LMV834 102
LMV831,
LMV832
LMV834 104
(Note 6)
±0.5 ±1.5
76
75
76
75
80
90
110
120
−0.1 2.1
102
102
102
104
104
103
Typ
(Note 5)
91
93
121
121
126
123
(Note 6)
±1.23
2.7V to 5.5V
Max
500
Units
mV
μV/°C
pA
pA
dB
dB
dB
V
dB
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LMV831 Single/ LMV832 Dual/ LMV834 Quad
Symbol Parameter Conditions Min
(Note 6)
V
OUT
Output Voltage Swing High
RL = 2 kΩ to V+/2
LMV831,
LMV832
29 36
Typ
(Note 5)
Max
(Note 6)
43
Units
LMV834 31 38
44
RL = 10 kΩ to V+/2
LMV831,
LMV832
LMV834 7 9
6 8
9
mV from
either rail
10
Output Voltage Swing Low
R = 2 kΩ to V+/2
25 34
43
RL = 10 kΩ to V+/2
5 8
10
I
OUT
I
S
Output Short Circuit Current Sourcing, V
VIN = 100 mV
OUT
= VCM,
LMV831,
LMV832
27
22
LMV834 24
28
28
19
Sinking, V
VIN = −100 mV
OUT
= VCM,
27
21
32
Supply Current LMV831 0.24 0.27
mA
0.30
LMV832 0.46 0.51
0.58
mA
LMV834 0.90 1.00
1.16
SR Slew Rate (Note 7) AV = +1, V
10% to 90%
OUT
= 1 VPP,
2
V/μs
GBW Gain Bandwidth Product 3.3 MHz
Φ
m
e
n
i
n
R
OUT
C
IN
Phase Margin 65
Input Referred Voltage Noise Density f = 1 kHz 12
Input Referred Current Noise Density f = 1 kHz 0.005
Closed Loop Output Impedance f = 2 MHz 500
Common-mode Input Capacitance 15
Differential-mode Input Capacitance 20
THD+N Total Harmonic Distortion + Noise
f = 10 kHz 10
f = 1 kHz, AV = 1, BW ≥ 500 kHz
0.02
deg
nV/
pA/
Ω
pF
%
5V Electrical Characteristics (Note 4)
Unless otherwise specified, all limits are guaranteed for at TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL = 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min
(Note 6)
V
OS
Input Offset Voltage
±0.25 ±1.00
(Note 9)
TCV
Input Offset Voltage Temperature Drift
OS
(Notes 9, 10)
LMV831,
LMV832
LMV834 ±0.5 ±1.7
I
B
Input Bias Current
0.1 10
(Note 10)
I
OS
CMRR Common-Mode Rejection Ratio
Input Offset Current 1
(Note 9)
0V ≤ V
≤ V+ −1.2V
CM
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±0.5 ±1.5
77
77
Typ
(Note 5)
93
Max
(Note 6)
±1.23
500
Units
mV
μV/°C
pA
pA
dB
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Symbol Parameter Conditions Min
(Note 6)
PSRR Power Supply Rejection Ratio
(Note 9)
EMIRR EMI Rejection Ratio, IN+ and IN-
(Note 8)
2.7V ≤ V+ ≤ 5.5V,
V
= 1V
OUT
V
=100 mVP (−20 dBP),
RF_PEAK
f = 400 MHz
V
=100 mVP (−20 dBP),
RF_PEAK
76
75
80
90
Typ
(Note 5)
93
Max
(Note 6)
f = 900 MHz
V
=100 mVP (−20 dBP),
RF_PEAK
110
f = 1800 MHz
V
=100 mVP (−20 dBP),
RF_PEAK
120
f = 2400 MHz
CMVR Input Common-Mode Voltage Range
A
VOL
Large Signal Voltage Gain
(Note 11)
CMRR ≥ 65 dB
RL = 2 kΩ,
V
OUT
V
OUT
LMV831 Single/ LMV832 Dual/ LMV834 Quad
RL = 10 kΩ,
V
OUT
V
OUT
= 0.15V to 2.5V,
= 4.85V to 2.5V
= 0.1V to 2.5V,
= 4.9V to 2.5V
LMV831,
LMV832
LMV834 104
LMV831,
LMV832
LMV834 105
–0.1 3.8
107
127
106
127
104
107
130
107
127
104
V
OUT
Output Voltage Swing High
RL = 2 kΩ to V+/2
LMV831,
LMV832
32 42
49
LMV834 35 45
52
RL = 10 kΩ to V+/2
LMV831,
LMV832
6 9
10
LMV834 7 10
11
Output Voltage Swing Low
RL = 2 kΩ to V+/2
27 43
52
RL = 10 kΩ to V+/2
6 10
12
I
OUT
Output Short Circuit Current Sourcing V
VIN = 100 mV
OUT
= V
LMV831,
CM
LMV832
LMV834 57
59
49
66
63
45
Sinking V
VIN = −100 mV
OUT
= V
LMV831,
CM
LMV832
LMV834 53
50
41
64
63
41
I
S
Supply Current LMV831 0.25 0.27
0.31
LMV832 0.47 0.52
0.60
LMV834 0.92 1.02
1.18
SR Slew Rate (Note 7) AV = +1, V
OUT
= 2VPP,
2
10% to 90%
GBW Gain Bandwidth Product 3.3 MHz
Φ
m
e
n
Phase Margin 65
Input Referred Voltage Noise f = 1 kHz 12
f = 10 kHz 10
Units
dB
dB
V
dB
mV from
either rail
mA
mA
V/μs
deg
nV/
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LMV831 Single/ LMV832 Dual/ LMV834 Quad
Symbol Parameter Conditions Min
(Note 6)
i
n
R
OUT
C
IN
Input Referred Current Noise f = 1 kHz 0.005
Closed Loop Output Impedance f = 2 MHz 500
Common-mode Input Capacitance 14
Typ
(Note 5)
Max
(Note 6)
pA/
Differential-mode Input Capacitance 20
THD+N Total Harmonic Distortion + Noise
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics
Tables.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) FieldInduced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: The maximum power dissipation is a function of T
PD = (T
Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where
TJ > TA.
Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 6: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using statistical quality
control (SQC) method.
Note 7: Number specified is the slower of positive and negative slew rates.
Note 8: The EMI Rejection Ratio is defined as EMIRR = 20log ( V
Note 9: The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting distribution.
Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 11: The specified limits represent the lower of the measured values for each output range condition.
- TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
J(MAX)
f = 1 kHz, AV = 1, BW ≥ 500 kHz
, θJA, and TA. The maximum allowable power dissipation at any ambient temperature is
J(MAX)
/ΔVOS).
RF_PEAK
0.02
Units
Ω
pF
%
Connection Diagrams
5-Pin SC-70
Top View
30024102
8-Pin MSOP
Top View
30024103
14-Pin TSSOP
Top View
30024104
Ordering Information
Package Part Number Package Marking Transport Media NSC Drawing
5-Pin SC-70
8-Pin MSOP
14-Pin TSSOP
LMV831MG
AFA
LMV831MGX 3k Units Tape and Reel
LMV832MM
AU5A
LMV832MMX 3.5k Units Tape and Reel
LMV834MT
LMV834MTX 2.5k Units Tape and Reel
LMV834MT
1k Units Tape and Reel
1k Units Tape and Reel
94 Units/Rail
MAA05ALMV831MGE 250 Units Tape and Reel
MUA08ALMV832MME 250 Units Tape and Reel
MTC14
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Typical Performance Characteristics At T
specified.
= 25°C, RL = 10 kΩ, V+ = 3.3V, V− = 0V, Unless otherwise
A
VOS vs. VCM at V+ = 3.3V
LMV831 Single/ LMV832 Dual/ LMV834 Quad
30024110
VOS vs. Supply Voltage
VOS vs. VCM at V+ = 5.0V
30024111
VOS vs. Temperature
30024112
VOS vs. V
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OUT
30024114
30024113
Input Bias Current vs. VCM at 25°C
30024115
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LMV831 Single/ LMV832 Dual/ LMV834 Quad
Input Bias Current vs. VCM at 85°C
30024116
Supply Current vs. Supply Voltage Single LMV831
Input Bias Current vs. VCM at 125°C
30024117
Supply Current vs. Supply Voltage Dual LMV832
30024118
Supply Current vs. Supply Voltage Quad LMV834
30024120
30024119
Supply Current vs. Temperature Single LMV831
30024121
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Supply Current vs. Temperature Dual LMV832
Supply Current vs. Temperature Quad LMV834
30024122
LMV831 Single/ LMV832 Dual/ LMV834 Quad
Sinking Current vs. Supply Voltage
30024124
Output Swing High vs. Supply Voltage RL = 2 kΩ
30024123
Sourcing Current vs. Supply Voltage
30024125
Output Swing High vs. Supply Voltage RL = 10 kΩ
30024126
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30024127
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LMV831 Single/ LMV832 Dual/ LMV834 Quad
Output Swing Low vs. Supply Voltage RL = 2 kΩ
30024128
Output Voltage Swing vs. Load Current at V+ = 3.3V
Output Swing Low vs. Supply Voltage RL = 10 kΩ
30024129
Output Voltage Swing vs. Load Current at V+ = 5.0V
30024130
Open Loop Frequency Response vs. Temperature
30024132
30024131
Open Loop Frequency Response vs. Load Conditions
30024133
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Phase Margin vs. Capacitive Load
PSRR vs. Frequency
30024134
LMV831 Single/ LMV832 Dual/ LMV834 Quad
CMRR vs. Frequency
30024136
Large Signal Step Response with Gain = 1
30024135
Channel Separation vs. Frequency
30024137
Large Signal Step Response with Gain = 10
30024138
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30024139
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LMV831 Single/ LMV832 Dual/ LMV834 Quad
Small Signal Step Response with Gain = 1
30024140
Slew Rate vs. Supply Voltage
Small Signal Step Response with Gain = 10
30024141
Input Voltage Noise vs. Frequency
THD+N vs. Frequency
30024142
30024145
30024144
THD+N vs. Amplitude
30024146
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R
vs. Frequency
OUT
EMIRR IN+ vs. Power at 400 MHz
30024147
LMV831 Single/ LMV832 Dual/ LMV834 Quad
EMIRR IN+ vs. Power at 900 MHz
30024149
EMIRR IN+ vs. Power at 2400 MHz
30024148
EMIRR IN+ vs. Power at 1800 MHz
30024150
EMIRR IN+ vs. Frequency
30024151
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30024152
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Application Information
INTRODUCTION
The LMV831, LMV832 and LMV834 are operational amplifiers with excellent specifications, such as low offset, low
noise and a rail-to-rail output. These specifications make the
LMV831, LMV832 and LMV834 great choices for medical and
instrumentation applications such as diagnosis equipment.
The low supply current is perfectly suited for battery powered
equipment. The small packages, SC-70 package for the
LMV831, the MSOP package for the dual LMV832 and the
TSSOP package for the quad LMV834, make these parts a
perfect choice for portable electronics. Additionally, the EMI
hardening makes the LMV831, LMV832 or LMV834 a must
for almost all op amp applications. Most applications are exposed to Radio Frequency (RF) signals such as the signals
transmitted by mobile phones or wireless computer peripherals. The LMV831, LMV832 and LMV834 will effectively reduce disturbances caused by RF signals to a level that will be
hardly noticeable. This again reduces the need for additional
filtering and shielding. Using this EMI resistant series of op
amps will thus reduce the number of components and space
needed for applications that are affected by EMI, and will help
applications, not yet identified as possible EMI sensitive, to
be more robust for EMI.
INPUT CHARACTERISTICS
The input common mode voltage range of the LMV831,
LMV832 and LMV834 includes ground, and can even sense
well below ground. The CMRR level does not degrade for input levels up to 1.2V below the supply voltage. For a supply
voltage of 5V, the maximum voltage that should be applied to
the input for best CMRR performance is thus 3.8V.
When not configured as unity gain, this input limitation will
usually not degrade the effective signal range. The output is
rail-to-rail and therefore will introduce no limitations to the
signal range.
The typical offset is only 0.25 mV, and the TCVOS is
0.5 μV/°C, specifications close to precision op amps.
CMRR MEASUREMENT
The CMRR measurement results may need some clarification. This is because different setups are used to measure the
AC CMRR and the DC CMRR.
The DC CMRR is derived from ΔVOS versus ΔVCM. This value
is stated in the tables, and is tested during production testing.
The AC CMRR is measured with the test circuit shown in
Figure 1.
LMV831 Single/ LMV832 Dual/ LMV834 Quad
30024164
FIGURE 1. AC CMRR Measurement Setup
The configuration is largely the usually applied balanced configuration. With potentiometer P1, the balance can be tuned
to compensate for the DC offset in the DUT. The main difference is the addition of the buffer. This buffer prevents the
open-loop output impedance of the DUT from affecting the
balance of the feedback network. Now the closed-loop output
impedance of the buffer is a part of the balance. As the closedloop output impedance is much lower, and by careful selection of the buffer also has a larger bandwidth, the total effect
is that the CMRR of the DUT can be measured much more
accurately. The differences are apparent in the larger measured bandwidth of the AC CMRR.
One artifact from this test circuit is that the low frequency
CMRR results appear higher than expected. This is because
in the AC CMRR test circuit the potentiometer is used to compensate for the DC mismatches. So, mainly AC mismatch is
all that remains. Therefore, the obtained DC CMRR from this
AC CMRR test circuit tends to be higher than the actual DC
CMRR based on DC measurements.
The CMRR curve in Figure 2 shows a combination of the AC
CMRR and the DC CMRR.
30024136
FIGURE 2. CMRR Curve
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Page 14
OUTPUT CHARACTERISTICS
As already mentioned the output is rail-to-rail. When loading
the output with a 10 kΩ resistor the maximum swing of the
output is typically 6 mV from the positive and negative rail.
The output of the LMV831/LMV832/LMV834 can drive currents up to 30 mA at 3.3V and even up to 65 mA at 5V
The LMV831/LMV832/LMV834 can be connected as non-inverting unity-gain amplifiers. This configuration is the most
sensitive to capacitive loading. The combination of a capacitive load placed at the output of an amplifier along with the
amplifier’s output impedance creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin
is significantly reduced, the response will be under damped
which causes peaking in the transfer and, when there is too
much peaking, the op amp might start oscillating. The
LMV831/LMV832/LMV834 can directly drive capacitive loads
up to 200 pF without any stability issues. In order to drive
heavier capacitive loads, an isolation resistor, R
used, as shown in Figure 3. By using this isolation resistor,
, should be
ISO
the capacitive load is isolated from the amplifier’s output, and
hence, the pole caused by CL is no longer in the feedback
LMV831 Single/ LMV832 Dual/ LMV834 Quad
loop. The larger the value of R
fier will be. If the value of R
back loop will be stable, independent of the value of CL.
However, larger values of R
and reduced output current drive.
, the more stable the ampli-
ISO
is sufficiently large, the feed-
ISO
result in reduced output swing
ISO
30024163
FIGURE 3. Isolating Capacitive Load
nificantly simplifies the unambiguous measurement and
specification of the EMI performance of an op amp.
RF signals interfere with op amps via the non-linearity of the
op amp circuitry. This non-linearity results in the detection of
the so called out-of-band signals. The obtained effect is that
the amplitude modulation of the out-of-band signal is downconverted into the base band. This base band can easily
overlap with the band of the op amp circuit. As an example
Figure 4 depicts a typical output signal of a unity-gain connected op amp in the presence of an interfering RF signal.
Clearly the output voltage varies in the rhythm of the on-off
keying of the RF carrier.
30024165
FIGURE 4. Offset voltage variation due to an interfering
RF signal
EMIRR DEFINITION
To identify EMI hardened op amps, a parameter is needed
that quantitatively describes the EMI performance of op
amps. A quantitative measure enables the comparison and
the ranking of op amps on their EMI robustness. Therefore
the EMI Rejection Ratio (EMIRR) is introduced. This parameter describes the resulting input-referred offset voltage shift
of an op amp as a result of an applied RF carrier (interference)
with a certain frequency and level. The definition of EMIRR is
given by:
A resistor value of around 150Ω would be sufficient. As an
example some values are given in the following table, for 5V.
C
LOAD
300 pF
400 pF
500 pF
R
ISO
165Ω
175Ω
185Ω
EMIRR
With the increase of RF transmitting devices in the world, the
electromagnetic interference (EMI) between those devices
and other equipment becomes a bigger challenge. The
LMV831, LMV832 and LMV834 are EMI hardened op amps
which are specifically designed to overcome electromagnetic
interference. Along with EMI hardened op amps, the EMIRR
parameter is introduced to unambiguously specify the EMI
performance of an op amp. This section presents an overview
of EMIRR. A detailed description on this specification for EMI
hardened op amps can be found in Application Note AN-1698.
The dimensions of an op amp IC are relatively small compared to the wavelength of the disturbing RF signals. As a
result the op amp itself will hardly receive any disturbances.
The RF signals interfering with the op amp are dominantly
received by the PCB and wiring connected to the op amp. As
a result the RF signals on the pins of the op amp can be represented by voltages and currents. This representation sig-
In which V
lated RF signal (V) and ΔVOS is the resulting input-referred
is the amplitude of the applied un-modu-
RF_PEAK
offset voltage shift (V). The offset voltage depends quadratically on the applied RF level, and therefore, the RF level at
which the EMIRR is determined should be specified. The
standard level for the RF signal is 100 mVP. Application Note
AN-1698 addresses the conversion of an EMIRR measured
for an other signal level than 100 mVP. The interpretation of
the EMIRR parameter is straightforward. When two op amps
have an EMIRR which differ by 20 dB, the resulting error signals when used in identical configurations, differ by 20 dB as
well. So, the higher the EMIRR, the more robust the op amp.
Coupling an RF Signal to the IN+ Pin
Each of the op amp pins can be tested separately on EMIRR.
In this section the measurements on the IN+ pin (which,
based on symmetry considerations, also apply to the IN- pin)
are discussed. In Application Note AN-1698 the other pins of
the op amp are treated as well. For testing the IN+ pin the op
amp is connected in the unity gain configuration. Applying the
RF signal is straightforward as it can be connected directly to
the IN+ pin. As a result the RF signal path has a minimum of
components that might affect the RF signal level at the pin.
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LMV831 Single/ LMV832 Dual/ LMV834 Quad
The circuit diagram is shown in Figure 5. The PCB trace from
RFIN to the IN+ pin should be a 50Ω stripline in order to match
the RF impedance of the cabling and the RF generator. On
the PCB a 50Ω termination is used. This 50Ω resistor is also
used to set the bias level of the IN+ pin to ground level. For
determining the EMIRR, two measurements are needed: one
is measuring the DC output level when the RF signal is off;
and the other is measuring the DC output level when the RF
signal is switched on. The difference of the two DC levels is
the output voltage shift as a result of the RF signal. As the op
amp is in the unity gain configuration, the input referred offset
voltage shift corresponds one-to-one to the measured output
voltage shift.
nected at the negative output of the pressure sensor prevents
the loading of the bridge by resistor R2. The buffer also prevents the resistors of the sensor from affecting the gain of the
following gain stage. The op amps are placed in a single supply configuration.
The experiment is performed on two different dual op amps:
a typical standard op amp and the LMV832, EMI hardened
dual op amp. A cell phone is placed on a fixed position a couple of centimeters from the op amps in the sensor circuit.
When the cell phone is called, the PCB and wiring connected
to the op amps receive the RF signal. Subsequently, the op
amps detect the RF voltages and currents that end up at their
pins. The resulting effect on the output of the second op amp
is shown in Figure 6.
30024167
FIGURE 5. Circuit for coupling the RF signal to IN+
Cell Phone Call
The effect of electromagnetic interference is demonstrated in
a setup where a cell phone interferes with a pressure sensor
application. The application is shown in Figure 7.
This application needs two op amps and therefore a dual op
amp is used. The op amp configured as a buffer and con-
FIGURE 7. Pressure Sensor Application
DECOUPLING AND LAYOUT
Care must be given when creating a board layout for the op
amp. For decoupling the supply lines it is suggested that 10
nF capacitors be placed as close as possible to the op amp.
For single supply, place a capacitor between V+ and V−. For
dual supplies, place one capacitor between V+ and the board
ground, and a second capacitor between ground and V−.
30024168
FIGURE 6. Comparing EMI Robustness
The difference between the two types of dual op amps is
clearly visible. The typical standard dual op amp has an output
shift (disturbed signal) larger than 1V as a result of the RF
signal transmitted by the cell phone. The LMV832, EMI hardened op amp does not show any significant disturbances.
This means that the RF signal will not disturb the signal entering the ADC when using the LMV832.
30024169
Even with the LMV831/LMV832/LMV834 inherent hardening
against EMI, it is still recommended to keep the input traces
short and as far as possible from RF sources. Then the RF
signals entering the chip are as low as possible, and the remaining EMI can be, almost, completely eliminated in the chip
by the EMI reducing features of the LMV831/LMV832/
LMV834.
15 www.national.com
Page 16
PRESSURE SENSOR APPLICATION
The LMV831/LMV832/LMV834 can be used for pressure sensor applications. Because of their low power the LMV831/
LMV832/LMV834 are ideal for portable applications, such as
blood pressure measurement devices, or portable barometers. This example describes a universal pressure sensor that
can be used as a starting point for different types of sensors
and applications.
Pressure Sensor Characteristics
The pressure sensor used in this example functions as a
Wheatstone bridge. The value of the resistors in the bridge
change when pressure is applied to the sensor. This change
of the resistor values will result in a differential output voltage,
depending on the sensitivity of the sensor and the applied
pressure. The difference between the output at full scale
pressure and the output at zero pressure is defined as the
span of the pressure sensor. A typical value for the span is
100 mV. A typical value for the resistors in the bridge is
5 kΩ. Loading of the resistor bridge could result in incorrect
output voltages of the sensor. Therefore the selection of the
LMV831 Single/ LMV832 Dual/ LMV834 Quad
circuit configuration, which connects to the sensor, should
take into account a minimum loading of the sensor.
Pressure Sensor Example
The configuration shown in Figure 7 is simple, and is very
useful for the read out of pressure sensors. With two op amps
in this application, the dual LMV832 fits very well. The op amp
configured as a buffer and connected at the negative output
of the pressure sensor prevents the loading of the bridge by
resistor R2. The buffer also prevents the resistors of the sensor from affecting the gain of the following gain stage. Given
the differential output voltage VS of the pressure sensor, the
output signal of this op amp configuration, V
OUT
, equals:
To align the pressure range with the full range of an ADC, the
power supply voltage and the span of the pressure sensor are
needed. For this example a power supply of 5V is used and
the span of the sensor is 100 mV. When a 100Ω resistor is
used for R2, and a 2.4 kΩ resistor is used for R1, the maximum voltage at the output is 4.95V and the minimum voltage
is 0.05V. This signal is covering almost the full input range of
the ADC. Further processing can take place in the microprocessor following the ADC.
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Page 17
Physical Dimensions inches (millimeters) unless otherwise noted
LMV831 Single/ LMV832 Dual/ LMV834 Quad
NS Package Number MAA05A
5-Pin SC-70
NS Package Number MUA08A
8-Pin MSOP
17 www.national.com
Page 18
LMV831 Single/ LMV832 Dual/ LMV834 Quad
NS Package Number MTC14
14-Pin TSSOP
www.national.com 18
Page 19
Notes
LMV831 Single/ LMV832 Dual/ LMV834 Quad
19 www.national.com
Page 20
Notes
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LMV831 Single/ LMV832 Dual/ LMV834 Quad 3.3 MHz Low Power CMOS, EMI Hardened
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