Datasheet LMU217JC35, LMU217JC25 Datasheet (LOGIC)

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DEVICES INCORPORATED

LMU217

16 x 16-bit Parallel Multiplier

LMU217

DEVICES INCORPORATED

FEATURES DESCRIPTION

❑❑

❑ 25 ns Worst-Case Multiply Time

❑❑ ❑❑

❑ Low Power CMOS Technology

❑❑ ❑❑

❑ Replaces Cypress CY7C517,

❑❑

IDT 7217L, and AMD Am29517

❑❑

❑ Single Clock Architecture with

❑❑

❑ Two’s Complement, Unsigned, or

❑❑

Mixed Operands

❑❑

❑ Three-State Outputs

❑❑ ❑❑

❑ 68-pin PLCC, J-Lead

❑❑

The LMU217 is a high-speed, low power 16-bit parallel multiplier.

The LMU217 produces the 32-bit product of two 16-bit numbers. Data present at the A inputs, along with the TCA control bit, is loaded into the A register on the rising edge of CLK. B data and the TCB control bit are similarly loaded. Loading of the A and B registers is controlled by the ENA and ENB controls. When HIGH, these controls prevent application of the clock to the respective register. The TCA and TCB controls specify the operands as two’s complement when HIGH, or unsigned magnitude when LOW.

LMU217 BLOCK DIAGRAM

15-0

CLK ENA ENB

TCA TCB

A REGISTER B REGISTER

16 x 16-bit Parallel multiplier

RND is loaded on the rising edge of CLK, provided either ENA or ENB are LOW. RND, when HIGH, adds ‘1’ to the most significant bit position of the least significant half of the product. Subsequent truncation of the 16 least significant bits produces a result correctly rounded to 16-bit precision.

At the output, the Right Shift control (RS) selects either of two output formats. RS LOW produces a 31-bit product with a copy of the sign bit inserted in the MSB postion of the least significant half. RS HIGH gives a full 32-bit product. Tw o 16-bit output registers are provided to hold the most and least significant halves of the result (MSP and LSP) as defined by RS. These registers are loaded on the rising edge of CLK, subject

15-0

to the ENR control. When ENR is HIGH, clocking of the result registers is prevented.

For asynchronous output, these registers may be made transparent by setting the feed through control (FT) HIGH and ENR LOW.

RND

ENR

MSPSEL

FORMAT ADJUST

16 16

REGISTERRESULT

OEM OEL

31-16

The two halves of the product may be routed to a single 16-bit three-state output port (MSP) via a multiplexer. MSPSEL LOW causes the MSP outputs to be driven by the most significant half of the result. MSPSEL HIGH routes the least significant half of the result to the MSP pins. In addition, the LSP is available via the B port through a separate three-state buffer.

Multipliers

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DEVICES INCORPORATED

FIGURE 1A.INPUT FORMATS

LMU217

16 x 16-bit Parallel Multiplier

AIN BIN

Fractional Two’s Complement (TCA, TCB = 1)

15 14 13 2 1 0

–2

2–12

–2

(Sign)

15 14 13 2 1 0

–2

(Sign)

2142

15 14 13 2 1 0

–12–22–3

15 14 13 2 1 0

15214213

FIGURE 1B.OUTPUT FORMATS

–132–142–15

–2

(Sign)

2–12

Integer Two’s Complement (TCA, TCB = 1)

15 14 13 2 1 0

22212

–2

(Sign)

2142

Unsigned Fractional (TCA, TCB = 0)

15 14 13 2 1 0

–142–152–16

–12–22–3

Unsigned Integer (TCA, TCB = 0)

15 14 13 2 1 0

22212

15214213

–2

–132–142–15

22212

–142–152–16

22212

MSP LSP

Fractional Two’s Complement (RS = 0)

31 30 29 18 17 16

–2

(Sign)

2–12

–2

–132–142–15

Fractional Two’s Complement (RS = 1)

31 30 29 18 17 16

–2

(Sign)

202

–1

–122–132–14

Integer Two’s Complement (RS = 1)

31 30 29 18 17 16

–2

(Sign)

2302

2182172

31 30 29 18 17 16

–12–22–3

–142–152–16

31 30 29 18 17 16 2312302

2182172

15 14 13 2 1 0

–2

(Sign)

15 14 13 2 1 0

2152142

Unsigned Fractional (RS = 1)

15 14 13 2 1 0

Unsigned Integer (RS = 1)

15 14 13 2 1 0

2152142

–162–17

–152–162–17

–172–182–19

–282–292–30

22212

–302–312–32

22212

Multipliers

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DEVICES INCORPORATED

LMU217

16 x 16-bit Parallel Multiplier

MAXIMUM RATINGS

Storage temperature ........................................................................................................... –65°C to +150°C

Operating ambient temperature........................................................................................... –55°C to +125°C

VCC supply voltage with respect to ground............................................................................ –0.5 V to +7.0V

Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V

Output current into low outputs............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

OPERATING CONDITIONS

Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V

ELECTRICAL CHARACTERISTICS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

To meet specified electrical and switching characteristics

Mode Temperature Range (Ambient) Supply Voltage

Over Operating Conditions (Note 4)

Symbol Parameter Test Condition Min Typ Max Unit

VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.5 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±20 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 12 25 mA ICC2 VCC Current, Quiescent (Note 7) 1.0 mA

Multipliers

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DEVICES INCORPORATED

SWITCHING CHARACTERISTICS

LMU217

16 x 16-bit Parallel Multiplier

COMMERCIAL OPERATING RANGE (0°C to +70°C)

Symbol Parameter Min Max Min Max Min Max Min Max Min Max Min Max

tMC Clocked Multiply Time 65 55 45 35 25 20 tMUC Unclocked Multiply Time 85 75 65 55 38 30

tPW Clock Pulse Width 15 15 15 10 10 9 tS Input Setup Time 15 15 15 12 12 11 tH Input Hold Time 3 3 3 1 1 1 tD Output Delay 30 30 30 25 20 18 tSEL Output Select Delay 25 25 25 25 20 18 tENA Three-State Output Enable Delay (Note 11) 25 25 25 25 20 18 tDIS Three-State Output Disable Delay (Note 11) 25 25 25 25 20 18

MILITARY OPERATING RANGE (–55°C to +125°C)

Symbol Parameter Min Max Min Max Min Max Min Max Min Max Min Max

tMC Clocked Multiply Time 75 65 55 40 30 25 tMUC Unclocked Multiply Time 95 85 75 60 43 38

tPW Clock Pulse Width 20 1 5 15 15 10 10 tS Input Setup Time 15 15 15 15 12 12 tH Input Hold Time 3 3 3 2 2 2 tD Output Delay 35 30 30 25 20 20 tSEL Output Select Delay 30 30 30 25 20 20 tENA Three-State Output Enable Delay (Note 11) 25 25 25 25 20 20

DIS Three-State Output Disable Delay (Note 11) 25 25 25 25 20 20

Notes 9, 10 (ns)

234567890123456789012345678

LMU217– *

35 25 20

234567890

Notes 9, 10 (ns)

2345678901234567890123456789012123456789012345678901234

LMU217– *

SWITCHING WAVEFORMS

INPUT

ENA, ENB

2345678901234567890123

*DISCONTINUED SPEED GRADE

ENR

CLK

MSPSEL

OEM

OEL

31-0

DIS

HIGH IMPEDANCE

MUC

ENA

SEL

Multipliers

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DEVICES INCORPORATED

DUT

0.2 V

DIS

ENA

0.2 V

1.5 V 1.5 V

3.5V Vth

1.5 V

0V Vth

VOL*

Measured V

with IOH = –10mA and IOL = 10mA

Measured V

with IOH = –10mA and IOL = 10mA

NOTES

LMU217

16 x 16-bit Parallel Multiplier

1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability.

2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values.

3. This device provides hard clamping of transient undershoot and overshoot. Input levels below ground or above VCC will be clamped beginning at –0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in excess of 100 mA.

9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except

tDIS test), and input levels of nominally

0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed.

This device has high-speed outputs capable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended:

a. A 0.1 µF ceramic capacitor should be installed between VCC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common.

11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.

12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current.

FIGURE A. OUTPUT LOADING CIRCUIT

FIGURE B. THRESHOLD LEVELS

4. Actual test conditions may vary from those designated but operation is guaranteed as specified.

5. Supply current for a given application can be accurately approximated by:

NCV F

where

N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency

6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock rate.

7. Tested with all inputs within 0.1 V of

VCC or Ground, no load.

8. These parameters are guaranteed but not 100% tested.

b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers.

c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin.

10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time.

Multipliers

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DEVICES INCORPORATED

LMU217

16 x 16-bit Parallel Multiplier

Speed

35 ns 25 ns

ORDERING INFORMATION

68-pin

ENR

OEMRSFT

MSPSEL

GND

VCCVCCTCB

TCA

RND

ENA

A15A14A

46663 6212

, B

5867

, B

27 32 33 34 35 36 37 386139 40941 42 43

28 29 30 31

, B

Plastic J-Lead

Chip Carrier (J2)

0°C to +70°C — COMMERCIAL SCREENING

LMU217JC35 LMU217JC25

–55°C to +125°C — COMMERCIAL SCREENING

–55°C to +125°C — MIL-STD-883 COMPLIANT

Top

View

, B

6768 6465

, B

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

NC A

OEL CLK ENB

23456789012345678901234567890121234567890123456

64-pin

23456789012345678901234567890121234567890123456

ENR

OEMRSFT

MSPSEL

GND

VCCVCCTCB

TCA

646362616059585756555453525150

1 2 3 4 5 6 7 8

Top

9 10

View

11 12 13 14 15 16

171819202122232425262728293031

, B

Discontinued Package

RND

, B

ENA

, B

A15A14A

, B

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

Ceramic Flatpack

(F4)

Multipliers

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OEL CLK ENB