Page 1
DEVICES INCORPORATED
LMU16/216
16 x 16-bit Parallel Multiplier
LMU16/216
DEVICES INCORPORATED
FEATURES DESCRIPTION
❑❑
❑ 20 ns Worst-Case Multiply Time
❑❑
❑❑
❑ Low Power CMOS Technology
❑❑
❑❑
❑ Replaces Fairchild MPY016/TMC216,
❑❑
Cypress CY7C516, IDT 7216L, and
AMD Am29516
❑❑
❑ Two’s Complement, Unsigned, or
❑❑
Mixed Operands
❑❑
❑ Three-State Outputs
❑❑
❑❑
❑ 68-pin PLCC, J-Lead
❑❑
The LMU16 and LMU216 are high-
speed, low power 16-bit parallel
multipliers. The LMU16 and
LMU216 are functionally identical;
they differ only in packaging.
The LMU16 and LMU216 produce
the 32-bit product of two 16-bit
numbers. Data present at the A
inputs, along with the TCA control
bit, is loaded into the A register on
the rising edge of CLK A. B data
and the TCB control bit are
similarly loaded by CLK B. The
TCA and TCB controls specify the
A and B operands as two’s
complement when HIGH, or
unsigned magnitude when LOW.
LMU16/216 BLOCK DIAGRAM
A
15-0
16
32
FORMAT ADJUST
16 16
REGISTERRESULT
CLK A
CLK B
RND
RS
FT
CLK M
MSPSEL
TCA TCB
A REGISTER B REGISTER
REGISTER
16 x 16-bit Parallel Multiplier
RND is loaded on the rising edge of
the logical OR of CLK A and CLK B.
RND, when HIGH, adds ‘1’ to the
most significant bit position of the
least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit precision.
At the output, the Right Shift control
(RS) selects either of two output
formats. RS LOW produces a 31-bit
product with a copy of the sign bit
inserted in the MSB postion of the
least significant half. RS HIGH gives a
full 32-bit product. Two 16-bit output
registers are provided to hold the
most and least significant halves of the
result (MSP and LSP) as defined by
RS. These registers are loaded on the
rising edge of CLK M and CLK L
respectively. For asynchronous
B
15-0
/
R
15-0
16
CLK L
output, these registers may be made
transparent by setting the feed
through control (FT) HIGH.
The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
MSPSEL LOW causes the MSP
outputs to be driven by the most
significant half of the result. MSPSEL
HIGH routes the least significant half
of the result to the MSP outputs. In
addition, the LSP is available via the B
port through a separate three-state
buffer.
The output multiplexer control
MSPSEL uses a pin which is a supply
ground in the Fairchild MPY016H/
TMC216H. When this control is LOW
(GND), the function is that of the
MPY016H/TMC216H, thus allowing
full compatibility.
OEM OEL
16
R
31-16
16
1
Multipliers
08/16/2000–LDS.16/216-N
Page 2
DEVICES INCORPORATED
FIGURE 1A.INPUT FORMATS
LMU16/216
16 x 16-bit Parallel Multiplier
AIN BIN
Fractional Two’s Complement (TCA, TCB = 1)
15 14 13 2 1 0
0
–2
2–12
–2
(Sign)
15 14 13 2 1 0
–2
(Sign)
15
2142
13
15 14 13 2 1 0
–12–22–3
2
15 14 13 2 1 0
15214213
2
FIGURE 1B.OUTPUT FORMATS
–132–142–15
2
–2
(Sign)
0
2–12
Integer Two’s Complement (TCA, TCB = 1)
15 14 13 2 1 0
15 14 13 2 1 0
22212
0
–2
(Sign)
15
2142
Unsigned Fractional (TCA, TCB = 0)
15 14 13 2 1 0
–142–152–16
2
–12–22–3
2
Unsigned Integer (TCA, TCB = 0)
15 14 13 2 1 0
22212
0
15214213
2
–2
13
–132–142–15
2
22212
–142–152–16
2
22212
0
0
MSP LSP
Fractional Two’s Complement (RS = 0)
31 30 29 18 17 16
0
–2
(Sign)
2–12
–2
–132–142–15
2
Fractional Two’s Complement (RS = 1)
31 30 29 18 17 16
1
–2
(Sign)
202
–1
–122–132–14
2
Integer Two’s Complement (RS = 1)
31 30 29 18 17 16
–2
(Sign)
31
2302
29
2182172
31 30 29 18 17 16
–12–22–3
2
–142–152–16
2
31 30 29 18 17 16
2312302
29
2182172
15 14 13 2 1 0
–2
(Sign)
15 14 13 2 1 0
2
15 14 13 2 1 0
16
2152142
Unsigned Fractional (RS = 1)
15 14 13 2 1 0
2
Unsigned Integer (RS = 1)
15 14 13 2 1 0
16
2152142
0
–162–17
2
–152–162–17
–172–182–19
–282–292–30
2
–282–292–30
2
13
13
22212
–302–312–32
2
22212
0
0
Multipliers
2
08/16/2000–LDS.16/216-N
Page 3
DEVICES INCORPORATED
LMU16/216
16 x 16-bit Parallel Multiplier
MAXIMUM RATINGS
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground............................................................................ –0.5 V to +7.0V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS
Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V
Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
To meet specified electrical and switching characteristics
Mode Temperature Range (Ambient) Supply Voltage
Over Operating Conditions (Note 4)
Symbol Parameter Test Condition Min Typ Max Unit
VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V
VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.5 V
VIH Input High Voltage 2.0 VCC V
V IL Input Low Voltage (Note 3) 0.0 0.8 V
IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±20 µA
IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA
ICC1 VCC Current, Dynamic (Notes 5, 6) 12 25 mA
ICC2 VCC Current, Quiescent (Note 7) 1.0 mA
Multipliers
3
08/16/2000–LDS.16/216-N
Page 4
DEVICES INCORPORATED
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6
6
6
6
6
6
6
6
6
6
6
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5
5
5
5
5
5
5
5
5
5
5
5
5
4
SWITCHING CHARACTERISTICS
LMU16/216
16 x 16-bit Parallel Multiplier
COMMERCIAL OPERATING RANGE (0°C to +70°C)
Symbol Parameter Min Max Min Max Min Max Min Max Min Max Min Max
tMC Clocked Multiply Time 65 55 45 35 25 20
tMUC Unclocked Multiply Time 85 75 65 55 38 30
tPW Clock Pulse Width 15 15 15 10 10 9
tS Input Setup Time 15 15 15 12 12 11
tH Input Hold Time 1 1 1 1 1 1
tD Output Delay 30 30 30 25 20 18
tSEL Output Select Delay 25 25 25 25 20 18
tENA Three-State Output Enable Delay (Note 11) 25 25 25 25 20 18
DIS Three-State Output Disable Delay (Note 11) 25 25 25 22 20 18
t
MILITARY OPERATING RANGE (–55°C to +125°C)
Symbol Parameter Min Max Min Max Min Max Min Max Min Max Min Max
tMC Clocked Multiply Time 75 65 55 40 30 25
tMUC Unclocked Multiply Time 95 85 75 60 43 38
tPW Clock Pulse Width 20 15 15 15 10 10
tS Input Setup Time 15 15 15 15 12 12
tH Input Hold Time 2 2 2 2 2 2
tD Output Delay 35 30 30 25 20 20
tSEL Output Select Delay 30 30 30 25 20 20
tENA Three-State Output Enable Delay (Note 11) 25 25 25 25 20 20
DIS Three-State Output Disable Delay (Note 11) 25 25 25 25 22 22
t
Notes 9, 10 (ns)
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65
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55
*
LMU16/216–
*
45
35
*
25 20
Notes 9, 10 (ns)
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75
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65
*
LMU16/216–
*
55
40
*
30
*
25
*
SWITCHING WAVEFORMS
INPUT
CLK A
CLK B
CLK L
CLK M
MSPSEL
OEL
OEM
31-0
R
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*DISCONTINUED SPEED GRADE
t
t
S
H
t
PW
t
t
DIS
HIGH IMPEDANCE
MC
t
PW
t
D
t
SEL
t
MUC
t
ENA
Multipliers
4
08/16/2000–LDS.16/216-N
Page 5
DEVICES INCORPORATED
S1
I
OH
I
OL
V
TH
C
L
DUT
OE
0.2 V
t
DIS
t
ENA
0.2 V
1.5 V 1.5 V
3.5V Vth
1
Z
0
Z
Z
1
Z
0
1.5 V
1.5 V
0V Vth
VOL*
V
OH
*
V
OL
*
V
OH
*
Measured V
OL
with IOH = –10mA and IOL = 10mA
Measured V
OH
with IOH = –10mA and IOL = 10mA
NOTES
LMU16/216
16 x 16-bit Parallel Multiplier
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot. Input levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mA.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
FIGURE B. THRESHOLD LEVELS
4. Actual test conditions may vary from
those designated but operation is guaranteed as specified.
5. Supply current for a given application can be accurately approximated by:
2
NCV F
where
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
5
Multipliers
08/16/2000–LDS.16/216-N
Page 6
DEVICES INCORPORATED
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LMU16/216
16 x 16-bit Parallel Multiplier
LMU16 — ORDERING INFORMATION
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64-pin
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R10, B10
R11, B11
R12, B12
R13, B13
R14, B14
R15, B15
1
A4
2
A3
3
A2
4
A1
5
A0
6
OEL
7
CLK L
8
CLK B
9
R
0, B0
10
R1, B1
11
R2, B2
12
R3, B3
13
R4, B4
14
R5, B5
15
R6, B6
16
R7, B7
17
R8, B8
18
R9, B9
19
20
21
22
23
24
25
R16
26
R17
27
R18
28
R19
29
R20
30
R21
31
R22
32
R23
Discontinued Package Discontinued Package
Sidebraze Hermetic DIP
Speed
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
(D6)
64
A5
63
A6
62
A7
61
A8
60
A9
59
A10
58
A11
57
A12
56
A13
55
A14
54
A15
53
CLK A
52
RND
51
TCA
50
TCB
49
V
CC
48
VCC
47
GND
46
GND
45
MSPSEL
44
FT
43
RS
42
OEM
41
CLK M
40
R
31
39
R30
38
R29
37
R28
36
R27
35
R26
34
R25
33
R24
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68-pin
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6
1234567 8 9 10 11
A
CLK B
OEL
A
1
A
3
A
5
A
7
NC
B
0
CLK L
A
A
2
A
4
A
6
A
8
R/B
1
R/B
0
C
R/B
3
R/B
2
D
R/B
5
R/B
R/B
R/B
4
7
R/B
6
9
R/B
8
Top View
Through Package
(i.e., Component Side Pinout)
E
F
G
R/B
11
R/B
10
H
R/B
13
R/B
12
J
R/B
15
R/B
14
K
R
NC
R
16
20
R
18
R
22
R
24
R
26
R
28
L
R
R
17
21
R
19
R
23
R
25
R
27
R
29
Ceramic Pin Grid Array
(G2)
08/16/2000–LDS.16/216-N
A
11
A
9
NC
A
12
A
10
A
A
14
13
CLK A
A
15
RND
TCA
CC
TCB
V
GND
CC
V
MSPSEL
GND
RS
FT
CLK M
R
R
OEM
30
NC
31
Multipliers
Page 7
DEVICES INCORPORATED
LMU216 — ORDERING INFORMATION
68-pin
NC
10
R
31
11
R30
12
R29
13
R28
14
R27
15
R26
16
R25
17
R24
18
R23
19
R22
20
R21
21
R20
22
R19
23
R18
24
R17
25
R16
26
NC
27 32 33 34 35 36 37 386139 40941 42 43
CLK M
OEMRSFT
28 29 30 31
5867
MSPSEL
GND
3
46663 6212
GND
VCCVCC
Top
View
TCB
TCA
6768 6465
RND
CLK A
A15A14
LMU16/216
16 x 16-bit Parallel Multiplier
A13
60
NC
59
12
A
58
A11
57
A10
56
A9
55
A8
54
A7
53
A6
52
A5
51
A4
50
A3
49
A2
48
A1
47
A0
46
OEL
45
CLK L
44
CLK B
Speed
25 ns
20 ns
R9, B9
R8, B8
R7, B7
R6, B6
R5, B5
R4, B4
R3, B3
R2, B2
R1, B1
R15, B15
R14, B14
R13, B13
R12, B12
R11, B11
R10, B10
R0, B0
Plastic J-Lead
Chip Carrier (J2)
0°C to +70°C — COMMERCIAL SCREENING
LMU216JC25
LMU216JC20
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
NC
Multipliers
7
08/16/2000–LDS.16/216-N
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