Page 1
LMF60 High Performance
6th-Order Switched Capacitor
Butterworth Lowpass Filter
LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter
May 1996
General Description
The LMF60 is a high performance, precision, 6th-order Butterworth lowpass active filter. It is fabricated using National’s LMCMOS process, an improved silicon-gate CMOS process specifically designed for analog products. Switchedcapacitor techniques eliminate external component requirements and allow a clock-tunable cutoff frequency. The ratio
of the clock frequency to the low-pass cutoff frequency is
internally set to 50:1 (LMF60-50) or 100:1 (LMF60-100). A
Schmitt trigger clock input stage allows two clocking options, either self-clocking (via an external resistor and capacitor) for stand-alone applications, or for tighter cutoff frequency control, a TTL or CMOS logic compatible clock can
be directly applied. The maximally flat passband frequency
response together with a DC gain of 1V/V allows cascading
LMF60 sections for higher-order filtering. In addition to the
filter, two independent CMOS op amps are included on the
die and are useful for any general signal conditioning applications. The LMF60 is pin- and functionally-compatible with
the MF6, but provides improved performance.
Block and Connection Diagrams
Features
Y
Cutoff frequency range of 0.1 Hz to 30 kHz
Y
Cutoff frequency accuracy ofg1.0%, maximum
Y
Low offset voltageg100 mV, maximum,g5V supply
Y
Low clock feedthrough of 10 mV
Y
Dynamic range of 88 dB, typical
Y
Two uncommitted op amps available
Y
No external components required
Y
14-pin DIP or 14-pin wide-body S.O. package
Y
Single/Dual Supply Operation:
a
4V toa14V (g2V tog7V)
Y
Cutoff frequency set by external or internal clock
Y
Pin-compatible with the MF6
p–p
, typical
Applications
Y
Communication systems
Y
Audio filtering
Y
Anti-alias filtering
Y
Data acquisition noise filtering
Y
Instrumentation
Y
High-order tracking filters
All Packages
Order Number LMF60CMJ-50,
See NS Package Number J14A
TL/H/9294– 1
Order Number LMF60CIWM-50
See NS Package Number M14B
Order Number LMF60CIN-50
See NS Package Number N14A
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation RRD-B30M56/Printed in U. S. A.
TL/H/9294
Top View
TL/H/9294– 2
(5962-9096 701MCA or
LMF60CMJ50/883),
LMF60CMJ-100, or
(5962-9096 702MCA
or LMF60CMJ100/883)
or LMF60CIWM-100
or LMF60CIN-100
Page 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Pin V
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4) 500 mW
Storage Temperature
ESD Susceptibility (Note 5) 2000V
CLK IN Pin 1700V
a
b
Vb) (Note 2) 15V
b
65§Ctoa150§C
a
a
0.2V
b
b
V
0.2V
Soldering Information:
N Package: 10 sec. 260§C
#
J Package: 10 sec. 300§C
#
SO Package: Vapor Phase (60 sec.) 215§C
#
Infrared (15 sec.) (Note 6) 220
Operating Ratings (Note 1)
s
Temperature Range T
LMF60CIN-50, LMF60CIN-100
LMF60CIJ-50, LMF60CIJ-100,
LMF60CIWM-50,
LMF60CIWM-100
b
40§CsT
LMF60CMJ-50, LMF60CMJ-100,
LMF60CMJ50/883,
LMF60CMJ100/883
Supply Voltage (V
a
b
Vb) 4Vto14V
b
55§CsT
Min
s
T
A
s
a
A
s
a
125§C
A
T
Max
85§C
C
§
Filter Electrical Characteristics
The following specifications apply for f
e
T
to T
MIN
; all other limits T
MAX
e
500 kHz (Note 7) unless otherwise specified. Boldface limits apply for T
CLK
e
e
T
A
25§C.
J
Symbol Parameter Conditions
a
V
f
CLK
I
S
H
o
f
CLK/fC
ea
b
eb
5V, V
5V
Clock Frequency Range 5 Hz (Min)
(Note 16) 1.5 MHz (Max)
Total Supply Current 7.0 / 12.0 mA (Max)
Clock Feedthrough V
DC Gain R
e
0V Filter 10 mVp-p
IN
Source
Opamp 5 mVp-p
s
2kX 0.10 / 0.10 dB (Max)
Clock to LMF60-50 49.00g0.8% /49.00g1.0% (Max)
Cutoff
Frequency LMF60-100 98.10
Ratio (Note 10)
Temperature Coefficient
of f
CLK/fC
A
V
V
I
MIN
OS
OUT
SC
Stopband Attenuation At 2cf
C
DC Offset LMF60-50
Voltage LMF60-100
Output Voltage
Swing (Note 2)
Output Short Circuit Source 90 mA
Current (Note 11) Sink 2.2 mA
Dynamic Range
(Note 12)
Additional
Magnitude
Response
Test Points
(Note 13)
LMF60-50
LMF60-100
e
f
12 kHz
IN
e
f
9 kHz
IN
e
f
6 kHz
IN
e
4.5 kHz
f
IN
e
A
Typical Limits Units
(Note 8) (Note 9) (Limits)
b
0.26 /b0.30 dB (Min)
g
0.8% /98.10g1.0% (Max)
4 ppm/
36 dB (Min)
g
100 mV (Max)
g
150 mV (Max)
a
3.9 /
b
4.2 /
a
3.7 V (Min)
b
4.0 V (Max)
88 dB
b
9.45g0.46 /b9.45g0.50 dB
b
0.87g0.16 /b0.87g0.20 dB
b
9.30g0.46 /b9.30g0.50 dB
b
0.87g0.16 /b0.87g0.20 dB
T
J
C
§
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Page 3
Filter Electrical Characteristics (Continued)
The following specifications apply for f
e
T
to T
MIN
; all other limits T
MAX
e
250 kHz (Note 7) unless otherwise specified. Boldface limits apply for T
CLK
e
e
T
A
25§C.
J
Symbol Parameter Conditions
a
V
f
CLK
I
S
H
o
f
CLK/fC
ea
b
2.5V, V
eb
2.5V
Clock Frequency Range 5 Hz (Min)
(Note 16) 750 kHz (Max)
Total Supply Current 5.0 / 6.5 mA (Max)
Clock Feedthrough V
(Peak to Peak) Opamp 3 mV
DC Gain (with f
s
R
Clock to
Cutoff
Source
2kX)
LMF60-50
Frequency
Ratio
(Note 10)
LMF60-100
e
0V Filter 6 mV
IN
e
250 kHz 0.10 / 0.10 dB (Max)
CLK
e
f
500 kHz
CLK
e
f
250 kHz 49.00g0.8% /49.00g1.0% (Max)
CLK
e
f
500 kHz 49.00g0.6%
CLK
e
f
250 kHz 98.10g0.8% /98.10g1.0% (Max)
CLK
e
500 kHz 98.10g0.6%
f
CLK
Temperature Coefficient
of f
CLK/fC
A
V
V
I
MIN
OS
OUT
SC
Stopband Attenuation At 2cf
C
DC Offset LMF60-50
Voltage LMF60-100
Output Voltage R
Swing (Note 2)
e
5kX
L
Output Short Circuit Source 42 mA
Current (Note 11) Sink 0.9 mA
Dynamic Range
(Note 12)
Additional
Magnitude
Response
Test Points
(Note 13)
LMF60-50
LMF60-100
f
f
f
f
IN
IN
IN
IN
e
6 kHz
e
4.5 kHz
e
3 kHz
e
2.25 kHz
e
T
A
Typical Limits Units
(Note 8) (Note 9) (Limits)
b
0.26 /b0.30 dB (Min)
b
0.08 dB
4 ppm/
36 dB (Min)
g
60 mV (Max)
g
90 mV (Max)
a
1.4 /
b
2.0 /
a
1.2 V (Min)
b
1.8 V (Max)
81 dB
b
9.45g0.46 /b9.45g0.50 dB
b
0.87g0.16 /b0.87g0.20 dB
b
9.30g0.46 /b9.30g0.50 dB
b
0.87g0.16 /b0.87g0.20 dB
J
C
§
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Page 4
Op Amp Electrical Characteristics
Boldface limits apply for T
Symbol Parameter Conditions
a
ea
V
V
OS
I
B
CMRR Common Mode Rejection Test Input Range
V
O
I
SC
b
eb
5V, V
Input Offset Voltage
Input Bias Current 10 pA
Ratio (Op Amp
Output Voltage Swing R
Output Short Circuit Source 90 mA
Current (Note 13) Sink 2.1 mA
5V
A
e
Ý
2 Only)
e
T
T
to T
J
MIN
; all other limits T
MAX
e
e
T
A
25§C.
J
Typical Limits Units
(Note 8) (Note 9) (Limits)
g
20 mV (Max)
b
2.2V toa1.8V
e
5kX 3.8 / 3.6 V (Min)
L
e
55 dB
b
4.2 /b4.0 V (Max)
SR Slew Rate 4 V/ms
A
VOL
DC Open Loop Gain 80 dB (Min)
GBW Gain Bandwidth Product 2.0 MHz
a
ea
V
V
OS
I
B
CMRR Common Mode Rejection Test Input Range
V
O
I
SC
b
2.5V, V
eb
2.5V
Input Offset Voltage
g
20 mV (Max)
Input Bias Current 10 pA
Ý
Ratio (Op Amp
2 Only)
Output Voltage Swing R
b
0.9V toa0.5V
e
5kX 1.3 / 1.1 V (Min)
L
e
55 dB
b
1.8 /b1.6 V (Max)
Output Short Circuit Source 42 mA
Current (Note 13) Sink 0.9 mA
SR Slew Rate 3 V/ms
A
VOL
DC Open Loop Gain 74 dB (Min)
GBW Gain Bandwidth Product 2.0 MHz
Logic Input-Output Characteristics
The following specifications apply for V
e
e
T
T
to T
J
MIN
; all other limits T
MAX
b
e
0V (Note 15), L.She0V unless otherwise specified. Boldface limits apply for T
e
e
T
A
25§C.
J
Symbol Parameter Conditions
TTL CLOCK INPUT, CLK R PIN (NOTE 14)
a
a
ea
ea
5V, V
2.5V, V
V
IH
V
IL
V
IH
V
IL
TTL Input Logical ‘‘1’’ V
Voltage Logical ‘‘0’’ 0.8 V (Max)
CLK R Input Logical ‘‘1’’ V
Voltage Logical ‘‘0’’ 0.6 / 0.4 V (Max)
Maximum Leakage
Current at CLK R
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Typical Limits Units
(Note 8) (Note 9) (Limits)
b
eb
5V 2.0 V (Min)
b
eb
2.5V 2.0 V (Min)
2.0 mA
A
Page 5
Logic Input-Output Characteristics (Continued)
The following specifications apply for V
e
e
T
T
to T
J
MIN
Symbol Parameter Conditions
; all other limits T
MAX
b
e
0V (Note 15), L.She0V unless otherwise specified. Boldface limits apply for T
e
e
T
A
25§C.
J
Typical Limits Units
(Note 8) (Note 9) (Limits)
SCHMITT TRIGGER
a
V
a
T
Positive Going Input V
Threshold Voltage 8.8 / 8.9 V (Max)
e
10V 6.1 / 6.0 V (Min)
a
e
V
5V 3.0 / 2.9 V (Min)
4.3 / 4.4 V (Max)
a
V
b
T
Negative Going Input V
Threshold Voltage 3.8 / 3.9 V (Max)
e
10V 1.4 / 1.3 V (Min)
a
e
V
5V 0.7 / 0.6 V (Min)
1.9 / 2.0 V (Max)
b
V
V
a
b
T
T
Hysteresis V
a
e
10V 2.3 / 2.1 V (Min)
7.4 / 7.6 V (Max)
a
e
V
5V 1.1 / 0.9 V (Min)
3.6 / 3.8 V (Max)
a
V
OH
V
OL
I
SOURCE
I
SINK
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. Specified Electrical Characteristics do not apply when operating the device outside its specified conditions.
Note 2: All voltages are measured with respect to AGND, unless otherwise specified.
Note 3: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with 5 mA to four.
Note 4: The Maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation is PD
typical junction-to-ambient thermal resistance of the LMF60CCN when board mounted is 67
LMF60CIWM, i
Note 5: Human body model: 100 pF discharged through a 1.5 kX resistor.
Note 6: See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in any current Linear Databook
for other methods of soldering surface mount devices.
Note 7: The specifications given are for a clock frequency (f
deviate from the specified error band over the temperature range but the filter still maintains its amplitude characteristics. See application hints.
Note 8: Typicals are at 25
Note 9: Guaranteed to National’s Average Outgoing Quality Level (AOQL).
Note 10: The cutoff frequency of the filter is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter.
Note 11: The short circuit source current is measured by forcing the output to its maximum positive swing and then shorting that output to the negative supply. The
short circuit sink current is measured by forcing the output being tested to its maximum negative voltage and then shorting that output to the positive supply. These
are worst case conditions.
Note 12: For
g
Note 13: The filter’s magnitude response is tested at the cutoff frequency, f
Note 14: The LMF60 is operated with symmetrical supplies and L.Sh is tied to GND.
Note 15: For simplicity all the logic levels (except for the TTL input logic levels) have been referenced to V
and
Note 16: The nominal ratio of the clock frequency to the low-pass cutoff frequency is internally set to 50-to-1 (LMF60-50) or 100-to-1 (LMF60-100).
g
2.5V supplies the dynamic range is referenced to 0.849 V
g
2.5V supplies.
Logical ‘‘1’’ Voltage V
eb
I
10 mA, Pin 11 V
O
Logical ‘‘0’’ Voltage V
eb
I
10 mA, Pin 11 V
O
Output Source CLK R to V
Current, Pin 11 V
Output Sink CLK R to V
Current, Pin 11 V
) at any pin exceeds the power supply rails (V
IN
e
b
(T
TA)/iJAor the number given in the absolute ratings, whichever is lower. For this device, T
J Max
e
78§C/W.
JA
) of 500 kHz ata5V and 250 kHz atg2.5V. Above this frequency, the cutoff frequency begins to
CLK
C and represent the most likely parametric norm.
§
5V supplies the dynamic range is referenced to 2.62 V
(1.2V peak), where the wideband noise over a 20 kHz bandwidth is typically 75 mV
rms
ea
10V 9.1 / 9.0 V (Min)
a
ea
5V 4.6 / 4.5 V (Min)
a
ea
10V 0.9 / 1.0 V (Max)
a
ea
5V 0.4 / 0.5 V (Max)
b
a
ea
10V 4.9 / 3.7 mA (Min)
a
ea
V
5V 1.6 / 1.2 mA (Min)
a
a
ea
10V 4.9 / 3.7 mA (Min)
a
ea
V
5V 1.6 / 1.2 mA (Min)
k
IN
(3.7V peak), where the wideband noise over a 20 kHz bandwidth is typically 100 mV. For
rms
,atf
C
IN
l
Vbor V
e
Va) the absolute value of current at that pin should be limited
IN
, iJA, and the ambient temperature TA. The maximum
J Max
C/W. For the LMF60CIJ this number decreases to 62§C/W. For the
§
2fC, and at these two additional frequencies.
b
e
0V. The logic levels will scale accordingly forg5V
J Max
e
125§C, and the
rms
.
A
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Page 6
Typical Performance Characteristics
Deviation
f
CLK/fC
vs Power Supply Voltage
Deviation
f
CLK/fC
vs Power Supply Voltage
DC Gain Deviation
vs Power Supply Voltage
f
Deviation
CLK/fC
vs Temperature
f
Deviation
CLK/fC
vs Temperature
DC Gain Deviation
vs Temperature
f
Deviation
CLK/fC
vs Clock Frequency
f
Deviation
CLK/fC
vs Clock Frequency
DC Gain Deviation
vs Clock Frequency
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TL/H/9294– 3
Page 7
Typical Performance Characteristics (Continued)
DC Gain Deviation
vs Power Supply Voltage
DC Offset Voltage Deviation
vs Power Supply Voltage
Positive Voltage Swing
vs Power Supply Voltage
DC Gain Deviation
vs Temperature
Power Supply Current
vs Power Supply Voltage
Negative Voltage Swing
vs Power Supply Voltage
DC Gain Deviation
vs Clock Frequency
Power Supply Current
vs Temperature
Positive Voltage Swing
vs Temperature
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TL/H/9294– 4
Page 8
Typical Performance Characteristics (Continued)
Negative Voltage Swing
vs Temperature
Crosstalk from Filter
to Op Amps
CLK R Trigger Threshold
vs Power Supply Voltage
Crosstalk from Either
Op Amp to Filter
Equivalent Input Noise
Voltage of Op Amps
Schmitt Trigger Threshold
vs Power Supply Voltage
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TL/H/9294– 5
Page 9
Crosstalk Test Circuits
From Filter to Op-Amps
From Either Op-Amp to Filter Output
Pin Description (Pin Numbers)
Pin Description
FILTER OUT (3) The output of the lowpass filter will typi-
FILTER IN (8) The input to the lowpass filter. To mini-
V
ADJ (7) This pin is used to adjust the DC offset
OS
AGND (5) The analog ground pin. This pin sets the
V
(4), VO1is the output and INV1 is the invert-
O1
INV1 (13) ing input of Op-Amp
V
(2), VO2is the output, INV2 is the inverting
O2
INV2 (14), input, and NINV2 is the non-inverting inNINV2 (1) put of Op-Amp
Va(6), Vb(10) The positive and negative supply pins.
cally swing to within 1V of each supply
rail.
mize gain errors the source impedance
that drives this input should be less than
2k (See Section 1.4). For single supply
operation the input signal must be biased to mid-supply or AC coupled.
of the filter output; if not used it must be
tied to the AGND potential. (See Section
1.3)
DC bias level for the filter section and
the noninverting input of Op-Amp
Ý
and must be tied to the system ground
for split supply operation or to mid-supply for single supply operation (See Section 1.2). When tied to mid-supply this
pin should be well bypassed.
Ý
1. The non-inverting input of this Op-Amp is internally
connected to the AGND pin.
Ý
2.
The total power supply range is 4V to
14V. Decoupling these pins with 0.1 mF
capacitors is highly recommended.
TL/H/9294– 6
Pin Description
CLK IN (9) A CMOS Schmitt-trigger input to be
used with an external CMOS logic level
clock. Also used for self-clocking
Schmitt-trigger oscillator (See Section
1.1).
CLK R (11) A TTL logic level clock input when in
split supply operation (
L. Sh tied to system ground. This pin becomes a low impedance output when
L.Sh is tied to V
b
. Also used in conjunction with the CLK IN pin for self clocking
Schmitt-trigger oscillator (See Section
1.1).
L.Sh (12) Level shift pin, selects the logic thresh-
old levels for the desired clock. When
b
1
tied to V
STATE
it enables an internal TRI-
buffer stage between the
É
Schmitt trigger and the internal clock
level shift stage thus enabling the CLK
IN Schmitt-trigger input and making the
CLK R pin a low impedance output.
When the voltage level at this input exceeds[25% (V
ternal TRI-STATE
a
b
É
lowing the CLK R pin to become the
clock input for the internal clock level
shift stage. The CLK R threshold level is
now 2V above the voltage applied to the
L.Sh pin. Driving the CLK R pin with TTL
logic levels can be accomplished
through the use of split supplies and by
tying the L.Sh pin to system ground.
TL/H/9294– 7
g
2V tog7V) and
b
]
Vb)aV
the in-
buffer is disabled al-
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Page 10
1.0 LMF60 Application Hints
The LMF60 is comprised of a non-inverting unity gain lowpass sixth-order Butterworth switched capacitor filter section and two undedicated CMOS Op-Amps. The switchedcapacitor topology makes the cutoff frequency (where the
gain drops 3.01 dB below the DC gain) a direct ratio (100:1
or 50:1) of the clock frequency supplied to the lowpass filter.
Internal integrator time constants set the filter’s cutoff frequency. The resistive element of these integrators is actually a capacitor which is ‘‘switched’’ at the clock frequency
(for a detailed discussion see Input Impedance section).
Varying the clock frequency changes the value of this resistive element and thus the time constant of the integrators.
The clock to cutoff frequency ratio (f
ratio of the input and feedback capacitors in the integrators.
The higher the clock to cutoff frequency ratio (or the sampling rate) the closer the approximation is to the theoretical
Butterworth response. The LMF60 is available in f
ratios of 50:1 (LMF60-50) or 100:1 (LMF60-100).
1.1 CLOCK INPUTS
The LMF60 has a Schmitt-trigger inverting buffer which can
be used to construct a simple R/C oscillator. The oscillator
CLK/fC
) is set by the
CLK/fC
frequency is dependent on the buffer’s threshold levels as
well as on the resistor/capacitor tolerance (See
Figure 1
Schmitt-trigger threshold voltage levels can vary significantly causing the R/C oscillator’s frequency to vary greatly
from part to part.
Where accuracy in f
used to drive the CLK R input of the LMF60. This input is
is required an external clock can be
C
TTL logic level compatible and also presents a very light
load to the external clock source (E2 mA) with split supplies and L.Sh tied to system ground. The logic level is programmed by the voltage applied to level shift (L.Sh) pin (See
the Pin Description for L.Sh pin).
1.2 POWER SUPPLY BIASING
The LMF60 can be biased from a single supply or dual split
supplies. The split supply mode shown in
Figures 2
and3is
the most flexible and easiest to implement. As discussed
earlier split supplies,
TTL or CMOS clock logic levels.
g
2V tog7V, will enable the use of
Figure 4
shows two
schemes for single supply biasing. In this mode only CMOS
clock logic levels can be used.
).
TL/H/9294– 8
FIGURE 1. Schmitt Trigger R/C Oscillator
e
f
CLK
RC In
Typically for V
e
f
CLK
1.37 RC
1
b
V
V
V
b
CC
b
V
Ð#
CC
e
V
CC
1
a
T
T
V
V
J
(
a
b
T
T
a
b
b
e
V
10V:
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Page 11
1.0 LMF60 Application Hints (Continued)
If the LMF60-50 or the LMF60-100 were set up for a cutoff
frequency of 10 kHz the input impedance would be:
e
R
IN
In this example with a source impedance of 10k the overall
gain, if the LMF60 had an ideal gain of 1 (0 dB) would be:
1MX
e
A
V
10 kXa1MX
Since the maximum overall gain error for the LMF60 is
b
dB,
0.3 dB with a R
case would be
S
a
0.21 dB tob0.39 dB.
1.5 CUTOFF FREQUENCY RANGE
The filter’s cutoff frequency (f
leakage currents through the internal switches discharging
the stored charge on the capacitors. At lower clock frequen-
10
1c10
s
e
10 kHz
1MX
e
0.99009 (b86.4 mdB)
2kXthe actual gain error for this
) has a lower limit caused by
C
a
0.1
cies these leakage currents can cause millivolts of error, for
example:
f
CLK
e
100 Hz, I
V
e
1 pF (100 Hz)
LEAKAGE
1pA
e
1 pA, Ce1pF
e
10 mV
The propagation delay in the logic and the settling time required to acquire a new voltage level on the capacitors increases as the LMF60 power supply voltage decreases.
This causes a shift in the f
noticeable when the clock frequency exceeds 500 kHz. The
amplitude characteristic will stay within tolerance until f
exceeds 750 kHz and will peak at about 0.4 dB at the cutoff
ratio which will become
CLK/fC
CLK
frequency with a 2 MHz clock. The response of the LMF60
is still a reasonable approximation of the ideal Butterworth
lowpass characteristic as can be seen in
Figure 7
.
FIGURE 7a. LMF60-100g5V Supplies
Amplitude Response
FIGURE 7c. LMF60-100g2.5V Supplies
Amplitude Response
TL/H/9294– 17
TL/H/9294– 19
FIGURE 7b. LMF60-50g5V Supplies
TL/H/9294– 18
Amplitude Response
TL/H/9294– 20
FIGURE 7d. LMF60-50g2.5V Supplies
Amplitude Response
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Page 12
1.0 LMF60 Application Hints (Continued)
FIGURE 2. Dual Supply Operation LMF60 Driven with
CMOS Logic Level Clock (V
b
s
V
a
V
IL
0.3 VSwhere V
t
V
IH
e
S
a
b
a
V
TL/H/9294– 9
0.3 VSand
b
Vb)
a) Resistor Biasing of AGND
FIGURE 3. Dual Supply Operation
TL/H/9294– 10
LMF60 Driven with TTL Logic Level Clock
TL/H/9294– 11
b) Using Op-Amp 2 to Buffer AGND
FIGURE 4. Single Supply Operation
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TL/H/9294– 12
Page 13
1.0 LMF60 Application Hints (Continued)
TL/H/9294– 13
FIGURE 5. VOSAdjust Schemes
1.3 OFFSET ADJUST
The V
ADJ pin is used in adjusting the output offset level
OS
of the filter section. If this pin is not used it must be tied to
the analog ground (AGND) level, either mid-supply for single
ended supply operation or ground for split supply operation.
This pin sets the zero reference for the output of the filter.
The implementation of this pin can be seen in
5(a)
DC offset is adjusted using a potentiometer; in
Op-Amp integrator circuit keeps the average DC output level at AGND. The circuit in
5(b)
is therefore appropriate only
for AC-coupled signals and signals biased at AGND.
1.4 INPUT IMPEDANCE
The LMF60 lowpass filter input (FILTER IN pin) is not a high
impedance buffer input. This input is a switched capacitor
resistor equivalent, and its effective impedance is inversely
proportional to the clock frequency. The equivalent circuit of
the input to the filter can be seen in
capacitor charges to the input voltage (V
of the clock period, during the second half the charge is
transferred to the feedback capacitor. The total transfer of
charge in one clock cycle is therefore Q
since current is defined as the flow of charge per unit time
the average input current becomes
e
I
Q/T
IN
(where T equals one clock period) or
CINV
IN
e
I
IN
e
CINVINf
T
Figure 5
Figure 6
. The input
) during one half
IN
e
CINVIN, and
CLK
5(b)
.In
the
TL/H/9294– 14
The equivalent input resistor (RIN) then can be defined as
e
VIN/I
R
IN
1
e
IN
CINf
CLK
The input capacitor is 2 pF for the LMF60-50 and 1 pF for
the LMF60-100, so for the LMF60-100
12
1c10
e
R
IN
f
CLK
e
1c10
c
f
C
100
12
e
1c10
f
C
10
and
11
5c10
e
R
IN
f
CLK
e
5c10
c
f
C
11
e
50
1c10
f
C
10
for the LMF60-50. As shown in the above equations, for a
given cutoff frequency (f
same for the LMF60-50 and the LMF60-100. The higher the
) the input impedance remains the
C
clock to cutoff frequency ratio, the greater equivalent input
resistance for a given clock frequency. As the cutoff frequency increases the equivalent input impedance decreases. This input resistance will form a voltage divider with the
source impedance (R
portional to the cutoff frequency, operation at higher cutoff
). Since RINis inversely pro-
SOURCE
frequencies will be more likely to load the input signal which
would appear as an overall decrease in gain at the output of
the filter. Since the filter’s ideal gain is unity, its overall gain
is given by:
R
e
A
V
IN
a
R
R
IN
SOURCE
a) Equivalent Circuit for LMF60 Filter Input
TL/H/9294– 15
FIGURE 6. LMF60 Filter Input
b) Actual Circuit for LMF60 Filter Input
TL/H/9294– 16
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Page 14
2.0 Designing with the LMF60
Given any lowpass filter specification, two equations will
come in handy in trying to determine whether the LMF60 will
do the job. The first equation determines the order of the
lowpass filter required:
n
where n is the order of the filter, A
band attenuation (in dB) desired at frequency f
the passband ripple or attenuation (in dB) at frequency f
the result of this equation is greater than 6, then more than
a single LMF60 is required.
The attenuation at any frequency can be found by the following equation:
Attn(f)
where n
2.1 A LOWPASS DESIGN EXAMPLE
Suppose the amplitude response specification in
given. Can the LMF60 be used? The order of the Butterworth approximation will have to be determined using eq. 1:
A
Since n can only take on integer values, n
the LMF60 can be used. In general, if n is 6 or less a single
LMF60 stage can be utilized.
Likewise, the attenuation at f
2 with the above values and n
This result also meets the design specification given in
ure 8
adequate.
Specification Where the Response of the Filter Design
Must Fall Within the Shaded Area of the Specification
Since the LMF60’s cutoff freqency f
a gain attenuation of
example it needs to be calculated. Solving equation 2 where
e
f
where f
e
log (10
0.1A
Min
b1)b
2 log (fs/fb)
e
10 log[1a(10
e
6 (the order of the filter).
0.1A
log(10
Max
0.1A
Max
b
1)
is the minimum stop-
Min
1) (f/fb)
2n
]
b
, and A
s
dB (2)
Figure 8
e
30 dB, A
Min
e
n
Atten (2 kHz)e10 log[1a(10
log(10
e
e
Max
3
b1)b
30.26 dB
s
log(10
e
2 kHz, and f
0.1
b
1)
1.0 dB, f
2 log(2)
can be found using equation
s
e
6 giving:
0.1
b
1) (2/1)
b
e
5.96
e
6. Therefore
12
again verifying that a single LMF60 section will be
FIGURE 8. Design Example Magnitude Response
TL/H/9294– 21
, which corresponds to
b
3.01 dB, was not specified in this
C
fCas follows:
0.1(3.01 dB)
10
e
f
f
c
b
(10
Ð
0.301
10
e
1
0.1
10
#
e
1.119 kHz
e
f
/50 or f
C
CLK
CLK
0.1A
/100.
b
1)
Max
b
b
1
1/(2n)
b
1)
(
1
1/12
J
Max
b
e
1 kHz
]
Fig-
(1)
.If
To implement this example for the LMF60-50 the clock frequency will have to be set to f
55.95 kHz or for the LMF60-100 f
111.9 kHz
CLK
CLK
e
2.2 CASCADING LMF60s
In the case where a steeper stopband attenuation rate is
required two LMF60’s can be cascaded
is
12th order slope of 72 dB per octave. Because the LMF60
is a Butterworth filter and therefore has no ripple in its passband, when LMF60’s are cascaded the resulting filter also
has no ripple in its passband. Likewise the DC and passband gains will remain at 1V/V. The resulting response is
shown in
Figure 10
.
In determining whether the cascaded LMF60’s will yield a
filter that will meet a particular amplitude response specification, as above, equations 3 and 4 can be used, shown
below.
is
n
Attn(f)
where n
Equation 3 will determine whether the order of the filter is
adequate (n
e
log (10
0.05 A
min
b1)b
2 log (fs/fb)
e
10 log[1a(10
e
6 (the order of each filter).
s
0.05 A
6) while equation 4 can determine if the
log(10
Max
0.05 A
b
1) (f/fb)
required stopband attenuation is met and what actual cutoff
frequency (f
response desired. The design procedure would be identical
) is required to obtain the particular frequency
C
to the one shown in Section 2.1.
2.3 IMPLEMENTING A ‘‘NOTCH’’ FILTER WITH THE
LMF60
A ‘‘notch’’ filter with 60 dB of attenuation can be obtained by
using one of the Op-Amps available in the LMF60 and three
external resistors. The circuit and amplitude response are
shown in
Figure 11
.
The frequency where the ‘‘notch’’ will occur is equal to the
frequency at which the output signal of the LMF60 will have
the same magnitude but be 180 degrees out of phase with
its input signal. For a sixth order Butterworth filter 180
phase shift occurs where fef
tion at this frequency is 0.12 dB which must be compensated for by making R
e
1
e
n
1.014cR2.
0.742 fC. The attenua-
Since R1does not equal R2there will be a gain inequality
above and below the notch frequency. At frequencies below
the notch frequency (fmf
has a gain of one and is non-inverting. Summing this with
the input signal through the Op-Amp yields an overall gain
a
of two or
6 dB. For fnfn, the signal at the output of the
), the signal through the filter
n
filter is greatly attenuated thus only the input signal will appear at the output of the Op-Amp. With R
R
the overall gain is 0.986 orb0.12 dB at frequencies
2
above the notch.
50(1.119 kHz)
e
100(1.119 kHz)
(Figure 9)
Max
b
1)
2n
]
dB (4)
e
R
3
yielding a
e
1.014
1
e
e
(3)
§
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Page 15
2.0 Designing with the LMF60 (Continued)
FIGURE 10a. One LMF60-50 vs.
Two LMF60-50s Cascaded
FIGURE 9. Cascading Two LMF60s
TL/H/9294– 23
TL/H/9294– 22
TL/H/9294– 24
FIGURE 10b. Phase Response
of Two Cascaded LMF60-50s
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Page 16
2.0 Designing with the LMF60 (Continued)
FIGURE 11a. ‘‘Notch’’ Filter
FIGURE 11b. LMF60-50 ‘‘Notch’’ Filter Amplitude Response
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TL/H/9294– 25
TL/H/9294– 26
Page 17
2.0 Designing with the LMF60 (Continued)
2.4 CHANGING CLOCK FREQUENCY
INSTANTANEOUSLY
The LMF60 will respond well to a sudden change in clock
frequency. Distortion in the output signal occurs at the transition of the clock frequency and lasts approximately three
cutoff frequency (f
control signal is low the LMF60-50 has a 100 kHz clock
making f
C
frequency changes to 50 kHz yielding 1 kHz f
The transient response of the LMF60 seen in
also dependent on the f
filter. The LMF60 responds as a classical sixth order Butterworth lowpass filter.
) cycles. As shown in
C
e
2 kHz; when this signal goes high the clock
Figure 12
.
C
Figure 13
and thus the f
c
applied to the
CLK
,ifthe
is
component will be ‘‘reflected’’ about f
quency range
nent is within the passband of the filter and of large enough
below
f
CLK
/2 as in
Figure 14b
/2 into the fre-
CLK
. If this compo-
amplitude it can cause problems. Therefore if frequency
components in the input signal exceed f
attenuated before being applied to the LMF60 input. The
/2 they must be
CLK
necessary amount of attenuation will vary depending on
system requirements. In critical applications the signal components above f
the filter’s residual noise level. An example circuit is shown
in
Figure 15
/2 will have to be attenuated at least to
CLK
using one of the uncommitted Op-Amps avail-
able in the LMF60.
e
f
1.5 kHz (Scope Time Basee2 ms/Div)
IN
FIGURE 12. LMF60-50 Abrupt Clock Frequency Change
TL/H/9294– 27
2.5 ALIASING CONSIDERATIONS
Aliasing effects have to be taken into consideration when
input signal frequencies exceed half the sampling rate. For
the LMF60 this equals half the clock frequency (f
When the input signal contains a component at a frequency
higher than half the clock frequency, as in
Figure 14a
CLK
, that
TL/H/9294– 29
(a) Input Signal Spectrum
FIGURE 14. The phenomenon of aliasing in sampled-data systems. An input signal whose frequency
is greater than one-half the sampling frequency will cause an output to appear
at a frequency lower than one-half the sampling frequency. In the LMF60, f
FIGURE 13. LMF60-50 Step Input Response,
Vertical
1 ms/Div., f
e
2V/Div., Horizontal
e
100 kHz
CLK
).
(b) Output Signal Spectrum. Note that the input signal at
f
/2af causes an output signal to appear at fs/2bf.
s
e
f
s
CLK
TL/H/9294– 28
e
TL/H/9294– 30
.
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Page 18
2.0 Designing with the LMF60 (Continued)
1
e
f
0
2q0R1R2C1C
e
H
R4/R3(H
0
Design Procedure:
pick C
1
e
R
2
2QC
for a 2nd Order Butterworth Qe0.707
0.113
e
R
2
C1f
make R
and
e
C
2
(2qf0R1)2C
Note: The parallel combination of R4(if used), R1and R2should bet10 kX in order not to load Op-AmpÝ2.
FIGURE 15. Second Order Butterworth Anti-Aliasing Filter Using Uncommitted Op-AmpÝ2
2
e
1 when R3and R4are omitted and VO2is directly tied to INV2).
0
1
100
0
e
R
1
2
1
1
TL/H/9294– 31
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Page 19
Physical Dimensions inches (millimeters) unless otherwise noted
Cavity Dual-In-Line Package (J)
Order Number LMF60CMJ-50, LMF60CMJ50/883,
LMF60CMJ-100 or LMF60CMJ100/883
NS Package Number J14A
Order Number LMF60CIWM-50 or LMF60CIWM-100
Small Outline Wide Body (M)
NS Package Number M14B
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Page 20
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Lit.
Molded Dual-In-Line Package (N)
Order Number LMF60CIN-50 or LMF60CIN-100
NS Package Number N14A
Ý
108461
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
LMF60 High Performance 6th-Order Switched Capacitor Butterworth Lowpass Filter
to the user.
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