Page 1
LMF100
High Performance Dual Switched Capacitor Filter
General Description
The LMF100 consists of two independent general purpose
high performance switched capacitor filters. With an external
clock and 2 to 4 resistors, various second-order and
first-order filtering functions can be realized by each filter
block. Each block has 3 outputs. One output can be configured to perform either an allpass, highpass, or notch function. The other two outputs perform bandpass and lowpass
functions. The center frequency of each filter stage is tuned
by usinganexternalclockor a combination of a clock and resistor ratio. Up to a 4th-order biquadratic function can be realized with a single LMF100. Higher order filters are implemented by simply cascading additional packages, and all the
classical filters (such as Butterworth, Bessel, Elliptic, and
Chebyshev) can be realized.
The LMF100 is fabricated on National Semiconductor’s high
performance analog silicon gate CMOS process,
LMCMOS
™
. This allows for the production of a very low offset, high frequency filter building block. The LMF100 is
pin-compatible with the industry standard MF10, but provides greatly improved performance.
Features
n Wide 4V to 15V power supply range
n Operation up to 100 kHz
n Low offset voltage: typically
(50:1 or 100:1 mode): Vos1
=
±
5mV
Vos2
=
±
15 mV
Vos3
=
±
15 mV
n Low crosstalk −60 dB
n Clock to center frequency ratio accuracy
±
0.2%typical
n f
0
x Q range up to 1.8 MHz
n Pin-compatible with MF10
4th Order 100 kHz Butterworth Lowpass Filter
Connection Diagram
LMCMOS™is a trademark of National Semiconductor Corporation.
DS005645-2
DS005645-3
Surface Mount and Dual-In-Line Package
DS005645-18
Top View
Order Number
LMF100CCN or LMF100CIWM
See NS Package Number N20A or M20B
July 1999
LMF100 High Performance Dual Switched Capacitor Filter
© 1999 National Semiconductor Corporation DS005645 www.national.com
Page 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 14)
Supply Voltage (V
+−V−
) 16V
Voltage at Any Pin V
+
+ 0.3V
V
−
− 0.3V
Input Current at Any Pin (Note 2) 5 mA
Package Input Current (Note 2) 20 mA
Power Dissipation (Note 3) 500 mW
Storage Temperature 150˚C
ESD Susceptability (Note 11) 2000V
Soldering Information
N Package: 10 sec. 260˚C
J Package: 10 sec. 300˚C
SO Package:
Vapor Phase (60 sec.) 215˚C
Infrared (15 sec.) 220˚C
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” (Appendix D) for other methods of
soldering surface mount devices.
Operating Ratings (Note 1)
Temperature Range T
MIN
≤ TA≤ T
MAX
LMF100CCN 0˚C ≤ TA≤ +70˚C
LMF100CIWM −40˚C ≤ T
A
≤ +85˚C
Supply Voltage 4V ≤ V
+−V−
≤15V
Electrical Characteristics
The following specifications apply for Mode 1, Q=10 (R
1
=
R
3
=
100k, R
2
=
10k), V
+
=
+5V and V
−
=
−5V unless otherwise
specified. Boldface limits apply for T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions
LMF100CCN LMF100CIWM
Units
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
I
s
Maximum Supply Current f
CLK
=
250 kHz 9 13 13 9 13 mA
No Input Signal
f
0
Center Frequency MIN 0.1 0.1 Hz
Range MAX 100 100 kHz
f
CLK
Clock Frequency MIN 5.0 5.0 Hz
Range MAX 3.5 3.5 MHz
f
CLK/f0
Clock to Center Frequency
Ratio Deviation
V
Pin12
=
5V or 0V
f
CLK
=
1 MHz
±
0.2
±
0.8
±
0.8
±
0.2
±
0.8
%
Q Error (MAX) (Note 4) Q=10, Mode 1
V
Pin12
=
5V or 0V
f
CLK
=
1 MHz
±
0.5
±
5
±
6
±
0.5
±
6
%
H
OBP
Bandpass Gain at f
0
f
CLK
=
1 MHz 0
±
0.4
±
0.4 0
±
0.4 dB
H
OLP
DC Lowpass Gain R
1
=
R
2
=
10k 0
±
0.2
±
0.2 0
±
0.2 dB
f
CLK
=
250 kHz
V
OS1
DC Offset Voltage (Note 5) f
CLK
=
250 kHz
±
5.0
±
15
±
15
±
5.0
±
15 mV
V
OS2
DC Offset Voltage (Note 5) f
CLK
=
250 kHz S
A/B
=
V
+
±
30
±
80
±
80
±
30
±
80 mV
S
A/B
=
V
−
±
15
±
70
±
70
±
15
±
70 mV
V
OS3
DC Offset Voltage (Note 5) f
CLK
=
250 kHz
±
15
±
40
±
60
±
15
±
60 mV
Crosstalk (Note 6) A Side to B Side or
−60 −60 dB
B Side to A Side
Output Noise (Note 12) f
CLK
=
250 kHz N 40 40
20 kHz Bandwidth BP 320 320 µV
100:1 Mode LP 300 300
Clock Feedthrough
(Note 13)
f
CLK
=
250 kHz 100:1 Mode 6 6 mV
V
OUT
Minimum Output R
L
=
5k +4.0
±
3.8
±
3.7
+4.0
±
3.7 V
Voltage Swing (All Outputs) −4.7 −4.7
R
L
=
3.5k +3.9 +3.9
V
(All Outputs) −4.6 −4.6
GBW Op Amp Gain BW Product 5 5 MHz
SR Op Amp Slew Rate 20 20 V/µs
I
sc
Maximum Output
Short
Source (All Outputs) 12 12 mA
Circuit Current
(Note 7)
Sink 45 45 mA
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Page 3
Electrical Characteristics (Continued)
The following specifications apply for Mode 1, Q=10 (R
1
=
R
3
=
100k, R
2
=
10k), V
+
=
+5V and V
−
=
−5V unless otherwise
specified. Boldface limits apply for T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions
LMF100CCN LMF100CIWM
Units
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
I
IN
Input Current on Pins: 4, 5, 10 10 µA
6, 9, 10, 11, 12, 16, 17
Electrical Characteristics
The following specifications apply for Mode 1, Q=10 (R
1
=
R
3
=
100k, R
2
=
10k), V
+
=
+2.50V and V
−
=
−2.50V unless oth-
erwise specified. Boldface limits apply for T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Symbol Parameter Conditions
LMF100CCN LMF100CIWM
Units
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note
10)
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note
10)
I
s
Maximum Supply
Current
f
CLK
=
250 kHz
No Input Signal
81212 8 12 mA
f
0
Center Frequency MIN 0.1 0.1 Hz
Range MAX 50 50 kHz
f
CLK
Clock Frequency MIN 5.0 5.0 Hz
Range MAX 1.5 1.5 MHz
f
CLK/f0
Clock to Center V
Pin12
=
2.5V or 0V
±
0.2
±
1
±
1
±
0.2
±
1
%
Frequency Ratio Deviation f
CLK
=
1 MHz
Q Error (MAX) Q=10, Mode 1
(Note 4) V
Pin12
=
5V or 0V
±
0.5
±
5
±
8
±
0.5
±
8
%
f
CLK
=
1 MHz
H
OBP
Bandpass Gain at f
0
f
CLK
=
1 MHz 0
±
0.4
±
0.5 0
±
0.5 dB
H
OLP
DC Lowpass Gain R
1
=
R
2
=
10k 0
±
0.2
±
0.2 0
±
0.2 dB
f
CLK
=
250 kHz
V
OS1
DC Offset Voltage (Note 5) f
CLK
=
250 kHz
±
5.0
±
15
±
15
±
5.0
±
15 mV
V
OS2
DC Offset Voltage (Note 5) f
CLK
=
250 kHz S
A/B
=
V
+
±
20
±
60
±
60
±
20
±
60 mV
S
A/B
=
V
−
±
10
±
50
±
60
±
10
±
60 mV
V
OS3
DC Offset Voltage (Note 5) f
CLK
=
250 kHz
±
10
±
25
±
30
±
10
±
30 mV
Crosstalk (Note 6) A Side to B Side or −65 −65 dB
B Side to A Side
Output Noise (Note 12) f
CLK
=
250 kHz N 25 25
20 kHz Bandwidth BP 250 250 µV
100:1 Mode LP 220 220
Clock Feedthrough (Note 13) f
CLK
=
250 kHz 100:1 Mode 2 2 mV
V
OUT
Minimum Output R
L
=
5k +1.6
±
1.5
±
1.4
+1.6
±
1.4 V
Voltage Swing (All Outputs) −2.2 −2.2
R
L
=
3.5k +1.5 +1.5 V
(All outputs) −2.1 −2.1
GBW Op Amp Gain BW Product 5 5 MHz
SR Op Amp Slew Rate 18 18 V/µs
I
sc
Maximum Output
Short Circuit
Source (All Outputs) 10 10 mA
Current (Note 7) Sink 20 20 mA
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Logic Input Characteristics
Boldface limits apply for T
MIN
to T
MAX
; all other limits T
A
=
T
J
=
25˚C.
Parameter Conditions
LMF100CCN LMF100CIWM
Units
Typical Tested Design Typical Tested Design
(Note 8) Limit Limit (Note 8) Limit Limit
(Note 9) (Note 10) (Note 9) (Note 10)
CMOS Clock MIN Logical “1” V
+
=
+5V, V
−
=
−5V, +3.0 +3.0 +3.0 V
Input Voltage MAX Logical “0” V
LSh
=
0V −3.0 −3.0 −3.0 V
MIN Logical “1” V
+
=
+10V, V
−
=
0V, +8.0 +8.0 +8.0 V
MAX Logical “0” V
LSh
=
+5V +2.0 +2.0 +2.0 V
TTL Clock MIN Logical “1” V
+
=
+5V, V
−
=
−5V, +2.0 +2.0 +2.0 V
Input Voltage MAX Logical “0” V
LSh
=
0V +0.8 +0.8 +0.8 V
MIN Logical “1” V
+
=
+10V, V
−
=
0V, +2.0 +2.0 +2.0 V
MAX Logical “0” V
LSh
=
0V +0.8 +0.8 +0.8 V
CMOS Clock MIN Logical “1” V
+
=
+2.5V, V
−
=
−2.5V, +1.5 +1.5 +1.5 V
Input Voltage MAX Logical “0” V
LSh
=
0V −1.5 −1.5 −1.5 V
MIN Logical “1” V
+
=
+5V, V
−
=
0V, +4.0 +4.0 +4.0 V
MAX Logical “0” V
LSh
=
+2.5V +1.0 +1.0 +1.0 V
TTL Clock MIN Logical “1” V
+
=
+5V, V
−
=
0V, +2.0 +2.0 +2.0 V
Input Voltage MAX Logical “0” V
LSh
=
0V, V
D
+
=
0V +0.8 +0.8 +0.8 V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
V−or V
IN
>
V+) the absolute value of current at that pin should be limited
to 5 mA or less. The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is P
D
=
(T
JMAX−TA
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
T
JMAX
=
125˚C, and the typical junction-to-ambient thermal resistance of the LMF100CIN when board mounted is 55˚C/W. For the LMF100CIWM this number is
66˚C/W.
Note 4: The accuracy of the Q value is afunction of the center frequency (f
0
). This is illustrated in the curves under the heading “TypicalPeformance Characteristics”.
Note 5: V
os1,Vos2
, and V
os3
refer to the internal offsets as discussed in the Applications Information section 3.4.
Note 6: Crosstalk between the internal filter sections is measured by applyinga1V
RMS
10 kHz signal to one bandpass filter section input and grounding the input
of the other bandpass filter section. The crosstalk is the ratio between the output of the grounded filter section and the 1 V
RMS
input signal of the other section.
Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output
to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8: Typicals are at 25˚C and represent most likely parametric norm.
Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Design limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) but are not 100%tested.
Note 11: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 12: In 50:1 mode the output noise is 3 dB higher.
Note 13: In 50:1 mode the clock feedthrough is 6 dB higher.
Note 14: A military RETS specification is available upon request.
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Page 5
Typical Performance Characteristics
Power Supply Current vs
Power Supply Voltage
DS005645-40
Power Supply Current vs
Temperature
DS005645-41
Output Swing vs
Supply Voltage
DS005645-42
Positive Output Swing
vs Temperature
DS005645-43
Negative Output Swing
vs Temperature
DS005645-44
Positive Output Voltage
Swing vs Load Resistance
DS005645-45
Negative Output Voltage
Swing vs Load Resistance
DS005645-46
f
CLK/f0
Ratio vs Q
DS005645-47
f
CLK/f0
Ratio vs Q
DS005645-48
f
CLK/f0
Ratio vs f
CLK
DS005645-49
f
CLK/f0
Ratio vs f
CLK
DS005645-50
f
CLK/f0
Ratio vs f
CLK
DS005645-51
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Page 6
Typical Performance Characteristics (Continued)
f
CLK/f0
Ratio vs f
CLK
DS005645-52
f
CLK/f0
Ratio vs Temperature
DS005645-53
f
CLK/f0
Ratio vs Temperature
DS005645-54
Q Deviation vs Clock
Frequency
DS005645-55
Q Deviation vs Clock
Frequency
DS005645-56
Q Deviation vs Clock
Frequency
DS005645-57
Q Deviation vs Clock
Frequency
DS005645-58
Q Deviation vs Temperature
DS005645-59
Q Deviation vs Temperature
DS005645-60
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Page 7
Typical Performance Characteristics (Continued)
LMF100 System Block Diagram
Maximum f0vsQat
V
s
=
±
7.5V
DS005645-61
Maximum f0vsQat
V
s
=
±
5.0V
DS005645-62
Maximum f0vsQat
V
s
=
±
2.5V
DS005645-63
DS005645-1
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Page 8
Pin Descriptions
LP(1,20),
BP(2,19),
N/AP/HP(3,18)
The second order lowpass,
bandpass and
notch/allpass/highpass outputs.
These outputs can typically swing
to within 1V of each supply when
drivinga5kΩload. For optimum
performance, capacitive loading
on these outputs should be
minimized. For signal frequencies
above 15 kHz the capacitance
loading should be kept below
30 pF.
INV(4,17) The inverting input of the
summing opamp of each filter.
These are high impedance inputs.
The non-inverting input is
internally tied to AGND so the
opamp can be used only as an
inverting amplifier.
S1(5,16) S1 is a signal input pin used in
modes 1b, 4, and 5. The input
impedance is 1/f
CLK
x 1 pF. The
pin should be driven with a source
impedance of less than 1 kΩ.If
S1 is not driven with a signal it
should be tied to AGND
(mid-supply).
S
A/B
(6) This pin activates a switch that
connects one of the inputs of each
filter’s second summer either to
AGND (S
A/B
tied to V−)ortothe
lowpass (LP) output (S
A/B
tied to
V
+
). This offers the flexibility
needed for configuring the filter in
its various modes of operation.
V
A
+
(7) (Note 15) This is both the analog and digital
positive supply.
V
D
+
(8) (Note 15) This pin needs to be tied to V
+
except when the device is to
operate on a single 5V supply and
a TTL level clock is applied. For
5V, TTL operation, V
D
+
should be
tied to ground (0V).
V
A
−
(14), V
D
−
(13) Analog and digital negative
supplies. V
A
−
and V
D
−
should be
derived from the same source.
They have been brought out
separately so they can be
bypassed by separate capacitors,
if desired. They can also be tied
together externally and bypassed
with a single capacitor.
LSh(9) Level shift pin. This is used to
accommodate various clock levels
with dual or single supply
operation. With dual
±
5V supplies
and CMOS (
±
5V) or TTL (0V–5V)
clock levels, LSh should be tied to
system ground.
For 0V–10V single supply
operation the AGND pin should be
biased at +5V and the LSh pin
should be tied to the system
ground for TTL clock levels. LSh
should be biased at +5V for
±
5V
CMOS clock levels.
The LSh pin is tied to system
ground for
±
2.5V operation. For
single 5V operation the LSh and
V
D
+ pins are tied to system
ground for TTL clock levels.
CLK(10,11) Clock inputs for the two switched
capacitor filter sections. Unipolar
or bipolar clock levels may be
applied to the CLK inputs
according to the programming
voltage applied to the LSh pin.
The duty cycle of the clock should
be close to 50%, especially when
clock frequencies above 200 kHz
are used. This allows the
maximum time for the internal
opamps to settle, which yields
optimum filter performance.
50/100(12)
(Note 15)
By tying this pin to V
+
a 50:1 clock
to filter center frequency ratio is
obtained. Tying this pin at
mid-supply (i.e., system ground
with dual supplies) or to V
−
allows
the filter to operate at a 100:1
clock to center frequency ratio.
AGND(15) This is the analog ground pin.
This pin should be connected to
the system ground for dual supply
operation or biased to mid-supply
for single supply operation. For a
further discussion of mid-supply
biasing techniques see the
Applications Information (Section
3.2). For optimum filter
performance a “clean” ground
must be provided.
Note 15: This device is pin-for-pin compatible with the MF10 except for the
following changes:
1. Unlike the MF10, the LMF100 has a single positive supply pin (V
A
+).
2. On the LMF100 V
D
+
is a control pin and is not the digital positive supply as
on the MF10.
3. Unlike the MF10, the LMF100 does not support the current limiting mode.
When the 50/100 pin is tied to V
−
the LMF100 will remain in the 100:1 mode.
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Page 9
1.0 Definitions of Terms
f
CLK
: the frequency of the external clock signal applied to pin
10 or 11.
f
0
: center frequency of the second order function complex
pole pair. f
0
is measured at the bandpass outputs of the
LMF100, and is the frequency of maximum bandpass gain.
(
Figure 1
).
f
notch
: the frequency of minimum (ideally zero) gain at the
notch outputs.
f
z
: the center frequency of the second order complex zero
pair, if any. If f
z
is different from f0and if Qzis high, it can be
observed as the frequency of a notch at the allpass output.
(
Figure 13
).
Q: “quality factor” of the 2nd order filter.Q is measured at the
bandpass outputs of the LMF100 and is equal to f
0
divided
by the −3 dB bandwidth of the 2nd order bandpass filter (
Fig-
ure 1
). The value of Q determines the shape of the 2nd order
filter responses as shown in
Figure 6
.
Q
z
: the quality factor of the second order complex zero pair,
if any. Q
Z
is related to the allpass characteristic, which is
written:
where Q
Z
=
Q for an all-pass response.
H
OBP
: the gain (in V/V) of the bandpass output at f=f0.
H
OLP
: the gain (in V/V) of the lowpass output as f→0Hz
(
Figure 2
).
H
OHP
: the gain (in V/V) of the highpass output as f→f
CLK
/2
(
Figure 3
).
H
ON
: the gain (in V/V) of the notch output as f→0 Hz and as
f→f
CLK
/2, when the notch filter has equal gain above and
below the center frequency (
Figure 4
). When the
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3a (
Figure 10
and
Figure 12
), the two quan-
tities below are used in place of H
ON
.
H
ON1
: the gain (in V/V) of the notch output as f→0 Hz.
H
ON2
: the gain (in V/V) of the notch output as f→f
CLK
/2.
DS005645-19
(a)
DS005645-20
(b)
FIGURE 1. 2nd-Order Bandpass Response
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Page 10
1.0 Definitions of Terms (Continued)
DS005645-21
(a)
DS005645-22
(b)
FIGURE 2. 2nd-Order Low-Pass Response
DS005645-23
(a)
DS005645-24
(b)
FIGURE 3. 2nd-Order High-Pass Response
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Page 11
1.0 Definitions of Terms (Continued)
DS005645-25
(a)
DS005645-26
(b)
FIGURE 4. 2nd-Order Notch Response
DS005645-27
(a)
DS005645-28
(b)
FIGURE 5. 2nd-Order All-Pass Response
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Page 12
1.0 Definitions of Terms (Continued)
(a) Bandpass
DS005645-64
(b) Low Pass
DS005645-65
(c) High-Pass
DS005645-66
(d) Notch
DS005645-67
(e) All-Pass
DS005645-68
FIGURE 6. Response of various 2nd-order filters as a function of Q. Gains
and center frequencies are normalized to unity.
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Page 13
2.0 Modes of Operation
The LMF100 is a switched capacitor (sampled data) filter.To
fully describe its transfer functions, a time domain analysis is
appropriate. Since this is cumbersome, and since the
LMF100 closely approximates continuous filters, the following discussion is based on the well-known frequency domain. Each LMF100 can produce two full 2nd order functions. See
Table1
for a summary of the characteristics of the
various modes.
MODE 1: Notch 1, Bandpass, Lowpass Outputs:
f
notch
=
f
0
(See
Figure 7
)
MODE 1a: Non-Inverting BP, LP (See
Figure 8
)
Note: VINshould be driven from a low impedance (<1kΩ) source.
DS005645-11
FIGURE 7. MODE 1
DS005645-4
FIGURE 8. MODE 1a
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Page 14
2.0 Modes of Operation (Continued)
MODE 1b: Notch 1, Bandpass, Lowpass Outputs:
f
notch
=
f
0
(See
Figure 9
)
MODE 2: Notch 2, Bandpass, Lowpass: f
notch
<
f
0
(See
Figure 10
)
DS005645-14
FIGURE 9. MODE 1b
DS005645-36
FIGURE 10. MODE 2
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Page 15
2.0 Modes of Operation (Continued)
MODE 3: Highpass, Bandpass, Lowpass Outputs
(See
Figure 11
)
MODE 3a: HP, BP, LP and Notch with External Op Amp
(See
Figure 12
)
DS005645-5
*
In Mode 3, the feedback loop is closed around the input summing amplifier; the finite GBW product of this op amp causes a slight Q enhancement. If this is a
problem, connect a small capacitor (10 pF−100 pF) across R4 to provide some phase lead.
FIGURE 11. MODE 3
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Page 16
2.0 Modes of Operation (Continued)
MODE 4: Allpass, Bandpass, Lowpass Outputs
(See
Figure 13
)
*
Due to the sampled data nature of the filter, a slight mismatch of fzand f
0
occurs causing a 0.4 dB peaking around f0of the allpass filter amplitude
response (which theoretically should be a straight line). If this is
unacceptable, Mode 5 is recommended.
MODE 5: Numerator Complex Zeros, BP, LP
(See
Figure 14
)
DS005645-10
FIGURE 12. MODE 3a
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Page 17
2.0 Modes of Operation (Continued)
MODE 6a: Single Pole, HP, LP Filter (See
Figure 15
)
DS005645-6
FIGURE 13. MODE 4
DS005645-15
FIGURE 14. MODE 5
DS005645-16
FIGURE 15. MODE 6a
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Page 18
2.0 Modes of Operation (Continued)
MODE 6b: Single Pole LP Filter (Inverting and Non-
Inverting) (See
Figure 16
)
MODE 6c: Single Pole, AP, LP Filter (See
Figure 17
)
DS005645-7
FIGURE 16. MODE 6b
DS005645-17
FIGURE 17. MODE 6c
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Page 19
2.0 Modes of Operation (Continued)
MODE 7: Summing Integrator (See
Figure 18
)
DS005645-37
Equivalent Circuit
DS005645-38
FIGURE 18. MODE 7
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Page 20
2.0 Modes of Operation (Continued)
TABLE 1. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks.
Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios.
Mode BP LP HP N AP Number of Adjustable Notes
Resistors f
CLK/f0
1
** *
3No
(2) May need input buffer.
1a H
OBP1
=
−Q H
OLP
=
+ 1 2 No Poor dynamics
H
OBP2
=
+1 for high Q.
1b
** *
3 No Useful for high
frequency applications.
Yes (above
2
** *
3f
CLK
/50 or
f
CLK
/100)
Universal State-
3
***
4 Yes Variable Filter. Best
general-purpose mode.
As above, but also
3a
****
7 Yes includes resistor-
tuneable notch.
Gives Allpass res-
4
** *
3 No ponse with H
OAP
=
−1
and H
OLP
=
−2.
Gives flatter allpass
5
** *
4 Yes response than above
if R
1
=
R
2
=
0.02R
4
.
6a
**
3 Yes Single pole.
(2)
6b H
OLP1
=
+ 1 2 Yes Single pole.
6c
**
3 No Single pole.
7 2 Yes Summing integrator with
adjustable time constant.
3.0 Applications Information
The LMF100 is a general purpose dual second-order state
variable filter whose center frequency is proportional to the
frequency of the square wave applied to the clock input
(f
CLK
). The various clocking options are summarized in the
following table.
Clocking Options
Power Supply Clock Levels LSh V
D
+
−5V and +5V TTL (0V to +5V) 0V +5V
−5V and +5V CMOS (−5V to +5V) 0V +5V
0V and 10V TTL (0V to 5V) 0V +10V
0V and 10V CMOS (0V to +10V) +5V +10V
−2.5V and
+2.5V
CMOS
0V +2.5V
(−2.5V to +2.5V)
0V and 5V TTL (0V to +5V) 0V 0V
Power Supply Clock Levels LSh V
D
+
0V and 5V CMOS (0V to +5V) +2.5V +5V
By connecting pin 12 to the appropriate dc voltage, the filter
center frequency,f
0
, can be made equal to either f
CLK
/100 or
f
CLK
/50. f0can be very accurately set (within±0.6%)byusing a crystal clock oscillator, or can be easily varied over a
wide frequency range by adjusting the clock frequency. If desired, the f
CLK/f0
ratio can be altered by external resistors as
in
Figures 10, 11,12, 13, 14, 15
and
Figure 16
. This is useful
when high-order filters (greater than two) are to be realized
by cascading the second-order sections. This allows each
stage to be stagger tuned while using only one clock. The filter Q and gain are set by external resistor ratios.
All of the five second-order filter types can be built using either section of the LMF100. These are illustrated in
Figures
1, 2, 3, 4
and
Figure 5
along with their transfer functions and
some related equations.
Figure 6
shows the effect of Q on
the shapes of these curves.
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Page 21
3.0 Applications Information
(Continued)
3.1 DESIGN EXAMPLE
In order to design a filter using the LMF100, we must define
the necessary values of three parameters for each
second-order section: f
0
, the filter section’s center frequency;
H
0
, the passband gain; and the filter’s Q. These are determined by the characteristics required of the filter being designed.
As an example, let’s assume that a system requires a
fourth-order Chebyshev low-pass filter with 1 dB ripple, unity
gain at dc, and 1000 Hz cutoff frequency.As the system order is four, it is realizable using both second-order sections
of an LMF100. Many filter design texts (and National’s
Switched Capacitor Filter Handbook) include tables that list
the characteristics (f
0
and Q) of each of the second-order filter sections needed to synthesize a given higher-order filter.
For the Chebyshev filter defined above, such a table yields
the following characteristics:
f
0A
=
529 Hz Q
A
=
0.785
f
0B
=
993 Hz Q
B
=
3.559
For unity gain at dc, we also specify:
H
0A
=
1
H
0B
=
1
The desired clock-to-cutoff-frequency ratio for the overall filter of this example is 100 and a 100 kHz clock signal is available. Note that the required center frequencies for the two
second-order sections will not be obtainable with
clock-to-center-frequency ratios of 50 or 100. It will be necessary to adjust
externally.From
Table1
, we see that Mode 3 can be used to
produce a low-pass filter with resistor-adjustable center frequency.
In most filter designs involving multiple second-order stages,
it is best to place the stages with lower Q values ahead of
stages with higher Q, especially when the higher Q is greater
than 0.707. This is due to the higher relative gain at the center frequency of a higher-Q stage. Placing a stage with lower
Q ahead of a higher-Q stage will provide some attenuation at
the center frequency and thus help avoid clipping of signals
near this frequency. For this example, stage A has the lower
Q (0.785) so it will be placed ahead of the other stage.
For the first section, we begin the design by choosing a convenient value for the input resistance: R
1A
=
20k. The abso-
lute value of the passband gain H
OLPA
is made equal to 1 by
choosing R
4A
such that: R
4A
=
−H
OLPAR1A
=
R
1A
=
20k. If
the 50/100/CL pin is connected to mid-supply for nominal
100:1 clock-to-center-frequency ratio, we find R
2A
by:
The resistors for the second section are found in a similar
fashion:
The complete circuit is shown in
Figure 19
for split±5V
power supplies. Supply bypass capacitors are highly
recommended.
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Page 22
3.0 Applications Information (Continued)
DS005645-30
FIGURE 19. Fourth-order Chebyshev low-pass filter from example in 3.1.
±
5V power supply. 0V–5V TTL or±5V CMOS logic levels.
DS005645-31
FIGURE 20. Fourth-order Chebyshev low-pass filter from example in 3.1. Single +10V power supply. 0V–5V TTL logic
levels. Input signals should be referred to half-supply or applied through a coupling capacitor.
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Page 23
3.0 Applications Information (Continued)
3.2 SINGLE SUPPLY OPERATION
The LMF100 can also operate with a single-ended power
supply.
Figure 20
shows the example filter with a
single-ended power supply. V
A
+ and VD+ are again con-
nected to the positive power supply (4 to 15 volts), and V
A
−
and V
D
− are connected to ground. The A
GND
pin must be
tied to V
+
/2 for single supply operation. This half-supply point
should be very “clean”, as any noise appearing on it will be
treated as an input to the filter. It can be derived from the
supply voltage with a pair of resistors and a bypass capacitor
(
Figure 21a
), or a low-impedance half-supply voltage can be
made using a three-terminal voltage regulator or an operational amplifier (
Figure 21b
and
Figure 21c
). The passive resistor divider with a bypass capacitor is sufficient for many
applications, provided that the time constant is long enough
to reject any power supply noise. It is also important that the
half-supply reference present a low impedance to the clock
frequency, so at very low clock frequencies the regulator or
op-amp approaches may be preferable because they will require smaller capacitors to filter the clock frequency. The
main power supply voltage should be clean (preferably regulated) and bypassed with 0.1 µF.
3.3 DYNAMIC CONSIDERATIONS
The maximum signal handling capability of the LMF100, like
that of any active filter, is limited by the power supply voltages used.The amplifiers in the LMF100 are able to swing to
within about 1 volt of the supplies, so the input signals must
be kept small enough that none of the outputs will exceed
these limits. If the LMF100 is operating on
±
5 volts, for ex-
ample, the outputs will clip at about 8V
p-p
. The maximum input voltage multiplied by the filter gain should therefore be
less than 8V
p-p
.
Note that if the filter Q is high, the gain at the lowpass or
highpass outputs will be much greater than the nominal filter
gain (
Figure 6
). As an example, a lowpass filter withaQof
10 will have a 20 dB peak in its amplitude response at f
0
.If
the nominal gain of the filter (H
OLP
) is equal to 1, the gain at
f
0
will be 10. The maximum input signal at f0must therefore
be less than 800 mV
p-p
when the circuit is operated on±5
volt supplies.
Also note that one output can have a reasonable small volt-
age on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1 (
Figure 7
). The notch out-
put will be very small at f
0
, so it might appear safe to apply a
large signal to the input. However, the bandpass will have its
maximum gain at f
0
and can clip if overdriven. If one output
clips, the performance at the other outputs will be degraded,
so avoid overdriving any filter section, even ones whose out-
puts are not being directly used.Accompanying
Figures 7, 8,
9, 10, 11, 12, 13, 14, 15, 16
and
Figure 17
are equations labeled “circuit dynamics”, which relate the Q and the gains at
the various outputs. These should be consulted to determine
peak circuit gains and maximum allowable signals for a
given application.
3.4 OFFSET VOLTAGE
The LMF100’s switched capacitor integrators have a slightly
higher input offset voltage than found in a typical continuous
time active filter integrator. Because of National’s new LMCMOS process and new design techniques the internal offsets
have been minimized, compared to the industry standard
MF10.
Figure 22
shows an equivalent circuit of the LMF100
from which the output dc offsets can be calculated. Typical
values for these offsets with S
A/B
tied to V+are:
V
OS1
=
opamp offset
=
±
5mV
V
OS2
=
±
30 mV at 50:1 or 100:1
V
OS3
=
±
15 mV at 50:1 or 100:1
When S
A/B
is tied to V−,V
OS2
will approximately halve. The
dc offset at the BP output is equal to the input offset of the
lowpass integrator (V
OS3
). The offsets at the other outputs
depend on the mode of operation and the resistor ratios, as
described in the following expressions.
Mode 1 and Mode 4
Mode 1a
DS005645-32
(a) Resistive Divider with
Decoupling Capacitor
DS005645-33
(b) Voltage Regulator
DS005645-34
(c) Operational Amplifier with
Divider
FIGURE 21. Three Ways of Generating V
+
/2 for Single-Supply Operation
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Page 24
3.0 Applications Information
(Continued)
Mode 1b
Mode 2 and Mode 5
Mode 3
Mode 6a and 6c
Mode 6b
In many applications, the outputs are ac coupled and dc offsets are not bothersome unless large signals are applied to
the filter input. However, larger offset voltages will cause
clipping to occur at lower ac signal levels, and clipping at any
of the outputs will cause gain nonlinearities and will change
f
0
and Q. When operating in Mode 3, offsets can become ex-
cessively large if R
2
and R4are used to make f
CLK/f0
significantly higher than the nominal value, especially if Q is also
high.
For example,
Figure 23
shows a second-order 60 Hz notch
filter. This circuit yields a notch with about 40 dB of attenuation at 60 Hz. A notch is formed by subtracting the bandpass
output of a mode 3 configuration from the input using the un-
used side B opamp. The Q is 10 and the gain is 1 V/V in the
passband. However, f
CLK/f0
=
1000 to allow for a wide input
spectrum. This means that for pin 12 tied to ground (100:1
mode), R4/R2=100. The offset voltage at the lowpass output (LP) will be about 3V. However, this is an extreme case
and the resistor ratio is usually much smaller. Where necessary,the offset voltage can be adjusted by using the circuit of
Figure 24
. This allows adjustment of V
OS1
, which will have
varying effects on the different outputs as described in the
above equations. Some outputs cannot be adjusted this way
in some modes, however (V
OS(BP)
in modes 1a and 3, for
example).
DS005645-12
FIGURE 22. Offset Voltage Sources
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Page 25
3.0 Applications Information (Continued)
3.5 SAMPLED DATA SYSTEM CONSIDERATIONS
The LMF100 is a sampled data filter, and as such, differs in
many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect
on signals at frequencies greater than one-half the sampling
frequency. (The LMF100’s sampling frequency is the same
as its clock frequency.) If a signal with a frequency greater
than one-half the sampling frequency is applied to the input
of a sampled data system, it will be “reflected” to a frequency
less than one-half the sampling frequency. Thus, an input
signal whose frequency is f
s
/2 + 100 Hz will cause the system to respond as though the input frequency was
f
s
/2 − 100 Hz. This phenomenon is known as “aliasing”, and
can be reduced or eliminated by limiting the input signal
spectrum to less than f
s
/2. This may in some cases require
the use of a bandwidth-limiting filter ahead of the LMF100 to
limit the input spectrum. However, since the clock frequency
is much higher than the center frequency, this will often not
be necessary.
Another characteristic of sampled-data circuits is that the
output signal changes amplitude once every sampling period, resulting in “steps” in the output voltage which occur at
the clock rate (
Figure 25
). If necessary, these can be
“smoothed” with a simple R-C low-pass filter at the LMF100
output.
The ratio of f
CLK
to fc(normally either 50:1 or 100:1) will also
affect performance. A ratio of 100:1 will reduce any aliasing
problems and is usually recommended for wide-band input
DS005645-39
R1=100 kΩ
R2=1kΩ
R3=100 kΩ
R4=100 kΩ
Rg=10 kΩ
Rl=10 kΩ
Rh=10 kΩ
FIGURE 23. Second-Order Notch Filter
DS005645-13
FIGURE 24. Method for Trimming V
OS
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Page 26
3.0 Applications Information
(Continued)
signals. In noise-sensitive applications, a ratio of 100:1 will
result in 3 dB lower output noise for the same filter configuration.
The accuracy of the f
CLK/f0
ratio is dependent on the value of
Q. This is illustrated in the curves under the heading “Typical
Performance Characteristics”. As Q is changed, the true
value of the ratio changes as well. Unless the Q is low, the
error in f
CLK/f0
will be small. If the error is too large for a specific application, use a mode that allows adjustment of the ratio with external resistors.
DS005645-35
FIGURE 25. The Sampled-Data Output Waveform
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Page 27
Physical Dimensions inches (millimeters) unless otherwise noted
Small Outline Package
Order Number LMF100CIWM
NS Package Number M20B
Molded Dual-In-Line Package (N)
Order Number LMF100CCN
NS Package Number N20A
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Page 28
Notes
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Tel: 1-800-272-9959
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www.national.com
LMF100 High Performance Dual Switched Capacitor Filter
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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