Page 1
LMC835 Digital Controlled Graphic Equalizer
LMC835 Digital Controlled Graphic Equalizer
February 1995
General Description
The LMC835 is a monolithic, digitally-controlled graphic
equalizer CMOS LSI for Hi-Fi audio. The LMC835 consists
of a Logic section and a Signal Path section made of analog
switches and thin-film silicon-chromium resistor networks.
The LMC835 is used with external resonator circuits to
make a stereo equalizer with seven bands,
g
12 dB org6
dB gain range and 25 steps each. Only three digital inputs
are needed to control the equalization. The LMC835 makes
it easy to build a mP-controlled equalizer.
The signal path is designed for very low noise and distortion, resulting in very high performance, compatible with
PCM audio.
Connection Diagrams
Dual-In-Line Package
Features
Y
No volume controls required
Y
Three-wire interface
Y
14 bands, 25 steps each
Y
g
12 dB org6 dB gain ranges
Y
Low noise and distortion
Y
TTL, CMOS logic compatible
Applications
Y
Hi-Fi equalizer
Y
Receiver
Y
Car stereo
Y
Musical instrument
Y
Tape equalization
Y
Mixer
Y
Volume controller
Molded Chip Carrier Package
Top View
TL/H/6753– 26
Order Number LMC835V
See NS Package V28A
Top View
TL/H/6753– 1
Order Number LMC835N
See NS Package N28B
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
TL/H/6753
Page 2
Block Diagram
TL/H/6753– 2
2
Page 3
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V
Allowable Input Voltage (Note 1) V
Storage Temperature, T
Lead Temperature (Soldering, 10 sec), N Pkg
Lead Temperature, V Pkg
Vapor Phase (60 sec)
Infrared (15 sec)
DD
b
V
SS
b
stg
60§Ctoa150§C
to V
DD
SS
a
a
a
18V
b
0.3V
a
0.3V
260§C
215§C
220§C
Operating Ratings
Supply Voltage, V
Digital Ground (Pin 13) VSSto V
Digital Input (Pins 14, 15, 16) VSSto V
Analog Input (Pins 1, 2, 3, 4, 25, 26, 27)
(Note 1) V
Operating Temperature, T
DD
b
V
SS
opr
5V to 16V
SS
b
40§Ctoa85§C
to V
DD
DD
DD
Electrical Characteristics (Note 2) V
LOGIC SECTION
DD
e
7.5V, V
eb
7.5V, A.GNDe0V
SS
Tested Design
Symbol Parameter Test Conditions Typ Limit Limit
(Note 3) (Note 4)
I
DDL
I
SSL
I
DDH
I
SSH
V
IH
V
IL
f
o
t
w(STB)
t
setup
t
hold
t
cs
I
IN
C
IN
Note 1: Pins 2, 3 and 26 have a maximum input voltage range ofg22V for the typical application shown in
Note 2: Bold numbers apply at temperature extremes. All other numbers apply at T
circuit,
Note 3: Guaranteed and 100% production tested.
Note 4: Guaranteed (but not 100% production tested) over the operating temperature range. These limits are not used to calculate outgoing quality levels.
Supply Current Pins 14, 15, 16 are 0V 0.01 0.5 0.5 mA (Max)
Pins 14, 15, 16 are 0V 0.01 0.5 0.5 mA (Max)
Pins 14, 15, 16 are 5V 1.3 5 5 mA (Max)
Pins 14, 15, 16 are 5V 0.9 5 5 mA (Max)
High-Level Input Voltage
Low-Level Input Voltage
Clock Frequency
Width of STB Input See
Data Setup Time See
Data Hold Time See
Delay from Rising Edge of CLOCK See
@
Pins 14, 15, 16 1.8 2.3 2.5 V (Min)
@
Pins 14, 15, 16 0.9 0.6 0.4 V (Max)
@
Pin 14 2000 500 500 kHz (Max)
Figure 1
Figure 1
Figure 1
Figure 1
0.25 1 1 ms (Min)
0.25 1 1 ms (Min)
0.25 1 1 ms (Min)
0.25 1 1 ms (Min)
to STB
A
e
25§C, V
k
5Vg0.01
IN
e
7.5V, V
DD
g
1 mA (Max)
Figure 7
.
eb
7.5V,D.GNDeA.GNDe0V as shown in the test
SS
Input Current
Input Capacitance
Figures 3
and4.
@
Pins 14, 15, 16 0VkV
@
Pins 14, 15, 16 fe1 MHz 5 pF
Timing Diagram
Unit
(Limit)
Note: To change the gain of the presently selected band, it is not necessary to send DATA 1 (Band Selection) each time.
FIGURE 1
3
TL/H/6753– 3
Page 4
Electrical Characteristics (Note 2) V
DD
e
7.5V, V
eb
7.5V, D.GNDeA.GNDe0V
SS
SIGNAL PATH SECTION
Symbol Parameter Test Conditions Typ Limit Limit
@
E
A
THD Total Harmonic A
V
O Max
Gain Error A
Distortion V
Maximum Output Voltage A
S/N Signal to Noise Ratio A
I
LEAK
Note 2; Boldface numbers apply at temperature extremes. All other numbers apply at T
test circuit,
Note 3: Guaranteed and 100% production tested.
Note 4: Guaranteed (but not 100% production tested) over the operating temperature range. These limits are not used to calculate outgoing quality levels.
Leakage Current A
Figures 3
and4.
e
V
e
A
V
e
A
V
(R
e
A
V
(R4bor R4cis ON)
e
A
V
(R
e
A
V
(R
e
A
V
(R
e
A
V
(R
e
V
e
A
V
V
V
eb
A
V
V
V
e
V
THD
e
V
V
e
A
V
V
eb
A
V
V
e
V
(All internal switches are OFF)
Pin 2
Pin 5EPin 11, Pin 18EPin 24 50 nA (Max)
g
0dB
0dB
g
5b
g
g
3b
g
2b
g
1b
g
0b
0dB
IN
12 dB
IN
IN
IN
IN
0dB
0dB
ref
ref
ref
0dB
e
e
e
e
e
12 dB
12 dB Range 0.1 0.5 0.5 dB (Max)
@
g
6 dB Range 0.1 1 1 dB (Max)
@
g
1dB
or R5cis ON)
2dB
3dB
or R3cis ON)
4dB
or R2cis ON)
5dB
or R1cis ON)
9dB
or R0cis ON)
12 dB
k
e
e
12 dB
e
a
dB Range 0.1 0.5 0.6 dB (Max)
@
g
12 dB Range 0.1 0.5 0.6 dB (Max)
@
g
12 dB Range 0.1 0.5 0.6 dB (Max)
@
g
12 dB Range 0.1 0.5 0.7 dB (Max)
@
g
12 dB Range 0.1 0.5 0.7 dB (Max)
@
g
12 dB Range 0.2 1 1.3 dB (Max)
@
g
12 dB Range 0.0015 %
4V
,fe1 kHz
rms
@
g
12 dB Range
1V
,fe1 kHz 0.01 0.1 % (Max)
rms
1V
,fe20 kHz 0.1 0.5 % (Max)
rms
@
g
4V
4V
1V
1V
1V
12 dB Range
,fe1 kHz 0.01 0.1 % (Max)
rms
,fe20 kHz 0.1 0.5 % (Max)
rms
@
g
12 dB Range 5.5 5.1 5 V
1%, fe1 kHz
@
g
12 dB Range 114 dB
rms
@
g
12 dB Range 106 dB
rms
@
g
12 dB Range 116 dB
rms
@
g
12 dB Range
3, Pin 26 500 nA (Max)
e
A
25§C, V
e
DD
Tested Design
(Note 3) (Note 4)
eb
7.5V, V
SS
rms
7.5V, D.GNDeA.GNDe0V as shown in the
Unit
(Limit)
(Min)
Timing Diagrams
Note: To change the gain of the presently selected band, it is not necessary to send DATA 1 (Band Selection) each time.
FIGURE 2
4
TL/H/6753– 4
Page 5
Truth Tables
DATA I (Band Selection)
D7 D6 D5 D4 D3 D2 D1 D0
HXLLLLLL
HXLLLLLH
HXLLLLHL
HXLLLLHH
HXLL LHLL
HXLL LHLH
HXLL LHHL
HX L L L HHH
HXLLHLLL
HXLLHL LH
HXLLHLHL
HXLLHLHH
HXLLHHLL
HXLLHHLH
HX L LHHHL
HX L LHHHH
H X L H Valid Binary Input
H X H L Valid Binary Input
H X H H Valid Binary Input
w
uuuu
jklm
j
DATA 1
k Don’t Care
g
l Ch A
m Ch B
6 dB/g12 dB Range
g
6 dB/g12 dB Range
Band Code
x
(Ch A: Band 1E7, Ch B: Band 8E14)
g
Ch A
12 dB Range, Ch Bg12 dB Range, No Band Selection
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 1
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 2
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 3
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 4
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 5
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 6
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 7
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 8
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 9
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 10
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 11
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 12
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 13
g
Ch A
12 dB Range, Ch Bg12 dB Range, Band 14
g
Ch A
12 dB Range, Ch Bg12 dB Range, No Band Selection
g
Ch A
12 dB Range, Ch Bg6 dB Range, Band 1E14
g
Ch A
6 dB Range, Ch Bg12 dB Range, Band 1E14
g
Ch A
6 dB Range, Ch Bg6 dB Range, Band 1E14
g
This is the gain if the
selected by DATA I. If the
range is selected, then the values
shown must be approximately halved.
See the characteristics curves for
more exact data.
12 dB range is
g
6dB
DATA II (Gain Selection)
D7 D6 D5 D4 D3 D2 D1 D0
Flat L X L L L L L L
1 dB Boost L H H L L L L L
2 dB Boost L H L H L L L L
3 dB Boost L H L L H L L L
4 dB Boost L H L L L H L L
5 dB Boost L H L L L L H L
6 dB Boost L H L H L L H L
7 dB Boost L H H L H L H L
8 dB Boost L H L H L H H L
9 dB Boost L H L L L L L H
10 dB Boost L H H L H L L H
11 dB Boost L H H L H H L H
12 dB Boost L H H L H H H H
E
$1dB
n
o Boost/Cut
12 dB Cut L L
DATA II
5
uu
no
Valid Above Input
w
Gain Code
x
Page 6
Test Circuits
FIGURE 3. Test Circuit for AC Measurement
FIGURE 4. Test Circuit for Leakage Current Measurement
6
TL/H/6753– 5
TL/H/6753– 6
Page 7
Test Circuits (Continued)
FIGURE 5. I to V Converter
FIGURE 6. Simple Word Generator
Typical Performance Characteristics
TL/H/6753– 7
TL/H/6753– 8
Supply Current vs
Supply Voltage
Supply Current vs
Temperature
7
Input Capacitance vs
Input Voltage
TL/H/6753– 9
Page 8
Typical Performance Characteristics (Continued)
Maximum Output Voltage
vs Supply Voltage
Distortion vs Frequency
@
g
12 dB Range
Distortion vs Output Voltage
@
g
6 dB Range
Maximum Output Voltage
vs Temperature
Distortion vs Frequency
@
g
6 dB Range
Gain vs Frequency
@
g
12 dB Range (Boost)
Nominal Resistor
vs Temperature
Distortion vs Output Voltage
@
g
12 dB Range
Gain vs Frequency
@
g
12 dB Range (Cut)
Gain vs Frequency
@
g
6 dB Range (Boost)
Gain vs Frequency
@
g
6 dB Range (Cut) Gain vs Temperature
8
TL/H/6753– 10
Page 9
Typical Applications
FIGURE 7. Stereo 7-Band Equalizer
TABLE I: Tuned Circuit Elements
e
Q
3.5, Q
0
12dB
e
1.05
Z1 fo(Hz) CO(F) CL(F) RL(X)RO(X)
Z1 63 1m 0.1m 100k 680
Z2 160 0.47 m 0.033m 100k 680
Z3 400 0.15 m 0.015m 100k 680
Z4 1k 0.068m 0.0068m 82k 680
Z5 2.5k 0.022m 0.0033m 82k 680
Z6 6.3k 0.01m 0.0015m 62k 680
Z7 16k 0.0047m 680p 47k 680
TL/H/6753– 11
e
L
CLRLR
0
0
1
e
f
0
2q0L0C
0
L
0
e
Q
0
2
C0R
0
0
R0Q
0
e
Q
12 dB
a
R
1590
0
TL/H/6753– 12
FIGURE 8. Tuned Circuit for Stereo
7-Band Equalizer (
Figure 7
)
9
Page 10
Typical Applications (Continued)
LMC835 Gain vs Frequency
@
g
12 dB Range
(All Boost or Cut)
Performance Characteristics (Circuit of
Figure 7
)
LMC835 Gain vs Frequency
@
g
12 dB Range
(1 kHz Boost or Cut)
LMC835 Gain vs Frequency
@
g
6 dB Range
(All Boost or Cut)
LMC835 Gain vs Frequency
@
g
6 dB Range
(1 kHz Boost or Cut)
TL/H/6753– 13
FIGURE 9. 12-Band Equalizer
10
TL/H/6753– 14
Page 11
Typical Applications (Continued)
TABLE II. Tuned Circuit Elements
e
Q
4.7, Q
0
fo(Hz) Co(F) CL(F) RL(X)Ro(X)
Z1 16 3.3m 0.47m 100k 680
Z2 31.5 15m 0.22m 110k 680
Z3 63 1m 0.1m 100k 680
Z4 125 0.39m 0.068m 91k 680
Z5 250 0.22m 0.033m 82k 680
Z6 500 0.1m 0.015m 100k 680
Z7 1k 0.047m 0.01m 82k 680
Z8 2k 0.022m 0.0047m 91k 680
Z9 4k 0.01m 0.0022m 110k 680
Z10 8k 0.0068m 0.001m 82k 680
Z11 16k 0.0033m 680p 62k 680
Z12 32k 0.0015m 470p 68k 510
e
1.4
12 dB
Performance Characteristics (Circuit of Figure 9)
e
L
CLRLR
0
1
e
f
0
2q0L0C
L
e
Q
0
C0R
0
e
Q
12 dB
R
FIGURE 10. Tuned Circuit for
12-Band Equalizer (
Figure 9
0
0
0
2
0
R0Q
0
a
1590
0
TL/H/6753– 15
)
12 Band Equalizer Application
LMC835 Gain vs Frequency
@
g
6 dB Range
(All Boost or Cut)
12 Band Equalizer Application
LMC835 Gain vs Frequency
@
g
12 dB Range
(All Boost or Cut)
LMC835 12 Band E.Q. Application
Gain vs Frequency
@
g
12 dB Range
(1 kHz Boost or Cut)
LMC835 12 Band E.Q. Application
Gain vs Frequency
@
g
6dB Range
(1 kHz Boost or Cut)
TL/H/6753– 16
11
Page 12
Typical Applications (Continued)
TL/H/6753– 25
L
F
Q
Q
o
o
O
12 dB
e
e
CL,RL,R
2q0LOC
e
COR
0
e
O
1
O
2
O
ROQ
O
a
R
15§C
O
a
V
The
output is used to bias the gyrators
2
FIGURE 11. Single Supply Stereo Equalizer
12
TL/H/6753– 17
Page 13
Typical Applications (Continued)
FIGURE 12. Stereo 7-Input/1-Output Mixers
TL/H/6753– 18
(THD is not as low as equalizer circuit)
FIGURE 14. LMC835-COP404L CPU Interface
FIGURE 13. Stereo Volume Control, Very Low THD
TL/H/6753– 19
TL/H/6753– 20
13
Page 14
Typical Applications (Continued)
Sample Subroutine Program for
HEX
CODE LABEL MNEMONICS COMMENTS
3F LMC835: LBI 3F ;POINT TO RAMADDRESS 3F
05 SEND LD ;RAMDATA TO A
22 SC ; SET CARRY
335F OGI ;SET PORT G4 1111, OPEN THE AND GATES
4F XAS ;SWAP A AND SIO, CLOCK START
05 LD ;RAMDATA TO A, MAKE SURE A 4 DATA
07 XDS ;SWAP A AND RAMDATA, RAMADDRESS4RAMADDRESS11
05 LD ;RAMDATA TO A
4F XAS ;SWAP A AND SIO
05 LD ;RAMDATA TO A, MAKE SURE A4NEWDATA
07 XDS ;SWAP A AND RAMDATA, RAMADDRESS4RAMADDRESS11
32 RC ;RESET CARRY
4F XAS ;SWAP A AND SIO, CLOCK STOP
335D OGJ 13 ;SET PORT G41101, MAKE STROBE LOW
335B OGI 11 ;SET PORT G41011, MAKE STROBE HIGH, CLOSE THE
4E CBA ;BD TO A
43 AISC 3 ;RAMADDRESS
48 RET
80 JP SEND
RAM
ADDRESS COMMENTS
3C DATA ;GAIN DATA D41D7
3D DATA ;GAIN DATA D01D3
3E DATA ;BAND DATA D41D7
3F DATA ;BAND DATA D01D3
Figure 14
, LMC835-COP404L CPU Interface
k
3C THEN RETURN
GATES
Application Hints
SWITCHING NOISE
The LMC835 uses CMOS analog switches that have small
leakages (less than 50 nA). When a band is selected for flat
gain, all the switches in that band are open and the resonator circuit is not connected to the LMC835 resistor network.
It is only in the flat mode that the small leakage currents can
cause problems. The input to the resonator circuit is usually
a capacitor and the leakage currents will slowly charge up
this capacitor to a large voltage if there is no resistive path
to limit it. When the band is set to any value other than flat,
the charge on the capacitor will be discharged by the resistor network and there will be a transient at the output. To
limit the size of this transient, R
HOW TO AVOID SWITCHING NOISE DUE TO LEAKAGE
CURRENT (Refer to
To avoid switching noise due to leakage currents when
changing the gain, it is recommended to put R
kX between Pin 3 and Pin 5Ð11 each, Pin 26 and Pin 12Ð
24 each. The resistor limits the voltage that the capacitor
can charge to, with minimal effects on the equalization. The
frequency response change due to R
ure 15
. The gain error is only 0.2 dB and Q error is only 5%
at 12 dB boost or cut.
Figures 7
LEAK
and8)
is necessary.
are shown in
LEAK
LEAK
e
100
Fig-
SIMPLE WORD GENERATOR
Circuit operation revolves around an MM74HC165 parallelin/serial-out shift register. Data bits D0 through D7 are applied to the parallel of the MM74HC165 from 8 toggle
switches. The bits are shifted out to the DATA input of the
LMC835 in sync with the clock. When all data bits have
been loaded, CLOCK is inhibited and a STROBE pulse is
generated: this sequence is initiated by a START pulse.
LMC835-COP404L CPU INTERFACE (Refer to
The diagram shows AND gates between the COP and the
LMC835. These permit G2 to inhibit the CLOCK and DATA
lines (SK and SO) during a STROBE (G1) pulse. This function may also be implemented in software. As shown in
ure 2
, the data groups are shifted in D0 first. Data is loaded
on positive clock edges.
POWER SUPPLIES
These applications show LM317/337 regulators for the
g
7.5V supplies for the LMC835. Since the latter draws only
5 mA max., 1k series dropping resistors from the
amp supply and a pair of 7.5V zeners and bypass caps will
also suffice.
14
(Figure 6)
Figure 14
g
15V op
)
Fig-
Page 15
Application Hints (Continued)
MODEL
RESULT
TL/H/6753– 21
FIGURE 15. Effect of R
REDUCING EXTERNAL COMPONENTS
The typical application shown in
free. The DC-coupled circuit in
Figure 7
Figure 16
is switching noise
is also switching
noise free, except at 12 dB/6 dB switch turn ON/OFF. This
switching noise is caused by the I
bias
and V
offset
of the op
AC COUPLING
TL/H/6753– 23
FIGURE 16. Reducing External Components
TL/H/6753– 22
LEAK
amps. Selecting a low I
the switching noise due to the 12 dB/6 dB switch. The DCcoupled application can also eliminate the R
tors with only a 0.5 dB gain error at 12 dB boost or cut.
bias
and V
op amp can minimize
offset
e
F
100k resis-
DC COUPLING
TL/H/6753– 24
15
Page 16
16
Page 17
Physical Dimensions inches (millimeters)
Order Number LMC835N
NS Package N28B
17
Page 18
Physical Dimensions inches (millimeters) (Continued)
LMC835 Digital Controlled Graphic Equalizer
Order Number LMC835V
NS Package V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor
Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd.
2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16
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Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne
TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999
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