Datasheet LMC6492, LMC6494 Specification

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Page 1



RES11A40-Q1

REF



–





IN

IN+

OUT

LMC649x

SNOS724F – AUGUST 2000 – REVISED FEBRUARY 2024

LMC649x Dual and Quad, CMOS, Rail-to-Rail Input/Output Operational Amplifiers

LMC6492, LMC6494

1 Features

• Rail-to-rail input common-mode voltage range, specified over temperature

• Rail-to-rail output swing within 100mV of supply rail, 2kΩ load

• Can operate on standard 5V and 15V supplies

• Excellent CMRR and PSRR: 82dB

• Ultra-low input current: 150fA

• Low supply current (at VS = 5V): 500μA/amplifier

• Low offset voltage drift: 1.0μV/°C

2 Applications

• Automotive transducer amplifier

• Pressure sensor

• Oxygen sensor

• Temperature sensor

• Speed sensor

3 Description

The LMC6492 and LMC6494 (LMC649x) amplifiers were specifically developed for single-supply applications that operate from −40°C to +125°C. This feature is an excellent choice for automotive systems because of the wide temperature range. A unique design topology enables the LMC649x common-mode voltage range to accommodate input signals beyond the rails. This eliminates non-linear output errors due to input signals exceeding a traditionally limited common-mode voltage range. The LMC649x signal range has a high CMRR of 82dB for excellent accuracy in noninverting circuit configurations.

The LMC649x rail-to-rail input is complemented by rail-to-rail output swing. This configuration provides maximum dynamic signal range and is particularly important in 5V systems.

An ultra-low input current of 150fA and a 120dB openloop gain provide high accuracy and direct interfacing with high-impedance sources.

Device Information

PART NUMBER CHANNEL COUNT PACKAGE

LMC6492 Dual D (SOIC, 8) LMC6494 Quad D (SOIC, 14)

(1)

(1) For more information, see Section 9.

Two-Op-Amp Instrumentation Amplifier Using the RES11A-Q1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Page 2

1OUT A 8 V+

2±IN A 7 OUT B

3+IN A 6 ±IN B

4V± 5 +IN B

Not to scale

LMC6492, LMC6494

SNOS724F – AUGUST 2000 – REVISED FEBRUARY 2024

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1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Pin Configuration and Functions...................................2

5 Specifications.................................................................. 4

5.1 Absolute Maximum Ratings........................................ 4

5.2 ESD Ratings............................................................... 4

5.3 Recommended Operating Conditions.........................4

5.4 Thermal Information....................................................4

5.5 Electrical Characteristics.............................................5

5.6 Typical Characteristics................................................8

6 Application and Implementation..................................14

4 Pin Configuration and Functions

Figure 4-1. LMC6492: D Package, 8-Pin SOIC (Top View)

6.1 Application Information............................................. 14

6.2 Typical Application....................................................17

6.3 Layout....................................................................... 19

7 Device and Documentation Support............................21

7.1 Device Support......................................................... 21

7.2 Receiving Notification of Documentation Updates....22

7.3 Support Resources................................................... 22

7.4 Electrostatic Discharge Caution................................22

7.5 Glossary....................................................................22

8 Revision History............................................................ 22

9 Mechanical, Packaging, and Orderable Information..23

Table 4-1. Pin Functions: LMC6492

NO. NAME

1 OUT A Output Output for amplifier A 2 −IN A Input Inverting input for amplifier A 3 +IN A Input Noninverting input for amplifier A 4 V– Power Negative supply voltage input 5 +IN B Input Noninverting input for amplifier B 6 −IN B Input Inverting input for amplifier B 7 OUT B Output Output for amplifier B 8 V+ Power Positive supply voltage input

TYPE DESCRIPTION

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1OUT A 14 OUT D

2±IN A 13 ±IN D

3+IN A 12 +IN D

4V+ 11 V±

5+IN B 10 +IN C

6±IN B 9 ±IN C

7OUT B 8 OUT C

Not to scale

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Figure 4-2. LMC6494: D Package, 14-Pin SOIC (Top View)

Table 4-2. Pin Functions: LMC6494

NO. NAME

1 OUT A Output Output for amplifier A 2 −IN A Input Inverting input for amplifier A 3 +IN A Input Noninverting input for amplifier A 4 V+ Power Positive supply voltage input 5 +IN B Input Noninverting input for amplifier B 6 −IN B Input Inverting input for amplifier B 7 OUT B Output Output for amplifier B 8 OUT C Output Output for amplifier C 9 −IN C Input Inverting input for amplifier C 10 +IN C Input Noninverting input for amplifier C 11 V– Power Negative supply voltage input 12 +IN C Input Inverting input for amplifier D 13 +IN C Input Noninverting input for amplifier D 14 OUT C Output Output for amplifier D

TYPE DESCRIPTION

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted

Differential input voltage ±Supply Voltage Voltage at input/output pin (V–) – 0.3 (V+) + 0.3 V

T T

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

(2) If military- or aerospace-specified devices are required, please contact the TI Sales Office or Distributors for availability and

(3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result

(4) The maximum power dissipation is a function of T

Supply voltage, VS = (V+) – (V–) 16 V

Current at input pin –5 5 mA Current at output pin

(3)

Current at power supply pin 40 mA Lead temperature (soldering, 10 sec) 260 °C Storage temperature –65 150 °C

STG

Junction temperature

(4)

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

specifications.

in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over a long term can adversely affect reliability.

, R

J(max)

temperature is PD = (T

− TA) / θJA. All numbers apply for packages soldered directly into a printed circuit board (PCB).

J(max)

θJA

(1) (2)

MIN MAX UNIT

–30 30 mA

150 °C

, and TA. The maximum allowable power dissipation at any ambient

5.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

±2000 V

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage, VS = (V+) – (V–) 2.5 15.5 V Junction temperature –40 125 ℃

5.4 Thermal Information

LMC6492 LMC6494

(1)

8 PINS 14 PINS

θJA

θJC(top)

θJB

θJC(bot)

THERMAL METRIC

Junction-to-ambient thermal resistance 128.9 83.0 ºC/W Junction-to-case(top) thermal resistance 68.6 42.7 ºC/W Junction-to-board thermal resistance 72.4 42.4 ºC/W Junction-to-top characterization parameter 19.7 7.0 ºC/W Junction-to-board characterization parameter 71.6 42.0 ºC/W Junction-to-case(bottom) thermal resistance N/A N/A ºC/W

UNITD (SOIC) D (SOIC)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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5.5 Electrical Characteristics

at TJ = +25°C, V+ = 5V, V– = 0V, VCM = V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DC SPECS

LMC649xAE

dVOS/dT

CMRR

+PSRR

–PSRR

Input offset voltage

LMC649xBE

Input offset voltage drift

Input bias current

Input offset current

TA = –40°C to +125°C ±1 µV/°C

TA = –40°C to +125°C ±200

TA = –40°C to +125°C ±100

Common-mode input capacitance

Input resistance >10 TΩ

LMC649xAE 0V ≤ VCM ≤ 15V, V+ = 15V

LMC649xBE

Common-mode rejection ratio

0V ≤ VCM ≤ 15V, V+ = 15V

LMC649xAE 0V ≤ VCM ≤ 5V, V+ = 5V

LMC649xBE 0V ≤ VCM ≤ 5V, V+ = 5V

LMC649xAE 5V ≤ V+ ≤ 15V, V– = 0V,

Positive powersupply rejection ratio

VO = 2.5V LMC649xBE

5V ≤ V+ ≤ 15V, V– = 0V, VO = 2.5V

LMC649xAE –5V ≤ V– ≤ –15V, V+ = 0V,

Negative powersupply rejection ratio

VO = –2.5V LMC649xBE

–5V ≤ V– ≤ –15V, V+ = 0V, VO = –2.5V

Input common-mode voltage

Large-signal voltage gain

V+ = 5V and 15V, for CMRR ≥ 50dB

Sourcing, RL = 2kΩ to 7.5V, V+ = 15V, 7.5V ≤ VO ≤ 11.5V 300 Sinking, RL = 2kΩ to 7.5V, V+ = 15V, 3.5V ≤ VO ≤ 7.5V 40

SNOS724F – AUGUST 2000 – REVISED FEBRUARY 2024

= V+ / 2, and RL > 1MΩ (unless otherwise noted)

OUT

TA = –40°C to +125°C ±3.8

TA = –40°C to +125°C ±6.8

TA = –40°C to +125°C 60

TA = –40°C to +125°C 58

TA = –40°C to +125°C 60

TA = –40°C to +125°C 58

TA = –40°C to +125°C 60

TA = –40°C to +125°C 58

TA = –40°C to +125°C 60

TA = –40°C to +125°C 58

Low (V–) – 0.3 –0.25 Low, TA = –40°C to +125°C 0

High

High, TA = –40°C to +125°C V+

65 82

63 82

65 82

63 82

65 82

63 82

65 82

63 82

(V+) +

(V+) + 0.3

0.25

LMC6492, LMC6494

±0.11 ±3

±0.11 ±6

±0.15

±0.075

3 pF

V/mV

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5.5 Electrical Characteristics (continued)

at TJ = +25°C, V+ = 5V, V– = 0V, VCM = V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V+ = 5V, RL = 2kΩ to V+ / 2

V+ = 5V, RL = 600Ω to V+ / 2

Voltage output swing

V+ = 15V, RL = 2kΩ to V+ / 2

V+ = 15V, RL = 600Ω to V+ / 2

V+ = 5V, sourcing, VO = 0V

V+ = 5V, sinking, VO = 5V Output short-circuit current

V+ = 15V, sourcing, VO = 0V

V+ = 15V, sinking, VO = 5V

Per amplifier, V+ = 5V,

VO = V+ / 2 Supply current

Per amplifier, V+ = 15V,

VO = V+ / 2

= V+ / 2, and RL > 1MΩ (unless otherwise noted)

OUT

Swing high 4.8 4.9 Swing high,

TA = –40°C to +125°C

4.7

Swing low 0.1 0.18 Swing low,

TA = –40°C to +125°C Swing high 4.5 4.7 Swing high,

TA = –40°C to +125°C

4.24

Swing low 0.3 0.5 Swing low,

TA = –40°C to +125°C Swing high 14.4 14.7 Swing high,

TA = –40°C to +125°C

14.0

Swing low 0.16 0.35 Swing low,

TA = –40°C to +125°C Swing high 13.4 14.1 Swing high,

TA = –40°C to +125°C

Swing low 0.5 1.0 Swing low,

TA = –40°C to +125°C

16 25

TA = –40°C to +125°C 10

11 22

TA = –40°C to +125°C 8

28 30

TA = –40°C to +125°C 20

(1)

30 30

TA = –40°C to +125°C 22

TA = –40°C to +125°C 1.05

0.65 0.975

TA = –40°C to +125°C 1.15

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0.24

0.65 V

0.5

1.5

0.5 0.875

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5.5 Electrical Characteristics (continued)

LMC6492, LMC6494

at TJ = +25°C, V+ = 5V, V– = 0V, VCM = V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AC SPECS

SR Slew rate

(2)

GBW Gain bandwidth V+ = 15V 1.5 MHz Θ

Phase margin 50 Deg Gain margin 15 dB

Amp-to-amp isolation

THD

Input-referred voltage noise

Input current noise density

Total harmonic distortion

(1) Do not short circuit output to V+ when V+ is greater than 13V or reliability is adversely affected. (2) Specification established from device population bench system measurements across multiple lots. Number specified is the slower of

either the positive or negative slew rates.

V+ = 15V, connected as voltage follower with 10V step

Input referred V+ = 15V, RL = 100kΩ to 7.5V, VO = 12VPP, f = 1kHz

f = 1kHz, VCM = 1V 37 nV/√Hz

f = 1kHz 0.06 pA/√Hz

f = 1kHz, AV = –2, RL = 10kΩ, VO = –4.1V f = 10kHz, AV = –2, RL = 10kΩ, VO = 8.5VPP, V+ = 10V 0.01

= V+ / 2, and RL > 1MΩ (unless otherwise noted)

OUT

TA = –40°C to +125°C 0.5

0.7 1.3

150 dB

0.01

V/µs

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5.6 Typical Characteristics

at VS = +15V, single supply, and TA = 25°C (unless otherwise specified)

Figure 5-1. Supply Current vs Supply Voltage Figure 5-2. Input Current vs Temperature

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Figure 5-3. Sourcing Current vs Output Voltage Figure 5-4. Sourcing Current vs Output Voltage

Figure 5-5. Sourcing Current vs Output Voltage Figure 5-6. Sinking Current vs Output Voltage

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5.6 Typical Characteristics (continued)

at VS = +15V, single supply, and TA = 25°C (unless otherwise specified)

Figure 5-7. Sinking Current vs Output Voltage Figure 5-8. Sinking Current vs Output Voltage

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LMC6492, LMC6494

Figure 5-9. Output Voltage Swing vs Supply Voltage Figure 5-10. Input Voltage Noise vs Frequency

Figure 5-11. Crosstalk Rejection vs Frequency Figure 5-12. Crosstalk Rejection vs Frequency

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5.6 Typical Characteristics (continued)

at VS = +15V, single supply, and TA = 25°C (unless otherwise specified)

Figure 5-13. Positive PSRR vs Frequency Figure 5-14. Negative PSRR vs Frequency

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Figure 5-15. CMRR vs Frequency Figure 5-16. Input Voltage vs Output Voltage

Figure 5-17. Input Voltage vs Output Voltage Figure 5-18. Open Loop Frequency Response

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5.6 Typical Characteristics (continued)

at VS = +15V, single supply, and TA = 25°C (unless otherwise specified)

Figure 5-19. Open Loop Frequency Response Figure 5-20. Open Loop Frequency Response vs Temperature

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Figure 5-21. Maximum Output Swing vs Frequency Figure 5-22. Gain and Phase vs Capacitive Load

Figure 5-23. Gain and Phase vs Capacitive Load Figure 5-24. Slew Rate vs Supply Voltage

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5.6 Typical Characteristics (continued)

at VS = +15V, single supply, and TA = 25°C (unless otherwise specified)

Figure 5-25. Non-Inverting Large Signal Pulse Response Figure 5-26. Non-Inverting Large Signal Pulse Response

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Figure 5-27. Non-Inverting Large Signal Pulse Response Figure 5-28. Non-Inverting Small Signal Pulse Response

Figure 5-29. Non-Inverting Small Signal Pulse Response Figure 5-30. Non-Inverting Small Signal Pulse Response

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5.6 Typical Characteristics (continued)

at VS = +15V, single supply, and TA = 25°C (unless otherwise specified)

Figure 5-31. Inverting Large Signal Pulse Response Figure 5-32. Inverting Large Signal Pulse Response

LMC6492, LMC6494

Figure 5-33. Inverting Large Signal Pulse Response Figure 5-34. Inverting Small Signal Pulse Response

Figure 5-35. Inverting Small Signal Pulse Response Figure 5-36. Inverting Small Signal Pulse Response

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6 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

6.1 Application Information

6.1.1 Input Common-Mode Voltage Range

Unlike Bi-FET amplifier designs, the LMC649x does not exhibit phase inversion when an input voltage exceeds the negative supply voltage. Figure 6-1 shows an input voltage exceeding both supplies with no resulting phase inversion on the output.

Figure 6-1. Input Voltage Signal Exceeds the

LMC649x Power Supply Voltages With

No Output Phase Inversion

The LMC649x is a true rail-to-rail input operational amplifier with an input common-mode range that extends beyond either supply rail. When the input common-mode voltage swings to about 3V from the positive rail, some dc specifications, namely offset voltage, can be slightly degraded. Figure 6-2 illustrates the input offset behavior across the entire common-mode range.

Figure 6-2. Input Offset Voltage vs Common-Mode Voltage

The absolute maximum input voltage is 300mV beyond either supply rail at room temperature. Voltages greatly exceeding this absolute maximum rating, as in Figure 6-3, can cause excessive current to flow in or out of the input pins possibly affecting reliability.

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Figure 6-3. A ±7.5V Input Signal Greatly Exceeds the 5V Supply in Figure 6-3, Causing No Phase

Inversion Due to R

Applications that exceed this rating must externally limit the maximum input current to ±5mA with an input resistor (RI) as shown in Figure 6-4.

Figure 6-4. RI Input Current Protection for

Voltages Exceeding the Supply Voltages

6.1.2 Rail-to-Rail Output

The LMC649x output can swing to within a few hundred millivolts of either supply voltage. Using the specified output swing specifications, an approximate output resistance can be calculated for different sourcing and sinking conditions. Using the calculated output resistance, the maximum output voltage swing can be estimated as a function of load.

6.1.3 Compensating for Input Capacitance

Large values of feedback resistance are commonly used for amplifiers with ultra-low input current, such as the LMC649x.

Although the LMC649x is highly stable over a wide range of operating conditions, make sure that certain precautions are met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors with even small values of input capacitance (due to transducers, photodiodes, and circuit board parasitics) reduce phase margins.

When high input impedances are demanded, guarding of the LMC649x is suggested. Guarding input lines not only reduces leakage, but also lowers stray input capacitance. See Printed-Circuit-Board Layout for High

Impedance Work.

The effect of input capacitance can be compensated by adding a capacitor, Cf, around the feedback resistors (as in Figure 6-1 ) so that:

(1)

R1 CIN ≤ R2 C

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(2)

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Frequency (Hz)

Open-Loop Output Impedence ()

200

400

600

800

1000

1k 10k 100k 1M

VS= 5 V, VCM= 2.5 V VS= 15 V, VCM= 7.5 V

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The exact value of CIN is difficult to know; therefore, Cf can be experimentally adjusted so that the desired pulse response is achieved. See the LMC660 and LMC662 for a more detailed discussion on compensating for input capacitance.

Figure 6-5. Canceling the Effect of Input Capacitance

6.1.4 Capacitive Load Tolerance

All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor is normally included in this integrator stage. The frequency location of the dominant pole is affected by the resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate resistive load in parallel with the capacitive load (see Typical Curves).

Direct capacitive loading reduces the phase margin of many op amps. A pole in the feedback loop is created by the combination of the op amp output impedance and the capacitive load. The open-loop output impedance of the LMC649x is shown in Figure 6-6. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 6-7.

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Figure 6-7. LMC649x Noninverting Amplifier, Compensated to Handle Capacitive Loads

Figure 6-6. LMC649x Open-Loop Ouput Impedance

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6.2 Typical Application

6.2.1 Application Circuits

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LMC6492, LMC6494

Where: V0 = V1 + V2 − V3 – V (V1 + V2 ≥ (V3 + V4) to keep V0 > 0V

Figure 6-8. DC Summing Amplifier (VIN ≥ 0VDC and VO ≥ V

For

(CMRR depends on this resistor ratio match)

As shown: VO = 2(V2 − V1)

Figure 6-9. High Input Z, DC Differential Amplifier

Figure 6-10. Photo Voltaic-Cell Amplifier

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If R1 = R5, R3 = R6, and R4 = R7; then

∴AV ≈ 100 for circuit shown (R2 = 9.3k).

Figure 6-11. Instrumentation Amplifier

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Figure 6-12. Rail-to-Rail Single Supply Low Pass Filter

This low-pass filter circuit can be used as an antialiasing filter with the same supply as the ADC. Filter designs can also take advantage of the LMC649x ultra-low input current. The ultra-low input current yields negligible offset error even when large value resistors are used. This configuration in turn allows the use of smaller-valued capacitors that take up less board space and cost less.

Figure 6-13. Low Voltage Peak Detector with Rail-to-Rail Peak Capture Range

Dielectric absorption and leakage is minimized by using a polystyrene or polypropylene hold capacitor. The droop rate is primarily determined by the value of C

and diode leakage current. Select low-leakage current

HOLD

diodes to minimize drooping.

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Rf = Rx Rf >> R1, R2, R3, and R4

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Figure 6-14. Pressure Sensor

In a manifold absolute pressure sensor application, a strain gauge is mounted on the intake manifold in the engine unit. Manifold pressure causes the sensing resistors, R1, R2, R3 and R4 to change. The resistors change in a way such that R2 and R4 increase by the same amount R1 and R3 decrease. This causes a differential voltage between the input of the amplifier. The gain of the amplifier is adjusted by Rf.

6.3 Layout

6.3.1 Layout Guidelines

6.3.1.1 Printed Circuit Board Layout For High-Impedance Work

Any circuit that operates with less than 1000pA of leakage current requires special layout of the printed circuit board (PCB). To take advantage of the ultra-low bias current of the LMC649x, typically 150fA, an excellent layout is required. Fortunately, the techniques to obtain low leakages are quite simple. First, do not ignore the surface leakage of the PCB. Even though this leakage can sometimes appear acceptably low, under conditions of high humidity or dust or contamination, the surface leakage is appreciable.

To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC649x inputs and the terminals of components connected to the op amp inputs, as in Figure 6-15. To have a significant effect, place guard rings on both the top and bottom of the PCB. This printed circuit foil must then be connected to a voltage that is at the same voltage as the amplifier inputs because no leakage current can flow between two points at the same potential.

For example, a PCB trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, can leak 5pA if the trace is a 5V bus adjacent to the pad of the input. This causes a 33 times degradation from the LMC649x actual performance. If a guard ring is used and held within 5mV of the inputs, then the same resistance of 1011Ω only causes 0.05pA of leakage current. Figure 6-15 to Figure 6-17 show typical connections of guard rings for standard op-amp configurations.

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Figure 6-15. Examples of Guard Ring in PCB Layout

Figure 6-16. Inverting Amplifier

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Figure 6-17. Noninverting Amplifier

Figure 6-18. Follower

Be aware that when laying out a PCB for the sake of just a few circuits is inappropriate, the following technique is even better than a guard ring on a PCB. Do not insert the amplifier input pin into the board at all; instead, bend the input pin up in the air and use only air as an insulator because air is an excellent insulator. In this case, some of the advantages of PCB construction are lost, but the advantages of air are sometimes well worth the effort of using point-to-point up-in-the-air wiring. Figure 6-19 shows an example of air wiring.

Input pins are lifted out of PCB and soldered directly to components. All other pins connected to the PCB.

Figure 6-19. Air Wiring

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7 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

7.1 Device Support

7.1.1 Development Support

7.1.1.1 Spice Macromodel

A spice macromodel is available for the LMC649x. This model includes accurate simulation of:

• Input common-model voltage range

• Frequency and transient response

• GBW dependence on loading conditions

• Quiescent and dynamic supply current

• Output swing dependence on loading conditions and many other characteristics as listed on the macromodel disk. Contact your local Texas Instruments sales office to obtain an operational amplifier spice model library disk.

7.1.1.2 PSpice® for TI

PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create

subsystem designs and prototype solutions before committing to layout and fabrication, reducing development cost and time to market.

7.1.1.3 TINA-TI™ Simulation Software (Free Download)

TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.

Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

Note

These files require that either the TINA software or TINA-TI software be installed. Download the free TINA-TI simulation software from the TINA-TI™ software folder.

7.1.1.4 DIP-Adapter-EVM

Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and inexpensive way to interface with small, surface-mount devices. Connect any supported op amp using the included Samtec terminal strips or wire them directly to existing circuits. The DIP-Adapter-EVM kit supports the following industry-standard packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT-23-6, SOT-23-5 and SOT-23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6).

7.1.1.5 DIYAMP-EVM

The DIYAMP-EVM is a unique evaluation module (EVM) that provides real-world amplifier circuits, enabling the user to quickly evaluate design concepts and verify simulations. This EVM is available in three industry-standard packages (SC70, SOT23, and SOIC) and 12 popular amplifier configurations, including amplifiers, filters, stability compensation, and comparator configurations for both single and dual supplies.

Product Folder Links: LMC6492 LMC6494

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Page 22

LMC6492, LMC6494

SNOS724F – AUGUST 2000 – REVISED FEBRUARY 2024

www.ti.com

7.1.1.6 TI Reference Designs

TI reference designs are analog solutions created by TI’s precision analog applications experts. TI reference designs offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI reference designs are available online at

https://www.ti.com/reference-designs.

7.1.1.7 Filter Design Tool

The filter design tool is a simple, powerful, and easy-to-use active filter design program. The filter design tool allows the user to create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.

Available as a web-based tool from the Design tools and simulation web page, the filter design tool allows the user to design, optimize, and simulate complete multistage active filter solutions within minutes.

7.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

7.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

Trademarks

TINA-TI™ and TI E2E™ are trademarks of Texas Instruments. TINA™ is a trademark of DesignSoft, Inc. PSpice® is a registered trademark of Cadence Design Systems, Inc. All trademarks are the property of their respective owners.

7.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

7.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

8 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (November 2023) to Revision F (February 2024) Page

• Added data to Thermal Information ...................................................................................................................4

• Updated footnote (2) to detail how slew rate minimum value is specified in Electrical Characteristics .............5

22 Submit Document Feedback

Product Folder Links: LMC6492 LMC6494

Page 23

www.ti.com

SNOS724F – AUGUST 2000 – REVISED FEBRUARY 2024

LMC6492, LMC6494

Changes from Revision D (March 2013) to Revision E (November 2023) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1

• Added the Pin Configuration and Functions, Specifications, ESD Ratings, Thermal Information, Application

and Implementation, Application Information, Typical Applications, Layout, Layout Guidelines, Device and

Documentation Support, and Mechanical, Packaging, and Orderable Information sections..............................1

• Updated Features ..............................................................................................................................................1

• Deleted P (PDIP) packages from data sheet......................................................................................................1

• Updated application circuit in Description ..........................................................................................................1

• Moved ESD tolerance value from Absolute Maximum Ratings to ESD Ratings ............................................... 4

• Updated note 1 of Absolute Maximum Ratings ................................................................................................. 4

• Changed Operating Conditions to Recommended Operating Conditions and deleted redundant table note.... 4

• Moved thermal information values from Operating Conditions to Thermal Information .................................... 4

• Updated format of Electrical Characteristics ..................................................................................................... 5

• Deleted table notes 1, 2, and 3 from Electrical Characteristics to be consistent with standard TI data sheets..5

• Added ± to input offset voltage, input offset voltage drift, input bias current, and input offset current in

Electrical Characteristics ................................................................................................................................... 5

• Updated parameter names to be consistent with modern data sheets.............................................................. 5

• Moved the AC Electrical Characteristics and DC Electrical Characteristics to Electrical Characteristics ........ 5

• Changed supply current specification from total to per amplifier in Electrical Characteristics ...........................5

• Deleted Figures 13 to 15, Figures 21 to 25, Figures 34 to 35, and Figures 51 to 54......................................... 8

• Added Input Offset Voltage vs Common-Mode Voltage plot in Amplifier Topology and related description ....14

• Updated description of Rail-to-Rail Output ......................................................................................................15

Changes from Revision C (March 2013) to Revision D (March 2013) Page

• Changed layout of National Data Sheet to TI format........................................................................................21

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LMC6492 LMC6494

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Page 24

PACKAGE OPTION ADDENDUM

www.ti.com

19-Jun-2024

PACKAGING INFORMATION

Orderable Device Status

LMC6492AEMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LMC64

LMC6492BEM/NOPB LIFEBUY SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC64

LMC6492BEMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LMC64

LMC6494AEMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC6494

LMC6494BEMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC6494

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

92AEM

92BEM

AEM

BEM

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Samples

Addendum-Page 1

Page 25

PACKAGE OPTION ADDENDUM

www.ti.com

19-Jun-2024

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

Page 26

PACKAGE MATERIALS INFORMATION

Reel Width (W1)

REEL DIMENSIONS

A0 B0 K0

Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1Q2 Q2

Q3 Q3Q4 Q4

User Direction of Feed

Reel

Diameter

www.ti.com 30-Apr-2024

TAPE AND REEL INFORMATION

*All dimensions are nominal

LMC6492AEMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6492BEMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6494AEMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMC6494BEMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1

Device Package

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 27

PACKAGE MATERIALS INFORMATION

TAPE AND REEL BOX DIMENSIONS

Width (mm)

www.ti.com 30-Apr-2024

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMC6492AEMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6492BEMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6494AEMX/NOPB SOIC D 14 2500 356.0 356.0 35.0 LMC6494BEMX/NOPB SOIC D 14 2500 356.0 356.0 35.0

Pack Materials-Page 2

Page 28

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Apr-2024

TUBE

T - Tube

height

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

LMC6492BEM/NOPB D SOIC 8 95 495 8 4064 3.05

L - Tube length

Pack Materials-Page 3

Page 29

Page 30

PACKAGE OUTLINE

.189-.197 [4.81-5.00]

NOTE 3

.228-.244 TYP [5.80-6.19]

B .150-.157

[3.81-3.98]

PIN 1 ID AREA

NOTE 4

SCALE 2.800

6X .050

[1.27]

.150 [3.81]

8X .012-.020 [0.31-0.51]

.010 [0.25] C A B

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.004 [0.1] C

4X (0 -15 )

.069 MAX

[1.75]

.005-.010 TYP [0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010 [0.25]

0 - 8

.016-.050 [0.41-1.27]

(.041) [1.04]

DETAIL A

TYPICAL

.004-.010 [0.11-0.25]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

Page 31

8X (.061 )

8X (.024)

6X (.050 )

[1.27]

[0.6]

[1.55]

SYMM

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

EXAMPLE BOARD LAYOUT

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

SEE DETAILS

SYMM

(R.002 ) TYP

[0.05]

EXPOSED

METAL

NON SOLDER MASK

SOLDER MASK OPENING

.0028 MAX [0.07] ALL AROUND

DEFINED

SOLDER MASK

OPENING

EXPOSED

METAL

.0028 MIN [0.07] ALL AROUND

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL UNDER SOLDER MASK

4214825/C 02/2019

www.ti.com

Page 32

8X (.061 )

8X (.024)

[0.6]

6X (.050 )

[1.27]

[1.55]

EXAMPLE STENCIL DESIGN

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

SYMM

(R.002 ) TYP

(.213)

[5.4]

[0.05]

BASED ON .005 INCH [0.125 MM] THICK STENCIL

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SCALE:8X

4214825/C 02/2019

SOLDER PASTE EXAMPLE

www.ti.com

Page 33

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Datasheet LMC6492, LMC6494 Specification

1 Features

2 Applications

3 Description

Table of Contents

4 Pin Configuration and Functions

5 Specifications

5.1 Absolute Maximum Ratings

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Thermal Information

5.5 Electrical Characteristics

5.6 Typical Characteristics

6 Application and Implementation

6.1 Application Information

6.1.1 Input Common-Mode Voltage Range

6.1.2 Rail-to-Rail Output

6.1.3 Compensating for Input Capacitance

6.1.4 Capacitive Load Tolerance

6.2 Typical Application

6.2.1 Application Circuits

6.3 Layout

6.3.1 Layout Guidelines

6.3.1.1 Printed Circuit Board Layout For High-Impedance Work

7 Device and Documentation Support

7.1 Device Support

7.1.1 Development Support

7.1.1.1 Spice Macromodel

7.1.1.2 PSpice® for TI

7.1.1.3 TINA-TI™ Simulation Software (Free Download)

7.1.1.4 DIP-Adapter-EVM

7.1.1.5 DIYAMP-EVM

7.1.1.6 TI Reference Designs

7.1.1.7 Filter Design Tool

7.2 Receiving Notification of Documentation Updates

7.3 Support Resources

Trademarks

7.4 Electrostatic Discharge Caution

7.5 Glossary

8 Revision History

9 Mechanical, Packaging, and Orderable Information