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LMC6081
Precision CMOS Single Operational Amplifier
General Description
The LMC6081 is a precision low offset voltage operational
amplifier, capable of single supply operation. Performance
characteristics includeultra low input bias current, high voltage gain, rail-to-rail output swing, and an input common
mode voltage range that includes ground. These features,
plus its low offset voltage, make the LMC6081 ideally suited
for precision circuit applications.
Other applications using the LMC6081 include precision
full-wave rectifiers, integrators, references, and
sample-and-hold circuits.
This device is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
For designs with more critical power demands, see the
LMC6061 precision micropower operational amplifier.
For a dual orquad operational amplifier with similarfeatures,
see the LMC6082 or LMC6084 respectively.
PATENT PENDING
Features
(Typical unless otherwise stated)
n Low offset voltage: 150 µV
n Operates from 4.5V to 15V single supply
n Ultra low input bias current: 10 fA
n Output swing to within 20 mV of supply rail, 100k load
n Input common-mode range includes V
−
n High voltage gain: 130 dB
n Improved latchup immunity
Applications
n Instrumentation amplifier
n Photodiode and infrared detector preamplifier
n Transducer amplifiers
n Medical instrumentation
n D/A converter
n Charge amplifier for piezoelectric transducers
Connection Diagram
Ordering Information
Package Temperature Range NSC
Drawing
Transport
Media
Military Industrial
−55˚C to +125˚C −40˚C to +85˚C
8-Pin LMC6081AMN LMC6081AIN N08E Rail
Molded DIP LMC6081IN
8-Pin LMC6081AIM M08A Rail
Small Outline LMC6081IM Tape and Reel
8-Pin DIP/SO
DS011423-1
Top View
November 1994
LMC6081 Precision CMOS Single Operational Amplifier
© 1999 National Semiconductor Corporation DS011423 www.national.com
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the NationalSemiconductorSales Office/
Distributors for availability and specifications.
Differential Input Voltage
±
Supply Voltage
Voltage at Input/Output Pin (V
+
) +0.3V,
(V
−
) −0.3V
Supply Voltage (V
+−V−
) 16V
Output Short Circuit to V
+
(Note 10)
Output Short Circuit to V
−
(Note 2)
Lead Temperature
(Soldering, 10 Sec.) 260˚C
Storage Temp. Range −65˚C to +150˚C
Junction Temperature 150˚C
ESD Tolerance (Note 4) 2 kV
Current at Input Pin
±
10 mA
Current at Output Pin
±
30 mA
Current at Power Supply Pin 40 mA
Power Dissipation (Note 3)
Operating Ratings (Note 1)
Temperature Range
LMC6081AM −55˚C ≤ T
J
≤ +125˚C
LMC6081AI, LMC6081I −40˚C ≤ T
J
≤ +85˚C
Supply Voltage 4.5V ≤ V
+
≤ 15.5V
Thermal Resistance (θ
JA
), (Note 11)
N Package, 8-Pin Molded DIP 115˚C/W
M Package, 8-Pin Surface Mount 193˚C/W
Power Dissipation (Note 9)
DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
J
=
25˚C. Boldface limits apply at the temperature extremes. V
+
=
5V, V
−
=
0V, V
CM
=
1.5V, V
O
=
2.5V and R
L
>
1M unless otherwise specified.
Typ LMC6081AM LMC6081AI LMC6081I
Symbol Parameter Conditions (Note 5) Limit Limit Limit Units
(Note 6) (Note 6) (Note 6)
V
OS
Input Offset Voltage 150 350 350 800 µV
1000 800 1300 Max
TCV
OS
Input Offset Voltage 1.0 µV/˚C
Average Drift
I
B
Input Bias Current 0.010 pA
100 4 4 Max
I
OS
Input Offset Current 0.005 pA
100 2 2 Max
R
IN
Input Resistance
>
10 Tera Ω
CMRR Common Mode 0V ≤ V
CM
≤ 12.0V 85 75 75 66 dB
Rejection Ratio V
+
=
15V 72 72 63 Min
+PSRR Positive Power Supply 5V ≤ V
+
≤ 15V 85 75 75 66 dB
Rejection Ratio V
O
=
2.5V 72 72 63 Min
−PSRR Negative Power Supply 0V ≤ V
−
≤ −10V 94 84 84 74 dB
Rejection Ratio 81 81 71 Min
V
CM
Input Common-Mode V
+
=
5V and 15V −0.4 −0.1 −0.1 −0.1 V
Voltage Range for CMRR ≥ 60 dB 000Max
V
+
− 1.9 V+− 2.3 V+− 2.3 V+− 2.3 V
V
+
− 2.6 V+− 2.5 V+− 2.5 Min
A
V
Large Signal R
L
=
2kΩ Sourcing 1400 400 400 300 V/mV
Voltage Gain (Note 7) 300 300 200 Min
Sinking 350 180 180 90 V/mV
70 100 60 Min
R
L
=
600Ω Sourcing 1200 400 400 200 V/mV
(Note 7) 150 150 80 Min
Sinking 150 100 100 70 V/mV
35 50 35 Min
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DC Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for T
J
=
25˚C. Boldface limits apply at the temperature extremes. V
+
=
5V, V
−
=
0V, V
CM
=
1.5V, V
O
=
2.5V and R
L
>
1M unless otherwise specified.
Typ LMC6081AM LMC6081AI LMC6081I
Symbol Parameter Conditions (Note 5) Limit Limit Limit Units
(Note 6) (Note 6) (Note 6)
V
O
Output Swing V
+
=
5V 4.87 4.80 4.80 4.75 V
R
L
=
2kΩto 2.5V 4.70 4.73 4.67 Min
0.10 0.13 0.13 0.20 V
0.19 0.17 0.24 Max
V
+
=
5V 4.61 4.50 4.50 4.40 V
R
L
=
600Ω to 2.5V 4.24 4.31 4.21 Min
0.30 0.40 0.40 0.50 V
0.63 0.50 0.63 Max
V
+
=
15V 14.63 14.50 14.50 14.37 V
R
L
=
2kΩto 7.5V 14.30 14.34 14.25 Min
0.26 0.35 0.35 0.44 V
0.48 0.45 0.56 Max
V
+
=
15V 13.90 13.35 13.35 12.92 V
R
L
=
600Ω to 7.5V 12.80 12.86 12.44 Min
0.79 1.16 1.16 1.33 V
1.42 1.32 1.58 Max
I
O
Output Current Sourcing, V
O
=
0V 22 16 16 13 mA
V
+
=
5V 8108Min
Sinking, V
O
=
5V 21 16 16 13 mA
11 13 10 Min
I
O
Output Current Sourcing, V
O
=
0V 30 28 28 23 mA
V
+
=
15V 18 22 18 Min
Sinking, V
O
=
13V 34 28 28 23 mA
(Note 10) 19 22 18 Min
I
S
Supply Current V
+
=
+5V, V
O
=
1.5V 450 750 750 750 µA
900 900 900 Max
V
+
=
+15V, V
O
=
7.5V 550 850 850 850 µA
950 950 950 Max
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AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
J
=
25˚C, Boldface limits apply at the temperature extremes. V
+
=
5V, V
−
=
0V, V
CM
=
1.5V, V
O
=
2.5V and R
L
>
1M unless otherwise specified.
Typ LMC6081AM LMC6081AI LMC6081
Symbol Parameter Conditions (Note 5) Limit Limit Limit Units
(Note 6) (Note 6) (Note 6)
SR Slew Rate (Note 8) 1.5 0.8 0.8 0.8 V/µs
0.5 0.6 0.6 Min
GBW Gain-Bandwidth Product 1.3 MHz
φ
m
Phase Margin 50 Deg
e
n
Input-Referred
Voltage Noise
F=1 kHz 22
i
n
Input-Referred
Current Noise
F=1 kHz 0.0002
T.H.D. Total Harmonic Distortion F=10 kHz, A
V
=
−10
R
L
=
2kΩ,V
O
=
8V
PP
0.01
%
±
5V Supply
Note 1: Absolute Maximum Ratings indicatelimits beyond which damage to the device may occur. Operating Ratings indicate conditions for whichthe device is intended to be functional, but do not guarantee specific performance limits. For guaranteedspecifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.
Note 2: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150˚C. Output currents in excess of
±
30 mA over long term may adversely affect reliability.
Note 3: The maximum power dissipation is a functionofT
J(Max)
, θJA, andTA. Themaximumallowablepowerdissipationat any ambient temperature is P
D
=
(T
J(Max)
−TA)/θJA.
Note 4: Human body model, 1.5 kΩ in series with 100 pF.
Note 5: Typical values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
Note 7: V
+
=
15V, V
CM
=
7.5V and R
L
connected to 7.5V. For Sourcing tests, 7.5V ≤ VO≤ 11.5V. For Sinking tests, 2.5V ≤ VO≤ 7.5V.
Note 8: V
+
=
15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Note 9: For operating at elevated temperatures the device must be derated based on the thermal resistance θ
JA
with P
D
=
(T
J−TA
)/θJA.
Note 10: Do not connect output to V
+
, when V+is greater than 13V or reliability will be adversely affected.
Note 11: All numbers apply for packages soldered directly into a PC board.
Typical Performance Characteristics V
S
=
±
7.5V, T
A
=
25˚C, Unless otherwise specified
Distribution of LMC6081
Input Offset Voltage
(T
A
=
+25˚C)
DS011423-15
Distribution of LMC6081
Input Offset Voltage
(T
A
=
−55˚C)
DS011423-16
Distribution of LMC6081
Input Offset Voltage
(T
A
=
+125˚C)
DS011423-17
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Page 5
Typical Performance Characteristics V
S
=
±
7.5V, T
A
=
25˚C, Unless otherwise
specified (Continued)
Input Bias Current
vs Temperature
DS011423-18
Supply Current
vs Supply Voltage
DS011423-19
Input Voltage
vs Output Voltage
DS011423-20
Common Mode
Rejection Ratio
vs Frequency
DS011423-21
Power Supply Rejection
Ratio vs Frequency
DS011423-22
Input Voltage Noise
vs Frequency
DS011423-23
Output Characteristics
Sourcing Current
DS011423-24
Output Characteristics
Sinking Current
DS011423-25
Gain and Phase Response
vs Temperature
(−55˚C to +125˚C)
DS011423-26
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Typical Performance Characteristics V
S
=
±
7.5V, T
A
=
25˚C, Unless otherwise
specified (Continued)
Applications Hints
AMPLIFIER TOPOLOGY
The LMC6081 incorporates a novelop-amp design topology
that enables it tomaintain rail-to-railoutput swingeven when
driving a large load. Instead of relying on a push-pull unity
gain output buffer stage, the output stage is taken directly
from the internal integrator, which provides both low output
impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability
over a wider range of operating conditions than traditional
micropower op-amps. These features make the LMC6081
both easier to design with, and provide higher speed than
products typically found in this ultra-low power class.
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the
LMC6081.
Gain and Phase
Response vs Capacitive Load
with R
L
=
600Ω
DS011423-27
Gain and Phase
Response vs Capacitive Load
with R
L
=
500 kΩ
DS011423-28
Open Loop
Frequency Response
DS011423-29
Inverting Small Signal
Pulse Response
DS011423-30
Inverting Large Signal
Pulse Response
DS011423-31
Non-Inverting Small
Signal Pulse Response
DS011423-32
Non-Inverting Large
Signal Pulse Response
DS011423-33
Stability vs Capacitive
Load, R
L
=
600Ω
DS011423-34
Stability vs Capacitive
Load R
L
=
1MΩ
DS011423-35
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Applications Hints (Continued)
Although the LMC6081 is highly stable over a wide range of
operating conditions, certain precautions must be met to
achieve the desired pulse response when a large feedback
resistor is used. Large feedback resistors and even small
values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce phase margins.
When high input impedancesare demanded, guardingof the
LMC6081 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well.
(See
Printed-Circuit-Board Layout for High Impedance
Work).
The effect of input capacitance can be compensated for by
adding a capacitor, C
f
, around the feedback resistors (as in
Figure 1
) such that:
or
R
1CIN
≤ R2C
f
Since it is often difficult to knowthe exact valueof CIN,Cfcan
be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and LMC662 for a
more detailed discussion on compensating for input
capacitance.
CAPACITIVE LOAD TOLERANCE
All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor is
normally included in this integrator stage. The frequency location of the dominant pole is affected by the resistive load
on the amplifier. Capacitive loaddriving capabilitycan be optimized by using an appropriate resistive load in parallel with
the capacitive load (see typical curves).
Direct capacitive loading will reduce the phase margin of
many op-amps. A pole inthe feedback loop is createdby the
combination of the op-amp’s output impedance and the capacitive load. This pole induces phase lag at the unity-gain
crossover frequency of theamplifier resulting in eitheran oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in
Figure 2
.
In the circuit of
Figure 2
, R1 and C1 serve to counteract the
loss of phase margin by feeding the high frequency component of the output signal back to the amplifier’s inverting input, thereby preserving phasemargin inthe overall feedback
loop.
Capacitive load driving capabilityis enhancedby usinga pull
up resistor to V
+
(
Figure 3
). Typically a pull up resistor conducting 500 µA or more will significantly improve capacitive
load responses. The valueof thepull up resistor mustbe determined based on the currentsinking capability ofthe amplifier with respect to the desired output swing. Open loop gain
of the amplifier can also be affected by the pull up resistor
(see electrical characteristics).
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generallyrecognized thatany circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC6081, typically less
than 10 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite
simple. First, the usermust notignore thesurface leakageof
the PC board, even thoughit may sometimesappear acceptably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6081’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs, as in
Fig-
DS011423-4
FIGURE 1. Cancelling the Effect of Input Capacitance
DS011423-5
FIGURE 2. LMC6081 Noninverting Gain of 10 Amplifier,
Compensated to Handle Capacitive Loads
DS011423-14
FIGURE 3. Compensating for Large
Capacitive Loads with a Pull Up Resistor
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Page 8
Applications Hints (Continued)
ure 4
. To have a significant effect, guard rings should be
placed on both the topand bottom of the PC board. This PC
foil must then be connectedto avoltage which isat thesame
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 10
12
Ω, which is normally considered a very large resistance, could leak 5 pA if
the trace were a5V busadjacent to thepad ofthe input.This
would cause a 100 times degradation from the LMC6081’s
actual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 10
11
Ω would
cause only 0.05 pA of leakage current. See
Figure 5
for typical connections of guard rings for standard op-amp
configurations.
The designer should be aware that when it is inappropriate
to lay outa PC board for the sake of justa few circuits,there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, butbend it upin theair anduse only airas aninsulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring.
See
Figure 6
.
Latchup
CMOS devices tend to be susceptible to latchupdue to their
internal parasitic SCR effects. The (I/O) inputand output pins
look similar to the gate of the SCR. There is a minimum cur-
DS011423-6
FIGURE 4. Example of Guard Ring in P.C. Board
Layout
DS011423-7
Inverting Amplifier
DS011423-8
Non-Inverting Amplifier
DS011423-9
Follower
FIGURE 5. Typical Connections of Guard Rings
DS011423-10
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board).
FIGURE 6. Air Wiring
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Latchup (Continued)
rent required to trigger the SCR gate lead. The LMC6061
and LMC6081 are designed to withstand 100 mA surge current on the I/O pins. Some resistive method should be used
to isolate any capacitance from supplying excess current to
the I/O pins. In addition, like an SCR, there is a minimum
holding current for any latchup mode. Limiting current to the
supply pins will also inhibit latchup susceptibility.
Typical Single-Supply
Applications
(V
+
=
5.0 V
DC
)
The extremely high input impedance, and low power consumption, of the LMC6081 make it ideal for applications that
require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held pH
probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers.
Figure 7
shows an instrumentation amplifier that features
high differential and common mode input resistance
(
>
1014Ω), 0.01%gain accuracy at A
V
=
1000, excellent
CMRR with 1 kΩ imbalance in bridge source resistance. Input current is less than 100 fA and offset drift is less than
2.5 µV/˚C. R
2
provides a simple means of adjusting gain
over a wide range without degrading CMRR. R
7
is an initial
trim used to maximize CMRR without using super precision
matched resistors. For good CMRR over temperature, low
drift resistors should be used.
DS011423-11
If R
1
=
R
5,R3
=
R
6
, and R
4
=
R
7
; then
AV≈ 100 for circuit shown (R
2
=
9.822k).
FIGURE 7. Instrumentation Amplifier
DS011423-12
FIGURE 8. Low-Leakage Sample and Hold
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Page 10
Typical Single-Supply
Applications
(Continued)
DS011423-13
FIGURE 9. 1 Hz Square Wave Oscillator
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Page 11
Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin Small Outline Package
Order Number LMC6081AIM or LMC6081IM
NS Package Number M08A
8-Pin Molded Dual-In-Line Package
Order Number LMC6081AIN, LMC6081AMN or LMC6081IN
NS Package Number N08E
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Page 12
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTSARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b)support orsustain life,and whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected toresult in a significantinjury
to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected tocause the failureof the life support
device or system, orto affect its safetyor effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
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Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
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Response Group
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Email: sea.support@nsc.com
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
LMC6081 Precision CMOS Single Operational Amplifier
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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