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LMC6034
CMOS Quad Operational Amplifier
General Description
The LMC6034 is a CMOS quad operational amplifier which
can operate from either a single supply or dual supplies. Its
performance features include an input common-mode range
that reaches ground, low input bias current, and high voltage
gain into realistic loads, such as 2 kΩ and 600Ω.
This chip is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
See the LMC6032 datasheet for a CMOS dual operational
amplifier with these same features. For higher performance
characteristics refer to the LMC660.
Features
n Specified for 2 kΩ and 600Ω loads
n High voltage gain: 126 dB
n Low offset voltage drift: 2.3 µV/˚C
n Ultra low input bias current: 40 fA
n Input common-mode range includes V
−
n Operating Range from +5V to +15V supply
n I
SS
=
400 µA/amplifier; independent of V
+
n Low distortion: 0.01%at 10 kHz
n Slew rate: 1.1 V/µs
n Improved performance over TLC274
Applications
n High-impedance buffer or preamplifier
n Current-to-voltage converter
n Long-term integrator
n Sample-and-hold circuit
n Medical instrumentation
Connection Diagram
Ordering Information
Temperature Range Package NSC
Drawing
Transport
Media
Industrial
−40˚C ≤ T
J
≤ +85˚C
LMC6034IN 14-Pin N14A Rail
Molded DIP
LMC6034IM 14-Pin M14A Rail
Small Outline Tape and Reel
14-Pin DIP/SO
DS011134-1
Top View
May 1998
LMC6034 CMOS Quad Operational Amplifier
© 1999 National Semiconductor Corporation DS011134 www.national.com
Page 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Differential Input Voltage
±
Supply Voltage
Supply Voltage (V
+−V−
) 16V
Output Short Circuit to V
+
(Note 10)
Output Short Circuit to V
−
(Note 2)
Lead Temperature
(Soldering, 10 sec.) 260˚C
Storage Temperature Range −65˚C to +150˚C
Power Dissipation (Note 3)
Voltage at Output/Input Pin (V
+
) +0.3V, (V−) −0.3V
Current at Output Pin
±
18 mA
Current at Input Pin
±
5mA
Current at Power Supply Pin 35 mA
Junction Temperature (Note 3) 150˚C
ESD Tolerance (Note 4) 1000V
Operating Ratings(Note 1)
Temperature Range −40˚C ≤ T
J
≤ +85˚C
Supply Voltage Range 4.75V to 15.5V
Power Dissipation (Note 11)
Thermal Resistance (θ
JA
), (Note 12)
14-Pin DIP 85˚C/W
14-Pin SO 115˚C/W
DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
J
=
25˚C. Boldface limits apply at the temperature extremes. V
+
=
5V,
V
−
=
GND=0V, V
CM
=
1.5V, V
OUT
=
2.5V, and R
L
>
1M unless otherwise specified.
Symbol Parameter Conditions Typical
(Note 5)
LMC6034I Units
Limit
(Note 6)
V
OS
Input Offset Voltage 1 9 mV
11 max
∆V
OS
/∆T Input Offset Voltage 2.3 µV/˚C
Average Drift
I
B
Input Bias Current 0.04 pA
200 max
I
OS
Input Offset Current 0.01 pA
100 max
R
IN
Input Resistance
>
1 TeraΩ
CMRR Common Mode 0V ≤ V
CM
≤ 12V 83 63 dB
Rejection Ratio V
+
=
15V 60 min
+PSRR Positive Power Supply 5V ≤ V
+
≤ 15V 83 63 dB
Rejection Ratio V
O
=
2.5V 60 min
−PSRR Negative Power Supply 0V ≤ V
−
≤ −10V 94 74 dB
Rejection Ratio 70 min
V
CM
Input Common-Mode V
+
=
5V & 15V −0.4 −0.1 V
Voltage Range For CMRR ≥ 50 dB 0 max
V
+
− 1.9 V+− 2.3 V
V
+
− 2.6 min
A
V
Large Signal Voltage Gain R
L
=
2kΩ(Note 7) 2000 200 V/mV
Sourcing 100 min
Sinking 500 90 V/mV
40 min
R
L
=
600Ω (Note 7) 1000 100 V/mV
Sourcing 75 min
Sinking 250 50 V/mV
20 min
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Page 3
DC Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for T
J
=
25˚C. Boldface limits apply at the temperature extremes. V
+
=
5V,
V
−
=
GND=0V, V
CM
=
1.5V, V
OUT
=
2.5V, and R
L
>
1M unless otherwise specified.
Symbol Parameter Conditions Typical
(Note 5)
LMC6034I Units
Limit
(Note 6)
V
O
Output Voltage Swing V
+
=
5V 4.87 4.20 V
R
L
=
2kΩto 2.5V 4.00 min
0.10 0.25 V
0.35 max
V
+
=
5V 4.61 4.00 V
R
L
=
600Ω to 2.5V 3.80 min
0.30 0.63 V
0.75 max
V
+
=
15V 14.63 13.50 V
R
L
=
2kΩto 7.5V 13.00 min
0.26 0.45 V
0.55 max
V
+
=
15V 13.90 12.50 V
R
L
=
600Ω to 7.5V 12.00 min
0.79 1.45 V
1.75 max
I
O
Output Current V
+
=
5V 22 13 mA
Sourcing, V
O
=
0V 9 min
Sinking, V
O
=
5V 21 13 mA
9 min
V
+
=
15V 40 23 mA
Sourcing, V
O
=
0V 15 min
Sinking, V
O
=
13V 39 23 mA
(Note 10) 15 min
I
S
Supply Current All Four Amplifiers 1.5 2.7 mA
V
O
=
1.5V 3.0 max
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AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
J
=
25˚C. Boldface limits apply at the temperature extremes. V
+
=
5V,
V
−
=
GND=0V, V
CM
=
1.5V, V
OUT
=
2.5V, and R
L
>
1M unless otherwise specified.
Symbol Parameter Conditions Typical
(Note 5)
LMC6034I Units
Limit
(Note 6)
SR Slew Rate (Note 8) 1.1 0.8 V/µs
0.4 min
GBW Gain-Bandwidth Product 1.4 MHz
φ
M
Phase Margin 50 Deg
G
M
Gain Margin 17 dB
Amp-to-Amp Isolation (Note 9) 130 dB
e
n
Input-Referred Voltage Noise F=1 kHz 22
i
n
Input-Referred Current Noise F=1 kHz 0.0002
THD Total Harmonic Distortion F=10 kHz, A
V
=
−10
R
L
=
2kΩ,V
O
=
8V
PP
0.01
%
±
5V Supply
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed.
Note 2: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts
can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of
±
30 mA over long term may adversely affect reliability.
Note 3: The maximum power dissipation is a function of T
J(max)
, θJA,TA. The maximum allowable power dissipation at any ambient temperature is P
D
=
(T
J(max)–TA
)/θJA.
Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5: Typical values represent the most likely parametric norm.
Note 6: All limits are guaranteed at room temperature (standard type face) or at operating temperature extremes (bold type face).
Note 7: V
+
=
15V, V
CM
=
7.5V, and R
L
connected to 7.5V. For Sourcing tests, 7.5V ≤ VO≤ 11.5V.For Sinking tests, 2.5V ≤ VO≤ 7.5V.
Note 8: V
+
=
15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Note 9: Input referred. V
+
=
15V and R
L
=
10 kΩ connected to V
+
/2. Each amp excited in turn with 1 kHz to produce V
O
=
13 V
PP
.
Note 10: Do not connect output to V
+
, when V+is greater than 13V or reliability may be adversely affected.
Note 11: For operating at elevated temperatures the device must be derated based on the thermal resistance θ
JA
with P
D
=
(T
J−TA
)/θJA.
Note 12: All numbers apply for packages soldered directly into a PC board.
Typical Performance Characteristics V
S
=
±
7.5V, T
A
=
25˚C unless otherwise specified
Supply Current
vs Supply Voltage
DS011134-23
Input Bias Current
DS011134-24
Output Characteristics
Current Sinking
DS011134-25
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Page 5
Typical Performance Characteristics V
S
=
±
7.5V, T
A
=
25˚C unless otherwise specified (Continued)
Applications Hint
Amplifier Topolgy
The topology chosen for the LMC6034, shown in
Figure 1
,is
unconventional (compared to general-purpose op amps) in
that the traditional unity-gain buffer output stage is not used;
instead, the output is taken directly from the output of the integrator, to allow a larger output swing. Since the buffer traditionally delivers the power to the load, while maintaining
high op amp gain and stability, and must withstand shorts to
either rail, these tasks now fall to the integrator.
As a result of these demands, the integrator is a compound
affair with an embedded gain stage that is doubly fed forward
(via C
f
and Cff) by a dedicated unity-gain compensation
driver. In addition, the output portion of the integrator is a
push-pull configuration for delivering heavy loads. While
sinking current the whole amplifier path consists of three
gain stages with one stage fed forward, whereas while
sourcing the path contains four gain stages with two fed
forward.
Output Characteristics
Current Sourcing
DS011134-27
Input Voltage Noise
vs Frequency
DS011134-28
CMRR vs Frequency
DS011134-29
Open-Loop Frequency
Response
DS011134-30
Frequency Response
vs Capacitive Load
DS011134-31
Non-Inverting Large Signal
Pulse Response
DS011134-32
Stability vs
Capacitive Load
DS011134-33
Stability vs
Capacitive Load
DS011134-34
Note: Avoid resistive loads of less than 500Ω, as they may cause instability.
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Page 6
Applications Hint (Continued)
The large signal voltage gain while sourcing is comparable
to traditional bipolar op amps, even with a 600Ω load. The
gain while sinking is higher than most CMOS op amps, due
to the additional gain stage; however, under heavy load
(600Ω) the gain will be reduced as indicated in the Electrical
Characteristics.
Compensating Input Capacitance
The high input resistance of the LMC6034 op amps allows
the use of large feedback and source resistor values without
losing gain accuracy due to loading. However, the circuit will
be especially sensitive to its layout when these large-value
resistors are used.
Every amplifier has some capacitance between each input
and AC ground, and also some differential capacitance between the inputs. When the feedback network around an
amplifier is resistive, this input capacitance (along with any
additional capacitance due to circuit board traces, the
socket, etc.) and the feedback resistors create a pole in the
feedback path. In the following General OperationalAmplifier
circuit,
Figure 2
the frequency of this pole is
where CSis the total capacitance at the inverting input, including amplifier input capcitance and any stray capacitance
from the IC socket (if one is used), circuit board traces, etc.,
and R
P
is the parallel combination of RFand RIN. This formula, as well as all formulae derived below, apply to inverting and non-inverting op-amp configurations.
When the feedback resistors are smaller than a few kΩ, the
frequency of the feedback pole will be quite high, since C
S
is
generally less than 10 pF. If the frequency of the feedback
pole is much higher than the “ideal” closed-loop bandwidth
(the nominal closed-loop bandwidth in the absence of C
S
),
the pole will have a negligible effect on stability,as it will add
only a small amount of phase shift.
However,if the feedback pole is less than approximately 6 to
10 times the “ideal” −3 dB frequency, a feedback capacitor,
C
F
, should be connected between the output and the inverting input of the op amp. This condition can also be stated in
terms of the amplifier’s low-frequency noise gain: To maintain stability a feedback capacitor will probably be needed if
where
is the amplifier’s low-frequency noise gain and GBW is the
amplifier’s gain bandwidth product. An amplifier’s
low-frequency noise gain is represented by the formula
regardless of whether the amplifier is being used in inverting
or non-inverting mode. Note that a feedback capacitor is
more likely to be needed when the noise gain is low and/or
the feedback resistor is large.
If the above condition is met (indicating a feedback capacitor
will probably be needed), and the noise gain is large enough
that:
the following value of feedback capacitor is recommended:
If
the feedback capacitor should be:
Note that these capacitor values are usually significantly
smaller than those given by the older, more conservative formula:
Using the smaller capacitors will give much higher bandwidth with little degradation of transient response. It may be
necessary in any of the above cases to use a somewhat
larger feedback capacitor to allow for unexpected stray ca-
DS011134-3
FIGURE 1. LMC6034 Circuit Topology (Each Amplifier)
DS011134-4
CSconsists of the amplifier’s input capacitance plus any stray capacitance
from the circuit board and socket. CFcompensates for the pole caused by
CSand the feedback resistors.
FIGURE 2. General Operational Amplifier Circuit
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Page 7
Applications Hint (Continued)
pacitance, or to tolerate additional phase shifts in the loop, or
excessive capacitive load, or to decrease the noise or bandwidth, or simply because the particular circuit implementation needs more feedback capacitance to be sufficiently
stable. For example, a printed circuit board’s stray capacitance may be larger or smaller than the breadboard’s, so the
actual optimum value for C
F
may be different from the one
estimated using the breadboard. In most cases, the values
of C
F
should be checked on the actual circuit, starting with
the computed value.
Capacitive Load Tolerance
Like many other op amps, the LMC6034 may oscillate when
its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration
most sensitive to oscillation is a unity-gain follower. See
Typical Performance Characteristics.
The load capacitance interacts with the op amp’s output resistance to create an additional pole. If this pole frequency is
sufficiently low, it will degrade the op amp’s phase margin so
that the amplifier is no longer stable at low gains. As shown
in
Figure 3
, the addition of a small resistor (50Ω to 100Ω)in
series with the op amp’s output, and a capacitor (5 pF to 10
pF) from inverting input to output pins, returns the phase
margin to a safe value without interfering with
lower-frequency circuit operation. Thus larger values of capacitance can be tolerated without oscillation. Note that in all
cases, the output will ring heavily when the load capacitance
is near the threshold for oscillation.
Capacitive load driving capability is enhanced by using a pull
up resistor to V
+
(
Figure 4
). Typically a pull up resistor conducting 500 µA or more will significantly improve capacitive
load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain
of the amplifier can also be affected by the pull up resistor
(see Electrical Characteristics).
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC6034, typically less
than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6034’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs. See
Figure
5
. To have a significant effect, guard rings should be placed
on both the top and bottom of the PC board. This PC foil
must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 10
12
Ω, which is normally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of an input. This
would cause a 100 times degradation from the LMC6034’s
actual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 10
11
Ω would
cause only 0.05 pA of leakage current, or perhaps a minor
(2:1) degradation of the amplifier’s performance. See
Fig-
ures 6, 7, 8
for typical connections of guard rings for standard op-amp configurations. If both inputs are active and at
high impedance, the guard can be tied to ground and still
provide some protection; see
Figure 9
.
DS011134-5
FIGURE 3. Rx, Cx Improve Capacitive Load Tolerance
DS011134-22
FIGURE 4. Compensating for Large Capacitive Loads
with a Pull Up Resistor
DS011134-6
FIGURE 5. Example of Guard Ring in P.C. Board
Layout
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Applications Hint (Continued)
The designer should be aware that when it is inappropriate
to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring. See
Figure
10
.
BIAS CURRENT TESTING
The test method of
Figure 11
is appropriate for bench-testing
bias current with reasonable accuracy. Tounderstand its operation, first close switch S2 momentarily. When S2 is
opened, then
A suitable capacitor for C2 would be a 5 pF or 10 pF silver
mica, NPO ceramic, or air-dielectric. When determining the
magnitude of I
b
−, the leakage of the capacitor and socket
must be taken into account. Switch S2 should be left shorted
most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2
shorted)
where Cxis the stray capacitance at the + input.
DS011134-7
FIGURE 6. Guard Ring Connections
Inverting Amplifier
DS011134-8
FIGURE 7. Guard Ring Connections
Non-Inverting Amplifier
DS011134-9
FIGURE 8. Guard Ring Connections
Follower
DS011134-10
FIGURE 9. Guard Ring Connections
Howland Current Pump
DS011134-11
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board.)
FIGURE 10. Air Wiring
DS011134-12
FIGURE 11. Simple Input Bias Current Test Circuit
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Typical Single-Supply Applications (V
+
=
5.0 VDC)
Additional single-supply applications ideas can be found in
the LM324 datasheet. The LMC6034 is pin-for-pin compatible with the LM324 and offers greater bandwidth and input
resistance over the LM324. These features will improve the
performance of many existing single-supply applications.
Note, however, that the supply voltage range of the
LMC6034 is smaller than that of the LM324.
For good CMRR over temperature, low drift resistors should
be used. Matching of R3 to R6 and R4 to R7 affect CMRR.
Gain may be adjusted through R2. CMRR may be adjusted
through R7.
Oscillator frequency is determined by R1, R2, C1, and C2:
fosc=1/2πRC, where R=R1=R2 and
C=C1=C2.
This circuit, as shown, oscillates at 2.0 kHz with a
peak-to-peak output swing of 4.0V.
Low-Leakage Sample-and-Hold
DS011134-13
Instrumentation Amplifier
DS011134-14
Sine-Wave Oscillator
DS011134-15
1 Hz Square-Wave Oscillator
DS011134-16
Power Amplifier
DS011134-17
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Page 10
Typical Single-Supply Applications
(V
+
=
5.0 VDC) (Continued)
10 Hz Bandpass Filter
DS011134-18
f
O
=
10 Hz
Q=2.1
Gain=−8.8
10 Hz High-Pass Filter
DS011134-20
f
c
=
10 Hz
d=0.895
Gain=1
2 dB passband ripple
1 Hz Low-Pass Filter
(Maximally Flat, Dual Supply Only)
DS011134-19
f
c
=
1Hz
d=1.414
Gain=1.57
High Gain Amplifier with Offset
Voltage Reduction
DS011134-21
Gain=−46.8
Output offset
voltage reduced
to the level of
the input offset
voltage of the
bottom amplifier
(typically 1 mV).
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Page 11
Physical Dimensions inches (millimeters) unless otherwise noted
Small Outline Dual-In-Line Pkg. (M)
Order Number LMC6034IM
NS Package Number M14A
Molded Dual-In-Line Pkg. (N)
Order Number LMC6034IN
NS Package Number N14A
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Page 12
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: [email protected]
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Europe
Fax: +49 (0) 1 80-530 85 86
Email: [email protected]
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Response Group
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Email: [email protected]
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
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LMC6034 CMOS Quad Operational Amplifier
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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