Page 1
查询LMC6032供应商
LMC6032
CMOS Dual Operational Amplifier
General Description
The LMC6032 is a CMOS dual operational amplifier which
can operate from either a single supply or dual supplies. Its
performance features include an input common-mode range
that reaches ground, low input bias current,andhighvoltage
gain into realistic loads, such as 2 kΩ and 600Ω.
This chip is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
See the LMC6034 datasheet for a CMOS quad operational
amplifier with these same features. For higher performance
characteristics refer to the LMC662.
Features
n Specified for 2 kΩ and 600Ω loads
n High voltage gain: 126 dB
n Low offset voltage drift: 2.3 µV/˚C
n Ultra low input bias current: 40 fA
n Input common-mode range includes V
n Operating range from +5V to +15V supply
=
n I
400 µA/amplifier; independent of V
SS
n Low distortion: 0.01%at 10 kHz
n Slew rate: 1.1 V/µs
n Improved performance over TLC272
−
Applications
n High-impedance buffer or preamplifier
n Current-to-voltage converter
n Long-term integrator
n Sample-and-hold circuit
n Medical instrumentation
LMC6032 CMOS Dual Operational Amplifier
November 1994
+
Connection Diagram
Ordering Information
Temperature Range Package NSC Drawing Transport Media
Industrial
−40˚C ≤ T
J
LMC6032IN 8-Pin N08E Rail
LMC6032IM 8-Pin M08A Rail
8-Pin DIP/SO
DS011135-1
Top View
≤ +85˚C
Molded DIP
Small Outline Tape and Reel
© 1999 National Semiconductor Corporation DS011135 www.national.com
Page 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the NationalSemiconductorSalesOffice/
Distributors for availability and specifications.
Differential Input Voltage
Supply Voltage (V
Output Short Circuit to V
Output Short Circuit to V
+−V−
) 16V
+
−
Lead Temperature
(Soldering, 10 sec.) 260˚C
Storage Temperature Range −65˚C to +150˚C
Junction Temperature 150˚C
ESD Tolerance (Note 4) 1000V
Power Dissipation (Note 3)
±
Supply Voltage
(Note 10)
(Note 2)
+
Voltage at Output/Input Pin (V
Current at Output Pin
Current at Input Pin
) + 0.3V,
−
(V
) − 0.3V
±
18 mA
±
5mA
Current at Power Supply Pin 35 mA
Operating Ratings (Note 1)
Temperature Range −40˚C ≤ T
Supply Voltage Range 4.75V to 15.5V
Power Dissipation (Note 11)
Thermal Resistance (θ
), (Note 12)
JA
8-Pin DIP 101˚C/W
8-Pin SO 165˚C/W
≤ +85˚C
J
DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
−
=
V
GND=0V, V
=
1.5V, V
CM
OUT
=
2.5V and R
Symbol Parameter Conditions Typical
V
OS
∆V
/∆T Input Offset Voltage 2.3 µV/˚C
OS
Input Offset Voltage 1 9 mV
Average Drift
I
B
I
OS
R
IN
Input Bias Current 0.04 pA
Input Offset Current 0.01 pA
Input Resistance
CMRR Common Mode 0V ≤ V
Rejection Ratio V
+PSRR Positive Power Supply 5V ≤ V
Rejection Ratio V
−PSRR Negative Power Supply 0V ≤ V
Rejection Ratio 70 min
V
CM
Input Common-Mode V
Voltage Range For CMRR ≥ 50 dB 0 max
A
V
Large Signal R
Voltage Gain Sourcing 100 min
=
25˚C. Boldface limits apply at the temperature extremes. V
J
>
1M unless otherwise specified.
L
(Note 5)
LMC6032I Units
Limit
(Note 6)
11 max
200 max
100 max
>
1 TeraΩ
≤ 12V 83 63 dB
CM
+
=
15V 60 min
+
≤ 15V 83 63 dB
=
2.5V 60 min
O
−
≤ −10V 94 74 dB
+
=
5V & 15V −0.4 −0.1 V
+
V
− 1.9 V+− 2.3 V
=
2kΩ(Note 7) 2000 200 V/mV
L
+
V
− 2.6 min
Sinking 500 90 V/mV
40 min
=
R
600Ω (Note 7) 1000 100 V/mV
L
Sourcing 75 min
Sinking 250 50 V/mV
20 min
+
=
5V,
www.national.com 2
Page 3
DC Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for T
−
=
V
GND=0V, V
=
1.5V, V
CM
OUT
=
2.5V and R
Symbol Parameter Conditions Typical
V
O
I
O
I
S
Output Voltage Swing V
Output Current V
Supply Current Both Amplifiers 0.75 1.6 mA
=
25˚C. Boldface limits apply at the temperature extremes. V
J
>
1M unless otherwise specified.
L
+
=
5V 4.87 4.20 V
=
R
2kΩto 2.5V 4.00 min
L
+
=
V
5V 4.61 4.00 V
=
R
600Ω to 2.5V 3.80 min
L
+
=
V
15V 14.63 13.50 V
=
R
2kΩto 7.5V 13.00 min
L
+
=
V
15V 13.90 12.50 V
=
R
600Ω to 7.5V 12.00 min
L
+
=
5V 22 13 mA
Sourcing, V
Sinking, V
+
=
V
Sourcing, V
Sinking, V
=
0V 9 min
O
=
5V 21 13 mA
O
15V 40 23 mA
=
0V 15 min
O
=
13V 39 23 mA
O
(Note 10) 15 min
=
V
1.5V 1.9 max
O
(Note 5)
LMC6032I Units
Limit
(Note 6)
0.10 0.25 V
0.35 max
0.30 0.63 V
0.75 max
0.26 0.45 V
0.55 max
0.79 1.45 V
1.75 max
9 min
+
=
5V,
www.national.com3
Page 4
AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
−
=
V
GND=0V, V
=
1.5V, V
CM
OUT
=
2.5V and R
Symbol Parameter Conditions Typical
=
25˚C. Boldface limits apply at the temperature extremes. V
J
>
1M unless otherwise specified.
L
(Note 5)
LMC6032I Units
Limit
+
=
5V,
(Note 6)
SR Slew Rate (Note 8) 1.1 0.8 V/µs
0.4 min
GBW Gain-Bandwidth Product 1.4 MHz
φ
M
G
M
Phase Margin 50 Deg
Gain Margin 17 dB
Amp-to-Amp Isolation (Note 9) 130 dB
e
n
Input-Referred Voltage Noise F=1 kHz 22
i
n
THD Total Harmonic Distortion F=10 kHz, A
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to component may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.
Note 2: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts
can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of
Note 3: The maximum power dissipation is a function of T
–TA)/θJA.
Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5: Typical values represent the most likely parametric norm.
Note 6: All limits are guaranteed at room temperature (standard type face) or at operating temperature extremes (bold type face).
Note 7: V
Note 8: V
Note 9: Input referred. V
Note 10: Do not connect output to V
Note 11: For operating at elevated temperatures the device must be derated based on the thermal resistance θ
Note 12: All numbers apply for packages soldered directly into a PC board.
Input-Referred Current Noise F=1 kHz 0.0002
=
−10
2kΩ,V
V
=
8V
O
PP
0.01
±
30 mA over long term may adversely affect reliability.
=
.
13 V
O
PP
=
with P
JA
(T
D
J−TA
=
R
L
±
5V Supply
, θJA, and TA. The maximum allowable power dissipation at any ambient temperature is P
J(max)
+
=
+
=
=
15V, V
15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
CM
7.5V, and R
+
=
connected to 7.5V. For Sourcing tests, 7.5V ≤ VO≤ 11.5V. For Sinking tests, 2.5V ≤ VO≤ 7.5V.
L
15V and R
=
10 kΩ connected to V
L
+
, when V+is greater than 13V or reliability may be adversely affected.
+
/2. Each amp excited in turn with 1 kHz to produce V
)/θJA.
%
=
(T
D
J(max)
www.national.com 4
Page 5
Typical Performance Characteristics V
Supply Current
vs Supply Voltage
Input Bias Current
=
±
S
7.5V, T
=
25˚C unless otherwise specified
A
Output Characteristics
Current Sinking
Output Characteristics
Current Sourcing
Open-Loop Frequency
Response
DS011135-23
DS011135-26
Input Voltage Noise
vs Frequency
Frequency Response
vs Capacitive Load
DS011135-24
DS011135-25
CMRR vs Frequency
DS011135-28
DS011135-27
Non-Inverting Large Signal
Pulse Response
DS011135-29
DS011135-30
DS011135-31
www.national.com5
Page 6
Typical Performance Characteristics V
=
±
S
7.5V, T
=
25˚C unless otherwise specified (Continued)
A
Stability vs
Capacitive Load
DS011135-32
Note 13: Avoid resistive loads of less than 500Ω, as they may cause instability.
Stability vs
Capacitive Load
Application Hints
AMPLIFIER TOPOLOGY
Figure 1
The topology chosen for the LMC6032, shown in
unconventional (compared to general-purpose op amps) in
that the traditional unity-gain buffer output stage is not used;
instead, the output is taken directly from the output of the integrator, to allow a larger output swing. Since the buffer traditionally delivers the power to the load, while maintaining
high op amp gain and stability, and must withstand shorts to
either rail, these tasks now fall to the integrator.
As a result of these demands, the integrator is a compound
affair with an embedded gain stage that is doubly fed forward
(via C
and Cff) by a dedicated unity-gain compensation
f
driver. In addition, the output portion of the integrator is a
push-pull configuration for delivering heavy loads. While
sinking current the whole amplifier path consists of three
gain stages with one stage fed forward, whereas while
sourcing the path contains four gain stages with two fed
forward.
DS011135-3
FIGURE 1. LMC6032 Circuit Topology (Each Amplifier)
The large signal voltage gain while sourcing is comparable
to traditional bipolar op amps, even with a 600Ω load. The
gain while sinking is higher than most CMOS op amps, due
to the additional gain stage; however, under heavy load
(600Ω) the gain will be reduced as indicated in the Electrical
Characteristics.
,is
DS011135-33
COMPENSATING INPUT CAPACITANCE
The high input resistance of the LMC6032 op amps allows
the use of large feedback and source resistor values without
losing gain accuracy due to loading. However,the circuit will
be especially sensitive to its layout when these large-value
resistors are used.
Every amplifier has some capacitance between each input
and AC ground, and also some differential capacitance between the inputs. When the feedback network around an
amplifier is resistive, this input capacitance (along with any
additional capacitance due to circuit board traces, the
socket, etc.) and the feedback resistors create a pole in the
feedback path. In the following General Operational Amplifier
Circuit,
Figure 2
, the frequency of this pole is
where CSis the total capacitance at the inverting input, including amplifier input capacitance and any stray capacitance from the IC socket (if one is used), circuit board traces,
etc., and R
formula, as well as all formulae derived below, apply to in-
is the parallel combination of RFand RIN. This
P
verting and non-inverting op-amp configurations.
When the feedback resistors are smaller than a few kΩ, the
frequency of the feedback pole will be quite high, since C
generally less than 10 pF. If the frequency of the feedback
S
pole is much higher than the “ideal” closed-loop bandwidth
(the nominal closed-loop bandwidth in the absence of C
the pole will have a negligible effect on stability, as it will add
only a small amount of phase shift.
However,if the feedback pole is less than approximately 6 to
10 times the “ideal” −3 dB frequency, a feedback capacitor,
C
, should be connected between the output and the invert-
F
ing input of the op amp. This condition can also be stated in
terms of the amplifier’s low-frequency noise gain: To maintain stability, a feedback capacitor will probably be needed if
is
),
S
www.national.com 6
Page 7
Application Hints (Continued)
where
is the amplifier’s low-frequency noise gain and GBW is the
amplifier’s gain bandwidth product. An amplifier’s
low-frequency noise gain is represented by the formula
regardless of whether the amplifier is being used in an inverting or non-inverting mode. Note that a feedback capacitor is
more likely to be needed when the noise gain is low and/or
the feedback resistor is large.
If the above condition is met (indicating a feedback capacitor
will probably be needed), and the noise gain is large enough
that:
the following value of feedback capacitor is recommended:
If
larger feedback capacitor to allow for unexpected stray capacitance, or to tolerate additional phase shifts in the loop, or
excessive capacitive load, or to decrease the noise or bandwidth, or simply because the particular circuit implementation needs more feedback capacitance to be sufficiently
stable. For example, a printed circuit board’s stray capacitance may be larger or smaller than the breadboard’s, so the
actual optimum value for C
estimated using the breadboard. In most cases, the value of
C
should be checked on the actual circuit, starting with the
F
computed value.
may be different from the one
F
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC6032 may oscillate when
its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration
most sensitive to oscillation is a unity-gain follower. See the
Typical Performance Characteristics.
The load capacitance interacts with the op amp’s output resistance to create an additional pole. If this pole frequency is
sufficiently low,it will degrade the op amp’s phase margin so
that the amplifier is no longer stable at low gains. As shown
in
Figure 3
, the addition of a small resistor (50Ω to 100Ω)in
series with the op amp’s output, and a capacitor (5 pF to 10
pF) from inverting input to output pins, returns the phase
margin to a safe value without interfering with
lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note that in all
cases, the output will ring heavily when the load capacitance
is near the threshold for oscillation.
the feedback capacitor should be:
Note that these capacitor values are usually significantly
smaller than those given by the older, more conservative formula:
CSconsists of the amplifier’s input capacitance plus any stray capacitance
from the circuit board and socket. C
CSand the feedback resistor.
DS011135-4
compensates for the pole caused by
F
FIGURE 2. General Operational Amplifier Circuit
Using the smaller capacitors will give much higher bandwidth with little degradation of transient response. It may be
necessary in any of the above cases to use a somewhat
DS011135-5
FIGURE 3. Rx, Cx Improve Capacitive Load Tolerance
Capacitive load driving capability is enhanced by using a pull
up resistor to V
+
(
Figure 4
). Typically a pull up resistor conducting 500 µA or more will significantly improve capacitive
load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain
of the amplifier can also be affected by the pull up resistor
(see Electrical Characteristics).
DS011135-22
FIGURE 4. Compensating for Large Capacitive
Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC6032, typically less
www.national.com7
Page 8
Application Hints (Continued)
than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6032’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs. See
5
. To have a significant effect, guard rings should be placed
on both the top and bottom of the PC board. This PC foil
must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 10
12
Ω, which is normally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of an input. This
would cause a 100 times degradation from the LMC6032’s
actual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 10
cause only 0.05 pA of leakage current, or perhaps a minor
(2:1) degradation of the amplifier’s performance. See
6a
,
Figure 6b,Figure 6c
for typical connections of guard
rings for standard op-amp configurations. If both inputs are
active and at high impedance, the guard can be tied to
ground and still provide some protection; see
11
Ω would
Figure 6d
Figure
Figure
.
DS011135-7
(a) Inverting Amplifier
DS011135-8
(b) Non-Inverting Amplifier
DS011135-9
(c) Follower
DS011135-6
FIGURE 5. Example of Guard Ring in
P.C. Board Layout
www.national.com 8
DS011135-10
(d) Howland Current Pump
FIGURE 6. Guard Ring Connections
The designer should be aware that when it is inappropriate
to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring.
See
Figure 7
.
Page 9
Application Hints (Continued)
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board.)
DS011135-11
FIGURE 7. Air Wiring
BIAS CURRENT TESTING
Figure 8
The test method of
is appropriate for bench-testing
bias current with reasonable accuracy. To understand its operation, first close switch S2 momentarily. When S2 is
opened, then
Typical Single-Supply Applications (V
Additional single-supply applications ideas can be found in
the LM358 datasheet. The LMC6032 is pin-for-pin compatible with the LM358 and offers greater bandwidth and input
resistance over the LM358. These features will improve the
performance of many existing single-supply applications.
Note, however, that the supply voltage range of the
LMC6032 is smaller than that of the LM358.
Instrumentation Amplifier
DS011135-12
FIGURE 8. Simple Input Bias Current Test Circuit
A suitable capacitor for C2 would be a 5 pF or 10 pF silver
mica, NPO ceramic, or air-dielectric. When determining the
magnitude of I
must be taken into account. Switch S2 should be left shorted
−, the leakage of the capacitor and socket
b
most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2
shorted)
where Cxis the stray capacitance at the + input.
+
=
5.0 V
)
DC
and R4=R7.
=
100 for circuit shown.
For good CMRR over temperature, low drift resistors should
be used. Matching of R3 to R6 and R4 to R7 affects CMRR.
Gain may be adjusted through R2. CMRR may be adjusted
through R7.
Sine-Wave Oscillator
if R1=R5;
R3=R6,
DS011135-14
Oscillator frequency is determined by R1, R2, C1, and C2:
=
1/2πRC
f
OSC
where R=R1=R2 and C=C1=C2.
DS011135-15
www.national.com9
Page 10
Typical Single-Supply Applications
+
=
(V
This circuit, as shown, oscillates at 2.0 kHz with a
peak-to-peak output swing of 4.0V.
) (Continued)
5.0 V
DC
Low-Leakage Sample-and-Hold
10 Hz Bandpass Filter
1 Hz Square-Wave Oscillator
Power Amplifier
DS011135-13
DS011135-16
DS011135-17
=
f
10 Hz
O
Q=2.1
Gain=−8.8
DS011135-18
1 Hz Low-Pass Filter
(Maximally Flat, Dual Supply Only)
DS011135-19
10 Hz High-Pass Filter
www.national.com 10
=
f
10 Hz
c
d=0.895
Gain=1
2 dB passband ripple
DS011135-20
Page 11
Typical Single-Supply Applications (V
High Gain Amplifier with
Offset Voltage Reduction
+
=
5.0 V
) (Continued)
DC
Gain=−46.8
Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV).
DS011135-21
www.national.com11
Page 12
Physical Dimensions inches (millimeters) unless otherwise noted
Small Outline Dual-In-Line Package (M)
Order Number LMC6032IM
NS Package Number M08A
Molded Dual-In-Line Package (N)
Order Number LMC6032IN
NS Package Number N08E
www.national.com 12
Page 13
Notes
LMC6032 CMOS Dual Operational Amplifier
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National Semiconductor
Europe
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: sea.support@nsc.com
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Loading...