Datasheet LMC555 Datasheet (National Semiconductor)

LMC555
CMOS Timer

LMC555 CMOS Timer

October 2003

General Description

The LMC555 is a CMOS version of the industry standard
555 series general purpose timers. In addition to the stan­dard package (SOIC, MSOP, and MDIP) the LMC555 is also
available in a chip sized package (8 Bump micro SMD) using
National’s micro SMD package technology. The LMC555
offers the same capability of generating accurate time delays
and frequencies as the LM555 but with much lower power
dissipation and supply current spikes. When operated as a
one-shot, the time delay is precisely controlled by a single
external resistor and capacitor. In the stable mode the oscil­lation frequency and duty cycle are accurately set by two
external resistors and one capacitor. The use of National
Semiconductor’s LMCMOS
quency range and low supply capability.

™

process extends both the fre-

Block and Connection Diagrams

8-Pin SOIC, MSOP,

and MDIP Packages

Features

n Less than 1 mW typical power dissipation at 5V supply
n 3 MHz astable frequency capability
n 1.5V supply operating voltage guaranteed
n Output fully compatible with TTL and CMOS logic at 5V

supply

n Tested to −10 mA, +50 mA output current levels
n Reduced supply current spikes during output transitions
n Extremely low reset, trigger, and threshold currents
n Excellent temperature stability
n Pin-for-pin compatible with 555 series of timers
n Available in 8 pin MSOP Package and 8-Bump micro

SMD package

Pulse Width Modulator

00866920

Top View

8-Bump micro SMD

Top View

(Bump side down)

LMCMOS™is a trademark of National Semiconductor Corp.

© 2004 National Semiconductor Corporation DS008669 www.national.com

00866901

00866915

00866909

Ordering Information

LMC555

Note: See Mil-datasheet MNLMC555-X for specifications on the military device LMC555J/883.

Package Temperature Range Package Marking Transport Media NSC Drawing

Industrial

−40˚C to +85˚C

8-LeadSmall Outline
(SO)

8-Lead Mini Small
Outline (MSOP)

8-Lead Molded Dip
(MDIP)

8-Bump micro SMD LMC555CBP F1 250 Units Tape and Reel

LMC555CM LMC555CM Rails

LMC555CMX LMC555CM 2.5k Units Tape and Reel

LMC555CMM ZC5 1k Units Tape and Reel

LMC555CMMX ZC5 3.5k Units Tape and Reel

LMC555CN LMC555CN Rails

LMC555CBPX F1 3k Units Tape and Reel

M08A

MUA08A

N08E

BPA08EFB

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LMC555

Absolute Maximum Ratings (Notes 2, 3)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage, V

Input Voltages, V
V

CTRL,VTHRESH

Output Voltages, V

Output Current I

+

TRIG,VRES

O,VDIS

O,IDIS

,

−0.3V to VS+ 0.3V

Storage Temperature Range −65˚C to +150˚C

Soldering Information

MDIP Soldering (10 seconds) 260˚C

SOIC, MSOP Vapor Phase (60

sec) 215˚C

SOIC, MSOP Infrared (15 sec) 220˚C

Note: See AN-450 “Surface Mounting Methods and Their Effect on Product

Reliability” for other methods of soldering surface mount devices.

15V

15V

100 mA

Operating Ratings(Notes 2, 3)

Termperature Range −40˚C to +85˚C

Thermal Resistance (θ

SO, 8-lead Small Outline 169˚C/W

MSOP, 8-lead Mini Small
Outline 225˚C/W

MDIP, 8-lead Molded Dip 111˚C/W

8-Bump micro SMD 220˚C/W

Maximum Allowable Power
Dissipation

@

25˚C

MDIP-8 1126mW

SO-8 740mW

MSOP-8 555mW

8 Bump micro SMD 568mW

) (Note 2)

JA

Electrical Characteristics (Notes 1, 2)

Test Circuit, T = 25˚C, all switches open, RESET to V

Symbol Parameter Conditions Min Typ Max Units

I

S

V

CTRL

V

DIS

V

OL

V

OH

V

TRIG

I

TRIG

V

RES

I

RES

I

THRESH

I

DIS

Supply Current VS= 1.5V

=5V

V

S

= 12V

V

S

Control Voltage VS= 1.5V

=5V

V

S

= 12V

V

S

Discharge Saturation Voltage VS= 1.5V, I

= 5V, I

V

S

Output Voltage (Low) VS= 1.5V, IO=1mA

= 5V, IO=8mA

V

S

= 12V, IO=50mA

V

S

Output Voltage
(High)

VS= 1.5V, IO= −0.25 mA

= 5V, IO=−2mA

V

S

= 12V, IO= −10 mA

V

S

Trigger Voltage VS= 1.5V

= 12V

V

S

Trigger Current VS=5V 10 pA

Reset Voltage VS= 1.5V (Note 4)

= 12V

V

S

Reset Current VS=5V 10 pA

Threshold Current VS=5V 10 pA

Discharge Leakage VS= 12V 1.0 100 nA

t Timing Accuracy SW 2, 4 Closed

VS= 1.5V

=5V

V

S

= 12V

V

S

∆t/∆V

∆t/∆T Timing Shift with

f

A

f

MAX

Timing Shift with Supply VS=5V±1V 0.3 %/V

S

V

=5V

S

Temperature

−40˚C ≤ T ≤ +85˚C

Astable Frequency SW 1, 3 Closed, VS= 12V 4.0 4.8 5.6 kHz

Maximum Frequency Max. Freq. Test Circuit, VS= 5V 3.0 MHz

unless otherwise noted

S

=1mA

DIS

=10mA

DIS

0.8

2.9

7.4

1.0

4.4

10.5

0.4

3.7

0.4

0.4

0.9

1.0

1.0

(Limits)

50
100
150

1.0

3.3

8.0

75
150

0.2

0.3

1.0

150
250
400

1.2

3.8

8.6

150
300

0.4

0.6

2.0

µA

V

mV

V

1.25

4.7

V

11.3

0.5

4.0

0.7

0.75

1.1

1.1

1.1

0.6

4.3

1.0

1.1

1.25

1.20

1.25

V

V

ms

75 ppm/˚C

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Electrical Characteristics (Notes 1, 2)

Test Circuit, T = 25˚C, all switches open, RESET to V

LMC555

Symbol Parameter Conditions Min Typ Max Units

tR,t

t

PD

F

Output Rise and
Fall Times

Max. Freq. Test Circuit

= 5V, CL=10pF

V

S

Trigger Propagation Delay VS= 5V, Measure Delay

from Trigger to Output

Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified.

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. Electrical Characteristics state DC andAC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.

Note 3: See AN-450 for other methods of soldering surface mount devices, and also AN-1112 for micro SMD considerations.

Note 4: If the RESET pin is to be used at temperatures of −20˚C and below V

Note 5: For device pinout please refer to table 1

unless otherwise noted (Continued)

S

is required to be 2.0V or greater.

S

15 ns

100 ns

(Limits)

Test Circuit (Note 5)

00866902

Maximum Frequency Test Circuit (Note 5)

TABLE 1. Package Pinout Names vs. Pin Function

Pin Function Package Pin numbers

8-Pin SO,MSOP, and MDIP 8-Bump micro SMD

GND 1 A3

Trigger

2B3

Output 3 C3

Reset

4C2

Control Voltage 5 C1

Threshold 6 B1

Discharge 7 A1

+

V

8A2

00866903

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Application Info

MONOSTABLE OPERATION

In this mode of operation, the timer functions as a one-shot
(Figure 1). The external capacitor is initially held discharged
by internal circuitry. Upon application of a negative trigger
pulse of less than 1/3 V
is set which both releases the short circuit across the capaci­tor and drives the output high.

to the Trigger terminal, the flip-flop

S

When the reset function is not use, it is recommended that it
be connected to V

to avoid any possibility of false triggering.

+

Figure 3 is a nomograph for easy determination of RC values
for various time delays.

Note: In monstable operation, the trigger should be driven high before the

end of timing cycle.

00866911

LMC555

00866904

FIGURE 1. Monostable (One-Shot)

The voltage across the capacitor then increases exponen­tially for a period of t

= 1.1 RAC, which is also the time that

H

the output stays high, at the end of which time the voltage
equals 2/3 V

. The comparator then resets the flip-flop which

S

in turn discharges the capacitor and drives the output to its
low state. Figure 2 shows the waveforms generated in this
mode of operation. Since the charge and the threshold level
of the comparator are both directly proportional to supply
voltage, the timing internal is independent of supply.

VCC= 5V Top Trace: Input 5V/Div.

TIME = 0.1 ms/Div. Middle Trace: Output 5V/Div.

= 9.1kΩ Bottom Trace: Capacitor Voltage 2V/Div.

R

A

C = 0.01µF

00866910

FIGURE 2. Monostable Waveforms

Reset overrides Trigger, which can override threshold.
Therefore the trigger pulse must be shorter than the desired

. The minimum pulse width for the Trigger is 20ns, and it is

t

H

400ns for the Reset. During the timing cycle when the output
is high, the further application of a trigger pulse will not effect
the circuit so long as the trigger input is returned high at least
10µs before the end of the timing interval. However the
circuit can be reset during this time by the application of a
negative pulse to the reset terminal. The output will then
remain in the low state until a trigger pulse is again applied.

FIGURE 3. Time Delay

ASTABLE OPERATION

If the circuit is connected as shown in Figure 4 (Trigger and
Threshold terminals connected together) it will trigger itself
and free run as a multivibrator. The external capacitor
charges through R

and discharges through RB. Thus

A+RB

the duty cycle may be precisely set by the ratio of these two
resistors.

00866905

FIGURE 4. Astable (Variable Duty Cycle Oscillator)

In this mode of operation, the capacitor charges and dis­charges between 1/3 V

and 2/3 VS. As in the triggered

S

mode, the charge and discharge times, and therefore the
frequency are independent of the supply voltage.

Figure 5 shows the waveform generated in this mode of
operation.

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Application Info (Continued)

LMC555

VCC= 5V Top Trace: Output 5V/Div.

TIME = 20 µs/Div. Bottom Trace: Capacitor Voltage 1V/Div.

= 3.9kΩ

R

A

=9kΩ

R

B

C = 0.01µF

00866912

FIGURE 5. Astable Waveforms

The charge time (output high) is given by

= 0.693 (RA+RB)C

t

1

And the discharge time (output low) by:

t2= 0.693 (RB)C

Thus the total period is:

T=t

= 0.693 (RA+RB)C

1+t2

The frequency of oscillation is:

Figure 6 may be used for quick determination of these RC
Values. The duty cycle, as a fraction of total period that the
output is low, is:

VCC= 5V Top Trace: Input 4V/Div.

TIME = 20 µs/Div. Middle Trace: Output 2V/Div.

= 9.1 kΩ Bottom Trace: Capacitor 2V/Div.

R

A

C = 0.01µF

00866914

FIGURE 7. Frequency Divider Waveforms

PULSE WIDTH MODULATOR

When the timer is connected in the monostable mode and
triggered with a continuous pulse train, the output pulse
width can be modulated by a signal applied to the Control
Voltage Terminal. Figure 8 shows the circuit, and in Figure 9
are some waveform examples.

00866913

FIGURE 6. Free Running Frequency

FREQUENCY DIVIDER

The monostable circuit of Figure 1 can be used as a fre­quency divider by adjusting the length of the timing cycle.
Figure 7 shows the waveforms generated in a divide by three
circuit.

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FIGURE 8. Pulse Width Modulator

VCC= 5V Top Trace: Modulation 1V/Div.

TIME = 0.2 ms/Div. Bottom Trace: Output Voltage 2V/Div.

= 9.1 kΩ

R

A

C = 0.01µF

00866915

FIGURE 9. Pulse Width Modulator Waveforms

00866920

LMC555

Application Info (Continued)

PULSE POSITION MODULATOR

This application uses the timer connected for astable opera­tion, as in Figure 10, with a modulating signal again applied
to the control voltage terminal. The pulse position varies with
the modulating signal, since the threshold voltage and hence
the time delay is varied. Figure 11 shows the waveforms
generated for a triangle wave modulation signal.

00866921

FIGURE 10. Pulse Position Modulator

50% DUTY CYCLE OSCILLATOR

The frequency of oscillation is

f = 1/(1.4 R

C)

C

FIGURE 12. 50% Duty Cycle Oscillator

micro SMD Marking Orientation

Top View

00866906

VCC= 5V Top Trace: Modulation Input 1V/Div.

TIME = 0.1 ms/Div. Bottom Trace: Output Voltage 2V/Div.

= 3.9 kΩ

R

A

=3kΩ

R

B

C = 0.01µF

00866916

FIGURE 11. Pulse Position Modulator Waveforms

Bumps are numbered counter-clockwise

00866923

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Physical Dimensions inches (millimeters) unless otherwise noted

LMC555

Molded Small Outline (SO) Package (M)

NS Package Number M08A

8-Lead (0.118” Wide) Molded Mini Small Outline Package

NS Package Number MUA08A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

LMC555

Molded Dual-in-line Package (N)

NS Package Number N08E

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

LMC555 CMOS Timer

NOTES: UNLESS OTHERWISE SPECIFIED

1. EPOXY COATING

2. 63Sn/37Pb EUTECTIC BUMP

3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.

4. PIN A1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION. REMAINING PINS ARE NUMBERED
COUNTERCLOCKWISE.

5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS
PACKAGE HEIGHT.

6. REFERENCE JEDEC REGISTRATION MO-211, VARIATION BC.

micro SMD Package

NS Package Number BPA08EFB

= 1.387 X2= 1.412 X3= 0.850

X

1

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the right at any time without notice to change said circuitry and specifications.

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