Datasheet LM8272MMX Datasheet (NSC)

December 2002

LM8272 Dual
RRIO, High Output Current & Unlimited Cap Load Op
Amp in Miniature Package

LM8272 Dual RRIO, High Output Current & Unlimited Cap Load Op Amp in Miniature Package

General Description

The LM8272 is a Rail-to-Rail input and output Op Amp which
can operate with a wide supply voltage range. This device
has high output current drive, greater than Rail-to-Rail input
common mode voltage range, unlimited capacitive load drive
capability while requiring only 0.95mA/channel supply cur­rent. It is specifically designed to handle the requirements of
flat panel TFT panel V
being suitable for other low power, and medium speed ap­plications which require ease of use and enhanced perfor­mance over existing devices.

Greater than Rail-to-Rail input common mode voltage range
with 50dB of Common Mode Rejection, allows high side and
low side sensing, among many applications, without having
any concerns over exceeding the range and no compromise
in accuracy. Exceptionally wide operating supply voltage
range of 2.5V to 24V alleviates any concerns over function­ality under extreme conditions and offers flexibility of use in
multitude of applications. In addition, most device param­eters are insensitive to power supply variations; this design
enhancement is yet another step in simplifying its usage.

The LM8272 is offered in the 8-pin MSOP package.

driver applications as well as

COM

Connection Diagram

8-Pin MSOP

Features

(VS= 12V, TA= 25˚C, Typical values unless specified).

n GBWP 15MHz
n Wide supply voltage range 2.5V to 24V
n Slew rate 15V/µs
n Supply current/channel 0.95mA
n Cap load tolerance Unlimited
n Output short circuit current
n Output current (1V from rails)
n Input common mode voltage 0.3V beyond rails
n Input voltage noise 15nV/
n Input current noise 1.4pA/

±

130mA

±

65mA

Applications

n TFT-LCD flat panel V
n A/D converter buffer
n High side/low side sensing
n Headphone amplifier

Large Signal Step Response for Various Cap. Load

COM

driver

Top View

10130863

10130899

Ordering Information

Package Part Number Package Marking Transport Media NSC Drawing

8-Pin MSOP LM8272MM

LM8272MMX 3.5k Unit Tape and Reel

© 2002 National Semiconductor Corporation DS101308 www.national.com

A60

1k Unit Tape and Reel

MUA08A

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

LM8272 Dual

ESD Tolerance

Differential +/−10V

V

IN

Output Short Circuit Duration (Notes 3, 11)

Supply Voltage (V

Voltage at Input/Output pins V

Storage Temperature Range −65˚C to +150˚C

+-V−

) 27V

2KV (Note 2)

200V(Note 9)

+

+0.3V, V−−0.3V

Junction Temperature (Note 4) +150˚C

Soldering Information:

Infrared or Convection (20 sec.) 235˚C

Wave Soldering (10 sec.) 260˚C

Operating Ratings

Supply Voltage (V+-V−) 2.5V to 24V

Junction Temperature Range(Note 4) −40˚C to +85˚C

Package Thermal Resistance, θ

8-Pin MSOP 235C/W

,(Note 4)

JA

5V Electrical Characteristics

Unless otherwise specified, all limited guaranteed for TJ= 25˚C, V+= 5V, V−= 0V, VCM= 0.5V, VO=V+/2, and

>

1MΩ to V−. Boldface limits apply at the temperature extremes.

R

L

Symbol Parameter Condition

V

OS

TC V

Input Offset Voltage VCM= 0.5V & VCM= 4.5V +/−0.7 +/−5

Input Offset Average Drift VCM= 0.5V & VCM= 4.5V

OS

Typ

(Note 5)

+/−2 — µV/˚C

(Note 12)

I

B

I

OS

Input Bias Current (Note 7) —

Input Offset Current 20 250

CMRR Common Mode Rejection Ratio VCMstepped from 0V to 5V 80 64

+

+PSRR Positive Power Supply Rejection Ratio V

from 4.5V to 13V 100 78

CMVR Input Common-Mode Voltage Range CMRR>50dB −0.3 −0.1

5.3 5.1

A

VOL

V

O

I

SC

Large Signal Voltage Gain VO= 0.5 to 4.5V,

= 10kΩ to V+/2

R

L

Output Swing
High

Output Swing
Low

Output Short Circuit Current Sourcing to V

RL= 10kΩ to V

I

SOURCE

R

I

SINK

= 5mA 4.85 4.70

= 10kΩ to V

L

= 5mA 300 350

−

−

+

80 64

4.93 4.85

215 250 mV

100 —

VID= 200mV (Note 10)

Sinking to V

+

100 —

VID= −200mV (Note 10)

I

I

OUT

S

Output Current VID=±200mV, VO= 1V from rails

Supply Current (Both Channel) No load, VCM= 0.5V 1.8 2.3

SR Slew Rate (Note 8) AV= +1, VI=5V

f

u

Unity Gain Frequency VI= 10mVp, RL=2KΩ to V+/2 7.5 — MHz

PP

±

55 — mA

12 — V/µs

GBWP Gain-Bandwidth Product f = 50KHz 13 — MHz

Phi

e

m

n

Phase Margin VI= 10mVp, RL=2kΩ to V+/2 55 — deg

Input-Referred Voltage Noise f = 2KHz, RS=50Ω 15 — nV/

Limit

(Note 6)

+/− 7

±

2.00

±

2.70

400

61

74

0.0

5.0

60

2.8

Units

mV

max

µA

max

nA

max

dB

min

dB

min

V

max

V

min

dB

min

V

min

max

mA

mA

max

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5V Electrical Characteristics (Continued)

Unless otherwise specified, all limited guaranteed for TJ= 25˚C, V+= 5V, V−= 0V, VCM= 0.5V, VO=V+/2, and

>

1MΩ to V−. Boldface limits apply at the temperature extremes.

R

L

Symbol Parameter Condition

i

n

Input-Referred Current Noise f = 2KHz 1.4 — pA/

Typ

(Note 5)

(Note 6)

Limit

LM8272 Dual

Units

f

max

Full Power Bandwidth ZL= (20pF || 10kΩ)toV+/2 700 — KHz

12V Electrical Characteristics

Unless otherwise specified, all limited guaranteed for TJ= 25˚C, V+= 12V, V−= 0V, VCM= 6V, VO= 6V, and

>

1MΩ to V−. Boldface limits apply at the temperature extremes.

R

L

Symbol Parameter Condition

V

OS

TC V

Input Offset Voltage VCM= 0.5V & VCM= 11.5V +/−0.7 +/−7

Input Offset Average Drift VCM= 0.5V & VCM= 11.5V

OS

Typ

(Note 5)

+/−2 — µV/˚C

(Note 12)

I

B

I

OS

Input Bias Current (Note 7) —

Input Offset Current 30 275

CMRR Common Mode Rejection Ratio VCMstepped from 0V to 12V 88 74

+

+PSRR Positive Power Supply Rejection Ratio V

−PSRR Negative Power Supply Rejection

from 4.5V to 13V, VCM= 0.5V 100 78

85 — dB

Ratio

>

CMVR Input Common-Mode Voltage Range CMRR

50dB −0.3 −0.1

12.3 12.1

A

VOL

V

O

I

SC

Large Signal Voltage Gain VO=1Vto11V

= 10kΩ to V+/2

R

L

Output Swing
High

Output Swing
Low

Output Short Circuit Current Sourcing to V

RL10kΩ to V+/2 11.8 11.7

I

SOURCE

R

I

SINK

= 5mA 11.6 11.5

= 10kΩ to V+/2 0.25 0.3

L

= 5mA .40 .45

−

83 74

130 110

VID= 200mV (Note 10)

Sinking to V

+

130 110

VID= 200mV (Note 10)

I

I

OUT

S

Output Current VID=±200mV, VO= 1V from rails

Supply Current (Both Channel) No load, VCM= 0.5V 1.9 2.4

SR Slew Rate

(Note 8)

R

OUT

f

u

Close Loop Output Resistance AV= +1, f = 100KHz 3 — Ω

Unity Gain Frequency VI= 10mVp, RL=2kΩ to V+/2 8 — MHz

= +1, VI= 10VPP,CL= 10pF 15 —

A

V

A

= +1, VI= 10VPP,CL= 0.1µF 1 —

V

±

65 — mA

GBWP Gain-Bandwidth Product f = 50KHz 15 — MHz

Phi

m

GM Gain Margin V

Phase Margin VI= 10mVp, RL=2kΩ to V+/2 57 — Deg

= 10mVp, RL=2kΩ to V+/2 20 — dB

I

Limit

(Note 6)

+/− 9

±

2.00

±

2.80

550

72

74

0

12.0

70

2.9

Units

mV

max

µA

max

nA

max

dB

min

dB

min

V

max

V

min

dB

min

V

min

V

max

mA
min

mA

max

V/µs

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12V Electrical Characteristics (Continued)

Unless otherwise specified, all limited guaranteed for TJ= 25˚C, V+= 12V, V−= 0V, VCM= 6V, VO= 6V, and

>

1MΩ to V−. Boldface limits apply at the temperature extremes.

R

L

Symbol Parameter Condition

LM8272 Dual

−3dB BW Small Signal -3db Bandwidth A

e

n

Input-Referred Voltage Noise f = 2KHz, RS=50Ω 15 — nV/

= +1, RL=2kΩ to V+/2 12.5 —

V

= +1, RL= 600Ω to V+/2 10.5 —

V

A

= +10, RL= 600Ω to V+/2 1.0 —

V

(Note 5)

Typ

Limit

(Note 6)

Units

MHzA

i

n

f

max

THD+N Total Harmonic Distortion +Noise A

CT Rej. Cross-Talk Rejection f = 5MHz, Driver R

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Rating indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.

Note 2: Human body model, 1.5kΩ in series with 100pF.

Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the

maximum allowed junction temperature of 150˚C.

Note 4: The maximum power dissipation is a function of T
P

D

Note 5: Typical Values represent the most likely parametric norm.

Note 6: All limits are guaranteed by testing or statistical analysis.

Note 7: Positive current corresponds to current flowing into the device.

Note 8: Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.

Note 9: Machine Model, 0Ω is series with 200pF.

Note 10: Short circuit test is a momentary test. See Note 11.

Note 11: Output short circuit duration is infinite for V

Note 12: Offset voltage average drift determined by dividing the change in V

Input-Referred Current Noise f = 2KHz 1.4 — pA/

Full Power Bandwidth ZL= (20pF || 10kΩ)toV+/2 300 — KHz

= +2, RL=2kΩ to V+/2

V

=8VPP,VS=±5V

V

O

(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is

=(TJ(max) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.

J

≤ 6V at room temperature and below. For V

S

at temperature extremes into the total temperature change.

OS

= 10kΩ to V+/2 68 — dB

L

>

6V, allowable short circuit duration is 1.5ms.

S

0.02 — %

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Typical Performance Charateristics

VOSDistribution VOSvs. VCMfor 3 Representative Units

101308A2 10130830

VOSvs. VCMfor 3 Representative Units VOSvs. VCMfor 3 Representative Units

LM8272 Dual

10130829 10130831

VOSvs. VSfor 3 Representative Units VOSvs. VSfor 3 Representative Units

10130884

10130883

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Typical Performance Charateristics (Continued)

V

vs. VSfor 3 Representative Units IBvs. V

OS

LM8272 Dual

10130882 10130871

IBvs. V

S

ISvs. V

S

CM

101308A3

ISvs. V

CM

10130875

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ISvs. V

10130872

S

10130874

Typical Performance Charateristics (Continued)

I

vs. V

S

S

LM8272 Dual

CMRR vs. Frequency

10130873

10130887

+PSRR vs. Frequency −PSRR vs. Frequency

10130888 10130889

Open Loop Gain/Phase for Various Supplies Closed Loop Frequency Response for Various Gains

10130893

10130896

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Typical Performance Charateristics (Continued)

LM8272 Dual

Closed Loop Frequency Response for Various Gains Closed Loop Frequency Response for Various Gains R

10130895

10130894

Maximum Output Swing vs. Load (1% Distortion) Maximum Output Swing vs. Frequency (1% Distortion)

L

10130876

Closed Loop Small Signal Frequency Response for

Various C

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L

10130886

10130877

Overshoot vs. Cap Load

10130878

Typical Performance Charateristics (Continued)

LM8272 Dual

Settling Time (

V

±

1%) & Slew Rate vs. Cap Load V

10130879

from V−vs. I

OUT

SINK

Step Response for Various Amplitudes

from V+vs. I

OUT

SOURCE

10130898

101308A0

10130897

Step Response for Various Amplitudes Large Signal Step Response for Various Cap Loads

101308A1

10130899

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Typical Performance Charateristics (Continued)

THD+N vs. Input Amplitude for Various Frequency Input Referred Noise Density

LM8272 Dual

10130892 10130880

Closed Loop Output Impedance vs. Frequency Crosstalk Rejection vs. Frequency

10130885

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10130881

Application Notes

BLOCK DIAGRAM AND OPEATIONAL DESCRIPTION A) INPUT STAGE:

As can be seen from the simplified schematic in Figure 1, the
input stage consists of two distinct differential pairs (Q1-Q2
and Q3-Q4) in order to accommodate the full Rail-to-Rail
input common mode voltage range. The voltage drop across
R5, R6, R7 and R8 is kept to less than 200mV in order to
allow the input to exceed the supply rails. Q13 acts as a
switch to steer current away from Q3-Q4 and into Q1-Q2, as
the input increases beyond 1.4 of V
signal path from the bottom stage differential pair to the top
one and causes a subsequent increase in the supply current.

In transitioning from one stage to another, certain input stage
parameters (V

OS,Ib,IOS,en

on which differential pair is “on” at the time. Input Bias
current, I

, will change in value and polarity as the input

b

crosses the transition region. In addition, parameter such as
PSRR and CMRR which involve the input offset voltage will
also be effected by changes in V
pair transition region.

FIGURE 1. Simplified Schematic Diagram

The input stage is protected with the combination of R9-R10
and D1, D2, D3 and D4 against differential input over­voltages. This fault condition could otherwise harm the dif­ferential pairs or cause offset voltage shift in case of pro­longed over voltage. As shown in Figure 2, if this voltage

±

reaches approximately

1.4V at 25˚C, the diodes turn on
and current flow is limited by the internal series resistors (R9
and R10). The Absolute Maximum Rating of
tial on V

still needs to be observed. With temperature

IN

variation, the point were the diodes turn on will change at the
rate of 5mV/˚C

+

. This in turn shifts the

, and in) are determined based

across the differential

CM

10130870

±

10V differen-

101308A4

FIGURE 2. Input Stage Current vs. Differential Input

Voltage

B) OUTPUT STAGE:

The output stage (see Figure 1) is comprised of complimen­tary NPN and PNP common-emitter stages to permit voltage
swing to within a V

of either supply rail. Q9 supplies the

ce(sat)

sourcing and Q10 supplies the sinking current load. Output
current limiting is achieved by limiting the V

of Q9 and Q10;

ce

using this approach to current limiting, alleviates the draw
back to the conventional scheme which requires one V
reduction in output swing.

The frequency compensation circuit includes Miller capaci­tors from collector to base of each output transistor (see
Figure 1,C

comp9

and C

). At light capacitive loads, the

comp10

high frequency gain of the output transistors is high, and the
Miller effect increases the effective value of the capacitors
thereby stabilizing the Op Amp. Large capacitive loads
greatly decrease the high frequency gain of the output tran­sistors thus lowering the effective internal Miller capacitance

- the internal pole frequency increases at the same time a
low frequency pole is created at the Op Amp output due to
the large load capacitor. In this fashion, the internal dominant
pole compensation, which works by reducing the loop gain to
less than 0dB when the phase shift around the feedback
loop is more than 180˚, varies with the amount of capacitive
load and becomes less dominant when the load capacitor
has increased enough. Hence the Op Amp is very stable
even at high values of load capacitance resulting in the
uncharacteristic feature of stability under all capacitive loads.

−

C) OUTPUT VOLTAGE SWING CLOSE TO V

:

The LM8272’s output stage design allows voltage swings to
within millivolts of either supply rail for maximum flexibility
and improved useful range. Because of this design architec­ture, as can be seen from Figure 1 diagram, with Output
approaching either supply rail, either Q9 or Q10 Collector­Base junction reverse bias will decrease. With output less
than a V

from either rail, the corresponding output transis-

be

tor operates near saturation. In this mode of operation, the
transistor will exhibit higher junction capacitance and lower f
which will reduce Phase Margin. With the Noise Gain (NG =
1 + Rf/Rg, Rf & Rg are external gain setting resistors) of 2 or
higher, there is sufficient Phase Margin that this reduction (in
Phase Margin) is of no consequence. However, with lower

LM8272 Dual

be

t

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Application Notes (Continued)

Noise Gain (
supply rail, if the output loading is light, the Phase Margin
reduction could result in unwanted oscillations.

LM8272 Dual

In the case of the LM8272, due to inherent architectural
specifics, the oscillation occurs only with respect to Q10
when output swings to within 150mV of V
collector current is larger than its idle value of a few micro­amps, the Phase Margin loss becomes insignificant. In this
case, 300µA is the required Q10 collector current to remedy
this situation. Therefore, when all the aforementioned critical
conditions are present at the same time (NG
150mV from supply rails, & output load is light) it is possible
to ensure stability by adding a load resistor to the output to
provide the necessary Q10 minimum Collector Current
(300µA).

For 12V (or
tor from the output to V
current and ensure stability. This is equivalent to about 15%
increase in total quiescent power dissipation.

DRIVING CAPACTIVE LOADS:

The LM8272 is specifically designed to drive unlimited ca­pacitive loads without oscillations (see Settling Time and
Overshoot vs. Cap Load plots in the typical performance
characteristics section). In addition, the output current han­dling capability of the device allows for good slewing char­acteristics even with large capacitive loads (Settling Time
and Slew Rate vs. Cap Load plot). The combination of these
features is ideal for applications such as TFT flat panel
buffers, A/D converter input amplifiers, etc.

However, as in most Op Amps, addition of a series isolation
resistor between the Op Amp and the capacitive load im­proves the settling and overshoot performance.

Output current drive is an important parameter when driving
capacitive loads. This parameter will determine how fast the
output voltage can change. Referring to the Settling Time
and Slew Rate vs. Cap Load plots (typical performance
characteristics section), two distinct regions can be identi­fied. Below about 10,000pF, the output Slew Rate is solely
determined by the Op Amp’s compensation capacitor value
and available current into that capacitor. Beyond 10nF, the
Slew Rate is determined by the Op Amp’s available output
current. An estimate of positive and negative slew rates for
loads larger than 100nF can be made by dividing the short
circuit current value by the capacitor.

<

2) and with less than 150mV voltage to the

−

. However, if Q10

±

6V) operation, for example, add a 39kΩ resis-

+

to cause 300µA output sinking

ing to loads tied between the output and ground. In each
case, the intersection of the device plot at the appropriate
temperature with the load line would be the typical output
swing possible for that load. For example, a 600Ω load can
accommodate an output swing to within 100mV of V
250mV of V

+

(VS=±5V) corresponding to a typical 9.65V

−

and to

PP

unclipped swing.

<

2, V

OUT

<

10130890

FIGURE 3. Steady State Output Sourcing

Characteristics with Load Lines

ESTIMATING THE OUTPUT VOLTAGE SWING

It is important to keep in mind that the steady state output
current will be less than the current available when there is
an input overdrive present. For steady state conditions, Fig-
ure 3 and Figure 4 plots can be used to predict the output
swing. These plots also show several load lines correspond-

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10130891

FIGURE 4. Steady State Output Sinking Characteristics

with Load Lines

LM8272 Dual

Application Notes (Continued)

OUTPUT SHORT CIRCUIT CURRENT AND DISSIPATION ISSUES:

The LM8272 output stage is designed for maximum output
current capability. Even though momentary output shorts to
ground and either supply can be tolerated at all operating
voltages, longer lasting short conditions can cause the junc­tion temperature to rise beyond the absolute maximum rat­ing of the device, especially at higher supply voltage condi­tions. Below supply voltage of 6V, output short circuit
condition can be tolerated indefinitely.

With the Op Amp tied to a load, the device power dissipation
consists of the quiescent power due to the supply current
flow into the device, in addition to power dissipation due to
the load current. The load portion of the power itself could
include an average value (due to a DC load current) and an
AC component. DC load current would flow if there is an
output voltage offset, or the output AC average current is
non-zero, or if the Op Amp operates in a single supply
application where the output is maintained somewhere in the
range of linear operation. Therefore:

P

total=PQ+PDC+PAC

PQ=IS·V

P

DC=IO

P

AC

S

·(Vr-Vo) DC Load Power

= See Table 1 below AC Load Power

where:

: Supply Current

I

S

: Total Supply Voltage (V+-V−)

V

S

V

: Average Output Voltage

O

:V+for sourcing and V−for sinking current

V

r

Table 1 below shows the maximum AC component of the
load power dissipated by the Op Amp for standard Sinusoi­dal, Triangular, and Square Waveforms:

Op Amp Quiescent Power

Dissipation

TABLE 1. Normalized AC Power Dissipated in the

Output Stage for Standard Waveforms

PAC(W.Ω/V2)

Sinusoidal Triangular Square

50.7 x 10

−3

46.9 x 10

The table entries are normalized to V

−3

62.5 x 10

2

/RL. To figure out the

S

−3

AC load current component of power dissipation, simply
multiply the table entry corresponding to the output wave­form by the factor V

2

/RL. For example, with±12V supplies,

S

a 600Ω load, and triangular waveform power dissipation in
the output stage is calculated as:

= (46.9 x 10−3) · [242/600] = 45.0mW

P

AC

OTHER APPLICATION HINTS:

The use of supply decoupling is mandatory in most applica­tions. As with most relatively high speed/high output current
Op Amps, best results are achieved when each supply line is
decoupled with two capacitors; a small value ceramic ca­pacitor (∼0.01µF) placed very close to the supply lead in

>

addition to a large value Tantalum or Aluminum (

4.7µF).
The large capacitor can be shared by more than one device
if necessary. The small ceramic capacitor maintains low
supply impedance at high frequencies while the large ca­pacitor will act as the charge “bucket” for fast load current
spikes at the Op Amp output. The combination of these
capacitors will provide supply decoupling and will help keep
the Op Amp oscillation free under any load.

LM8272 ADVANTAGES:

Compared to other Rail-to-Rail Input/Output devices, the
LM8272 offers several advantages such as:

Improved cross over distortion

•

Nearly constant supply current throughout the output

•

voltage swing range and close to either rail.
Nearly constant Unity gain frequency (fu) and Phase

•

Margin (Phi

) for all operating supplies and load condi-

m

tions.
No output phase reversal under input overload condition.

•

www.national.com13

Physical Dimensions inches (millimeters)

unless otherwise noted

8-Pin MSOP

NS Package Number MUA08A

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LM8272 Dual RRIO, High Output Current & Unlimited Cap Load Op Amp in Miniature Package

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