Page 1
LM8261 Single
RRIO, High Output Current & Unlimited Cap Load Op
Amp in SOT23-5
LM8261 Single RRIO, High Output Current & Unlimited Cap Load Op Amp in SOT23-5
April 2000
General Description
The LM8261 is a Rail-to-Rail input and output OpAmpwhich
can operate with a wide supply voltage range. This device
has high output current drive, greater than Rail-to-Rail input
common mode voltage range,unlimitedcapacitiveloaddrive
capability, and provides tested and guaranteed high speed
and slew rate while requiring only 0.97mA supply current. It
is specifically designed to handle the requirements of flat
panel TFT panel V
suitable for other low power,andmediumspeedapplications
which require ease of use and enhanced performance over
existing devices.
Greater than Rail-to-Rail input common mode voltage range
with 50dB of Common Mode Rejection, allows high side and
low side sensing, among many applications, without having
any concerns over exceeding the range and no compromise
in accuracy. Exceptionally wide operating supply voltage
range of 2.5V to 30V alleviates any concerns over functionality under extreme conditions and offers flexibility of use in
multitude of applications. In addition, most device parameters are insensitive to power supply variations; this design
enhancement is yet another step in simplifying its usage.
The output stage has low distortion (0.05% THD+N) and can
supply a respectable amount of current (15mA) with minimal
headroom from either rail (300mV).
driver applications as well as being
COM
The LM8261 is offered in the space saving SOT23-5 package.
Features
(VS=5V,TA= 25˚C, Typical values unless specified).
n GBWP 21MHz
n Wide supply voltage range 2.5V to 30V
n Slew rate 12V/µs
n Supply current 0.97 mA
n Cap load limit Unlimited
n Output short circuit current +53mA/−75mA
n +/−5% Settling time 400ns (500pF, 100mV
n Input common mode voltage 0.3V beyond rails
n Input voltage noise 15nV/
n Input current noise 1pA/
n THD+N
PP
<
step)
0.05%
Applications
n TFT-LCD flat panel V
n A/D converter buffer
n High side/low side sensing
n Headphone amplifier
COM
driver
Output Response with Heavy Capacitive Load
DS101084-37
© 2000 National Semiconductor Corporation DS101084 www.national.com
Page 2
Connection Diagram
LM8261
SOT23-5
DS101084-62
Top View
Ordering Information
Package Ordering Info Pkg Marking Supplied AS NSC Drawing
5-Pin SOT-23 LM8261M5
LM8261M5X 3K Units Tape and Reel
A45A
1K Units Tape and Reel
MA05B
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Page 3
LM8261
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance
V
Differential +/−10V
IN
Output Short Circuit Duration (Notes 3, 11)
Supply Voltage (V
+-V−
) 32V
Voltage at Input/Output pins V
2KV (Note 2)
200V(Note 9)
+
+0.8V, V−−0.8V
Junction Temperature (Note 4) +150˚C
Soldering Information:
Infrared or Convection (20 sec.) 235˚C
Wave Soldering (10 sec.) 260˚C
Operating Ratings
Supply Voltage (V+-V−) 2.5V to 30V
Junction Temperature Range(Note 4) −40˚C to +85˚C
Package Thermal Resistance, θ
SOT23-5 325˚C/W
,(Note 4)
JA
Storage Temperature Range −65˚C to +150˚C
2.7V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25˚C, V+= 2.7V, V−= 0V, VCM= 0.5V, VO=V+/2, and
>
R
1MΩ to V−. Boldface limits apply at the temperature extremes.
L
Symbol Parameter Condition
V
OS
TC V
Input Offset Voltage VCM= 0.5V & VCM= 2.2V +/−0.7 +/−5
Input Offset Average Drift VCM= 0.5V & VCM= 2.2V
OS
(Note 12)
I
B
Input Bias Current VCM= 0.5V
(Note 7)
= 2.2V
V
CM
(Note 7)
I
OS
CMRR Common Mode Rejection Ratio V
+PSRR Positive Power Supply
Input Offset Current VCM= 0.5V & VCM= 2.2V 20 250
stepped from 0V to 1.0V 100 76
CM
stepped from 1.7V to 2.7V 100
V
CM
V
stepped from 0V to 2.7V 70 58
CM
+
V
= 2.7V to 5V 104 78
Rejection Ratio
CMVR Input Common-Mode Voltage
CMRR
>
50dB −0.3 −0.1
Range
A
VOL
V
O
Large Signal Voltage Gain VO= 0.5 to 2.2V,
= 10K to V
R
L
V
= 0.5 to 2.2V,
O
=2KtoV
R
L
Output Swing
RL= 10K to V
−
−
−
High
−
−
Output Swing
=2KtoV
R
L
R
= 10K to V
L
Low
I
SC
Output Short Circuit Current Sourcing to V
−
VID= 200mV (Note 10)
Sinking to V
+
VID= −200mV (Note 10)
I
S
SR Slew Rate (Note 8) A
Supply Current No load, VCM= 0.5V 0.95 1.20
= +1,VI=2V
V
PP
Typ
(Note 5)
+/−2 – µV/C
−1.20 −2.00
+0.49 +1.00
3.0 2.8
78 70
73 67
2.59 2.49
2.53 2.45
90 100
48 30
65 50
9 – V/µs
Limit
(Note 6)
+/−7
−2.70
+1.60
2.46
2.41
1.50
400
60
50
74
0.0
2.7
67
63
120
20
30
Units
mV
max
µA
max
nA
max
dB
min
dB
min
V
max
V
min
dB
min
dB
min
V
min
mV
max
mA
min
mA
min
mA
max
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Page 4
2.7V Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ= 25˚C, V+= 2.7V, V−= 0V, VCM= 0.5V, VO=V+/2, and
LM8261
>
R
1MΩ to V−. Boldface limits apply at the temperature extremes.
L
Symbol Parameter Condition
f
u
Unity Gain-Frequency VI= 10mV, RL=2KΩto V+/2 10 – MHz
Typ
(Note 5)
GBWP Gain Bandwidth Product f = 50KHz 21 15.5
Phi
e
m
n
Phase Margin VI= 10mV 50 – Deg
Input-Referred Voltage Noise f = 2KHz, RS=50Ω 15 – nV/
Limit
(Note 6)
14
Units
MHz
min
i
n
f
max
Input-Referred Current Noise f = 2KHz 1 pA/
Full Power Bandwidth ZL= (20pF || 10KΩ)toV+/2 1 – MHz
5V Electrical Characteristics
Unless otherwise specified, all limited guaranteed for TJ= 25˚C, V+= 5V, V−= 0V, VCM= 1V, VO=V+/2, and
>
R
1MΩ to V−. Boldface limits apply at the temperature extremes.
L
Symbol Parameter Condition
V
OS
TC V
Input Offset Voltage VCM=1V&VCM= 4.5V +/−0.7 +/−5
Input Offset Average Drift VCM=1V&VCM= 4.5V
OS
(Note 12)
I
B
Input Bias Current VCM=1V
(Note 7)
= 4.5V
V
CM
(Note 7)
I
OS
CMRR Common Mode Rejection Ratio V
+PSRR Positive Power Supply Rejection
Input Offset Current VCM=1V&VCM= 4.5V 20 250
stepped from 0V to 3.3V 110 84
CM
stepped from 4V to 5V 100 –
V
CM
V
stepped from 0V to 5V 80 64
CM
+
V
= 2.7V to 5V, VCM= 0.5V 104 78
Ratio
CMVR Input Common-Mode Voltage Range CMRR
A
VOL
V
O
Large Signal Voltage Gain VO= 0.5 to 4.5V,
Output Swing
>
50dB −0.3 −0.1
= 10K to V
R
L
= 0.5 to 4.5V,
V
O
=2KtoV
R
L
RL= 10K to V
−
−
−
High
−
−
Output Swing
=2KtoV
R
L
R
= 10K to V
L
Low
I
SC
Output Short Circuit Current Sourcing to V
−
VID= 200mV (Note 10)
Sinking to V
+
VID= −200mV (Note 10)
Typ
(Note 5)
+/−2 – µV/˚C
−1.18 −2.00
+0.49 +1.00
5.3 5.1
84 74
80 70
4.87 4.75
4.81 4.70
86 125
53 35
75 60
Limit
(Note 6)
+/− 7
−2.70
+1.60
400
72
61
74
0.0
5.0
70
66
4.72
4.66
135
20
50
Units
mV
max
µA
max
nA
max
dB
min
dB
min
V
max
V
min
dB
min
V
min
mV
max
mA
min
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Page 5
5V Electrical Characteristics (Continued)
Unless otherwise specified, all limited guaranteed for TJ= 25˚C, V+= 5V, V−= 0V, VCM= 1V, VO=V+/2, and
>
R
1MΩ to V−. Boldface limits apply at the temperature extremes.
L
Symbol Parameter Condition
I
S
SR Slew Rate (Note 8) A
f
u
Supply Current No load, VCM= 1V 0.97 1.25
= +1, VI=5V
V
PP
Unity Gain Frequency VI= 10mV,
=2KΩto V+/2
R
L
Typ
(Note 5)
12 10
10.5 – MHz
GBWP Gain-Bandwidth Product f = 50KHz 21 16
Phi
e
m
n
Phase Margin VI= 10mV 53 – Deg
Input-Referred Voltage Noise f = 2KHz, RS=50Ω 15 – nV/
Limit
(Note 6)
1.75
15
LM8261
Units
mA
max
V/µs
7
min
MHz
min
i
n
f
max
t
S
THD+N Total Harmonic Distortion + Noise R
Input-Referred Current Noise f = 2KHz 1 – pA/
Full Power Bandwidth ZL= (20pF || 10kΩ)toV+/2 900 – KHz
Settling Time (+/−5%) 100mVPPStep, 500pF load 400 – ns
=1KΩto V+/2
L
f = 10KHz to A
= +2, 4V
V
PP
0.05 – %
swing
+/−15V Electrical Characteristics
Unless otherwise specified, all limited guaranteed for TJ= 25˚C, V+= 15V, V−= −15V, VCM= 0V, VO= 0V, and
>
R
1MΩ to 0V. Boldface limits apply at the temperature extremes.
L
Symbol Parameter Condition
V
OS
TC V
Input Offset Voltage VCM= −14.5V & VCM= 14.5V +/−0.7 +/−7
Input Offset Average Drift VCM= −14.5V & VCM= 14.5V
OS
(Note 12)
I
B
Input Bias Current VCM= −14.5V
(Note 7)
= 14.5V
V
CM
(Note 7)
I
OS
CMRR Common Mode Rejection Ratio V
+PSRR Positive Power Supply Rejection
Input Offset Current VCM= −14.5V & VCM= 14.5V 30 275
stepped from −15V to 13V 100 84
CM
stepped from 14V to 15V 100 –
V
CM
V
stepped from −15V to 15V 88 74
CM
+
V
= 12V to 15V 100 70
Ratio
−PSRR Negative Power Supply Rejection
−
V
= −12V to −15V 100 70
Ratio
CMVR Input Common-Mode Voltage Range CMRR
>
50dB −15.3 −15.1
Typ
(Note 5)
(Note 6)
+/−2 – µV/˚C
−1.05 −2.00
−2.80
+0.49 +1.00
+1.50
−15.0
15.3 15.1
Limit
+/− 9
550
80
72
66
66
15.0
Units
mV
max
µA
max
nA
max
dB
min
dB
min
dB
min
V
max
V
min
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Page 6
+/−15V Electrical Characteristics (Continued)
Unless otherwise specified, all limited guaranteed for TJ= 25˚C, V+= 15V, V−= −15V, VCM= 0V, VO= 0V, and
LM8261
>
R
1MΩ to 0V. Boldface limits apply at the temperature extremes.
L
Symbol Parameter Condition
A
VOL
V
O
Large Signal Voltage Gain VO= 0V to +/−13V,
= 10KΩ
R
L
= 0V to +/−13V,
V
O
=2KΩ
R
L
Output Swing
RL= 10KΩ 14.83 14.65
Typ
(Note 5)
85 78
79 72
High
=2KΩ 14.73 14.60
R
L
Output Swing
R
= 10KΩ −14.91 −14.75
L
Low
=2KΩ −14.83 −14.65
R
L
I
SC
I
S
Output Short Circuit Current Sourcing to ground
Supply Current No load, VCM= 0V 1.30 1.50
SR Slew Rate
= 200mV (Note 10)
V
ID
Sinking to ground
= 200mV (Note 10)
V
ID
A
= +1, VI= 24V
V
PP
60 40
100 70
15 10
(Note 8)
f
u
Unity Gain Frequency VI= 10mV, RL=2KΩ 14 – MHz
GBWP Gain-Bandwidth Product f = 50KHz 24 18
Phi
e
n
m
Phase Margin VI= 10mV 58 – Deg
Input-Referred Voltage Noise f = 2KHz, RS=50Ω 15 – nV/
Limit
(Note 6)
74
66
14.61
14.55
−14.65
−14.60
25
60
1.90
8
16
Units
dB
min
V
min
V
max
mA
min
mA
max
V/µs
min
MHz
min
i
n
f
max
t
S
THD+N Total Harmonic Distortion +Noise R
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Rating indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5kΩ in series with 100pF.
Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150˚C.
Note 4: The maximum power dissipation is a function of T
P
D
Note 5: Typical Values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
Note 7: Positive current corresponds to current flowing into the device.
Note 8: Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
Note 9: Machine Model, 0Ω is series with 200pF.
Note 10: Short circuit test is a momentary test. See Note 11.
Note 11: Output short circuit duration is infinite for V
Note 12: Offset voltage average drift determined by dividing the change in V
Input-Referred Current Noise f = 2KHz 1 – pA/
Full Power Bandwidth ZL= 20pF || 10KΩ 160 – KHz
Settling Time (+/−1%, AV= +1) Positive Step, 5V
Negative Step, 5V
=1KΩ, f = 10KHz,
L
= +2, 28VPPswing
A
V
(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is
=(TJ(max) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
J
≤ 6V at room temperature and below. For V
S
PP
PP
at temperature extremes into the total temperature change.
OS
>
6V, allowable short circuit duration is 1.5ms.
S
320 –
600 –
0.01 – %
ns
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Page 7
LM8261
Typical Performance Characteristics T
V
vs. VCMfor 3 Representative Units
OS
DS101084-30
VOSvs. VCMfor 3 Representative Units
= 25˚C, Unless Otherwise Noted
A
VOSvs. VCMfor 3 Representative Units
VOSvs. VSfor 3 Representative Units
DS101084-29
VOSvs. VSfor 3 Representative Units
DS101084-31
DS101084-35
DS101084-34
VOSvs. VSfor 3 Representative Units
DS101084-33
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Typical Performance Characteristics T
LM8261
I
vs. V
B
CM
= 25˚C, Unless Otherwise Noted (Continued)
A
IBvs. V
S
ISvs. V
ISvs. V
CM
CM
DS101084-24
DS101084-27
ISvs. V
CM
ISvs. VS(PNP side)
DS101084-36
DS101084-28
DS101084-68
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DS101084-25
Page 9
LM8261
Typical Performance Characteristics T
I
vs. VS(NPN side)
S
DS101084-26
Unity Gain Frequency vs. V
S
= 25˚C, Unless Otherwise Noted (Continued)
A
Gain/Phase vs. Frequency
Phase Margin vs. V
S
DS101084-18
Unity Gain Freq. and Phase Margin vs. V
S
DS101084-7
DS101084-4
DS101084-8
Unity Gain Frequency vs. Load
DS101084-5
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Page 10
Typical Performance Characteristics T
LM8261
Phase Margin vs. Load
= 25˚C, Unless Otherwise Noted (Continued)
A
Unity Gain Freq. and Phase Margin vs. C
L
CMRR vs. Frequency
−PSRR vs. Frequency
DS101084-6
DS101084-14
DS101084-9
+PSRR vs. Frequency
DS101084-16
Output Voltage vs. Output Sourcing Current
DS101084-17
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DS101084-46
Page 11
LM8261
Typical Performance Characteristics T
Output Voltage vs. Output Sourcing Current
DS101084-44
Max Output Swing vs. Load
= 25˚C, Unless Otherwise Noted (Continued)
A
Output Voltage vs. Output Sinking Current
Max Output Swing vs. Frequency
DS101084-45
% Overshoot vs. Cap Load
DS101084-10
DS101084-48
±
5% Settling Time vs. Cap Load
DS101084-11
DS101084-47
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Page 12
Typical Performance Characteristics T
LM8261
+SR vs. Cap Load
= 25˚C, Unless Otherwise Noted (Continued)
A
−SR vs. Cap Load
+SR vs. Cap Load
Settling Time vs. Error Voltage
DS101084-51
DS101084-49
DS101084-52
−SR vs. Cap Load
DS101084-50
Settling Time vs. Error Voltage
DS101084-43
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DS101084-42
Page 13
LM8261
Typical Performance Characteristics T
Input Noise Voltage/Current vs. Frequency
DS101084-15
Input Noise Current for Various V
CM
= 25˚C, Unless Otherwise Noted (Continued)
A
Input Noise Voltage for Various V
Input Noise Voltage vs. V
CM
CM
DS101084-13
Input Noise Current vs. V
CM
DS101084-12
DS101084-54
DS101084-55
THD+N vs. Frequency
DS101084-23
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Page 14
Typical Performance Characteristics T
LM8261
THD+N vs. Frequency
= 25˚C, Unless Otherwise Noted (Continued)
A
THD+N vs. Frequency
THD+N vs. Amplitude
Small Signal Step Response
DS101084-22
DS101084-19
DS101084-21
THD+N vs. Amplitude
DS101084-20
Large Signal Step Response
DS101084-38
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DS101084-40
Page 15
Application Notes:
Block Diagram and Operational Description:
A) Input Stage:
As can be seenfromthesimplifiedschematic in
input stage consists of two distinct differential pairs (Q1-Q2
and Q3-Q4) in order to accommodate the full Rail-to-Rail input common mode voltage range. The voltage drop across
R5, R6, R7, and R8 is kept to less than 200mV in order to allow the input to exceed the supply rails. Q13 acts as a switch
to steer current away from Q3-Q4 and into Q1-Q2, as the input increases beyond 1.4V of V
+
. This in turn shifts the signal
path from the bottom stage differential pair to the top one
and causes a subsequent increase in the supply current.
In transitioning from one stage to another, certain input stage
parameters (V
os,Ib,Ios,en
, and in) are determined based on
which differential pair is ″on″ at the time. Input Bias current,
I
, will change in value and polarity as the input crosses the
b
transition region. In addition, parameters such as PSRR and
CMRR which involve the input offset voltage will also be effected by changes in V
across the differential pair transi-
CM
tion region.
FIGURE 1. Simplified schematic Diagram
The input stage is protected with the combination of R9-R10
and D1, D2, D3, and D4 against differential input
over-voltages. This fault condition could otherwise harm the
differential pairs or cause offset voltage shift in case of prolonged over voltage. As shown in
Figure 2
reaches approximately +/−1.4V at 25˚C, the diodes turn on
and current flow is limited by the internal series resistors (R9
and R10). The Absolute Maximum Rating of +/−10V differential on V
still needs to be observed. With temperature varia-
in
tion, the point were the diodes turn on will change at the rate
of 5mV/˚C.
Figure 1
, the
DS101084-67
, if this voltage
DS101084-66
FIGURE 2. Input Stage Current vs Differential Input
Voltage
B) Output Stage:
The output stage
Figure 1
is comprised of complementary
NPN and PNP common-emitter stages to permit voltage
swing to within a V
of either supply rail. Q9 supplies the
ce(sat)
sourcing and Q10 supplies the sinking current load. Output
current limiting is achieved by limiting the V
of Q9 and Q10;
ce
using this approach to current limiting, alleviates the draw
back to the conventional scheme which requires one V
re-
be
duction in output swing.
The frequency compensation circuit includes Miller capaci-
tors from collector to base of each output transistor (see
ure 1
,C
comp9
and C
). At light capacitive loads, the
comp10
Fig-
high frequency gain of the output transistors is high, and the
Miller effect increases the effective value of the capacitors
thereby stabilizing the Op Amp. Large capacitive loads
greatly decrease the high frequency gain of the output transistors thus lowering the effective internal Miller capacitance
- the internal pole frequency increases at the same time a
low frequency pole is created at the Op Amp output due to
the large load capacitor. In this fashion, the internal dominant
pole compensation, which works by reducing the loop gain to
less than 0dB when the phase shift around the feedback
loop is more than 180˚C, varies with the amount of capacitive load and becomes less dominant when the load capacitor has increased enough. Hence the Op Amp is very stable
even at high values of load capacitance resulting in the uncharacteristic feature of stability under all capacitive loads.
Driving Capacitive Loads:
The LM8261 is specifically designed to drive unlimited capacitive loads without oscillations (See Settling Time and
Percent Overshoot vs. Cap Load plots in the typical performance characteristics section). In addition, the output current handling capability of the device allows for good slewing
characteristics even with large capacitive loads (see Slew
Rate vs. Cap Load plots). The combination of these features
is ideal for applications such as TFT flat panel buffers, A/D
converter input amplifiers, etc.
However, as in most Op Amps, addition of a series isolation
resistor between the Op Amp and the capacitive load improves the settling and overshoot performance.
Output current drive is an important parameter when driving
capacitive loads. This parameter will determine how fast the
output voltage can change. Referring to the Slew Rate vs.
Cap Load Plots (typical performance characteristics section), two distinct regions can be identified. Below about
10,000pF, the output Slew Rate is solely determined by the
LM8261
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Page 16
Application Notes: (Continued)
Op Amp’s compensation capacitor value and available cur-
LM8261
rent into that capacitor. Beyond 10nF, the Slew Rate is determined by the Op Amp’s available output current. Note that
because of the lower output sourcing current compared to
the sinking one, the Slew Rate limit under heavy capacitive
loading is determined by the positive transitions.An estimate
of positive and negative slew rates for loads larger than
100nF can be made by dividing the short circuit current value
by the capacitor.
For the LM8261, the available output current increases with
the input overdrive. Referring to
put Short Circuit Current vs. Input Overdrive, it can be seen
that both sourcing and sinking short circuit current increase
as input overdrive increases. In a closed loop amplifier configuration, during transient conditions while the fed back output has not quite caught up with the input, there will be an
overdrive imposed on the input allowing more output current
than would normally be available under steady state condition. Because of this feature, the Op Amp’s output stage quiescent current can be kept to a minimum, thereby reducing
power consumption, while enabling the device to deliver
large output current when the need arises (such as during
transients).
FIGURE 3. Output Short Circuit Sourcing Current vs
Input Overdrive
Figure 3
and
DS101084-57
Figure 4
, Out-
Figure 5
resulting input overdrive with the device set forA
the input tied to a 1V
shows the output voltage, output current, and the
= +1 and
step function driving a 47nF capaci-
pp
V
tor. As can be seen, during the output transition, the input
overdrive reaches 1V peak and is more than enough to
cause the output current to increase to its maximum value
(see
Figure 3
and
Figure 4
plots). Note that because of the
larger output sinking current compared to the sourcing one,
the output negative transition is faster than the positive one.
DS101084-39
FIGURE 5. Buffer Amplifier scope photo
Estimating the output voltage swing:
It is important to keep in mind that the steady state output
current will be less than the current available when there is
an input overdrive present. For steady state conditions, the
Output Voltage vs. Output Current plot (Typical Performance
Characteristics section) can be used to predict the output
swing.
Figure 6
and
Figure 7
show this performance along
with several load lines corresponding to loads tied between
the output and ground. In each cases, the intersection of the
device plot at the appropriate temperature with the load line
would be the typical output swing possible for that load. For
example, a 1KΩ load can accomadate an output swing to
within 250mV of V
responding to a typical 29.3V
−
and to 330mV of V+(Vs = +/−15V) cor-
unclipped swing.
pp
DS101084-56
FIGURE 4. Output Short Circuit Sinking Current vs
Input Overdrive
www.national.com 16
DS101084-60
FIGURE 6. Output Sourcing Characteristics with Load
Lines
Page 17
Application Notes: (Continued)
DS101084-59
FIGURE 7. Output Sinking Characteristics with Load
Lines
TFT applications:
Figure 8
LM8261 is used as a buffer amplifier for the V
ployed in a TFT LCD flat panel:
Figure 9
when used as a V
this application, the Op Amp loop will try and maintain its output voltage based on the voltage on its non-inverting input
(V
REF
load.As long as this load current is within the range tolerable
by the LM8261 (45mA sourcing and 65mAsinking for +/−5V
supplies), the output will settle to its final value within less
than 2µs.
below, shows a typical application where the
signal em-
com
DS101084-61
FIGURE 8. V
driver application schematic
com
shows the time domain response of the amplifier
buffer/driver with V
com
at ground. In
REF
) despite the current injected into the TFT simulated
Output Short Circuit Current and Dissipation Issues:
The LM8261 output stage is designed for maximum output
current capability. Even though momentary output shorts to
ground and either supply can be tolerated at all operating
voltages, longer lasting short conditions can cause the junction temperature to rise beyond the absolute maximum rating of the device, especially at higher supply voltage conditions. Below supply voltage of 6V, output short circuit
condition can be tolerated indefinitely.
With the Op Amp tied to a load, the device power dissipation
consists of the quiescent power due to the supply current
flow into the device, in addition to power dissipation due to
the load current. The load portion of the power itself could include an average value (due to a DC load current) and an AC
component. DC load current would flow if there is an output
voltage offset, or the output AC average current is non-zero,
or if the Op Amp operates in a single supply application
where the output is maintained somewhere in the range of
linear operation. Therefore:
P
total=PQ+PDC+PAC
PQ=IS·V
S
Op Amp Quiescent
Power Dissipation
P
DC=IO
P
AC
·(Vr-Vo) DC Load Power
= See Table 1 below AC Load Power
where:
I
: Supply Current
s
V
: Total Supply Voltage (V+-V−)
s
I
: Average load current
o
V
: Average Output Voltage
o
V
:V+for sourcing and V−for sinking current
r
Table 1
below shows the maximum AC component of the
load power dissipated by the Op Amp for standard Sinusoidal, Triangular, and Square Waveforms:
TABLE 1. Normalized AC Power Dissipated in the
Output Stage for Standard Waveforms
PAC(W.Ω/V2)
Sinusoidal Triangular Square
50.7 x 10
−3
46.9 x 10
The table entries are normalized to V
−3
62.5 x 10
2
/RL. To figure out the
s
−3
AC load current component of power dissipation, simply multiply the table entry corresponding to the output waveform by
the factor V
2
/RL. For example, with±15V supplies, a 600Ω
s
load, and triangular waveform power dissipation in the output stage is calculated as:
P
= (46.9 x 10−3) · [302/600]= 70.4mW
AC
LM8261
FIGURE 9. V
DS101084-65
driver performance scope photo
com
www.national.com17
Page 18
Application Notes: (Continued)
Other Application Hints:
LM8261
The use of supply decoupling is mandatory in most applications. As with most relatively high speed/high output current
OpAmps, best results are achieved when each supply line is
decoupled with two capacitors; a small value ceramic capacitor (∼0.01µF) placed very close to the supply lead in addition to a large value Tantalum orAluminum (
large capacitor can be shared by more than one device if
necessary. The small ceramic capacitor maintains low supply impedance at high frequencies while the large capacitor
will act as the charge ″bucket″ for fast load current spikes at
the Op Amp output. The combination of these capacitors will
provide supply decoupling and will help keep the Op Amp oscillation free under any load.
>
4.7µF). The
LM8261 Advantages:
Compared to other Rail-to-Rail Input/Output devices, the
LM8261 offers several advantages such as:
Improved cross over distortion.
•
Nearly constant supply current throughout the output
•
voltage swing range and close to either rail.
Consistent stability performance for all input/output volt-
•
age and current conditions.
Nearly constant Unity gain frequency (fu) and Phase Mar-
•
gin (Phi
No output phase reversal under input overload condition.
•
) for all operating supplies and load conditions.
m
www.national.com 18
Page 19
Physical Dimensions inches (millimeters) unless otherwise noted
LM8261 Single RRIO, High Output Current & Unlimited Cap Load Op Amp in SOT23-5
5-Pin SOT23-5
NS Package Number MA05B
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