Datasheet LM555, LM555C, NE555 Datasheet (HARRIS Semiconductor)

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SEMICONDUCTOR

May 1997

CA555, CA555C,

LM555, LM555C, NE555

Timers for Timing Dela ys and Oscillator Application

in Commercial, Industrial and Military Equipment

Features

• Accurate Timing From Microseconds Through Hours

• Astable and Monostable Operation

• Adjustable Duty Cycle

• Output Capable of Sourcing or Sinking up to 200mA

• Output Capable of Driving TTL Devices

• Normally ON and OFF Outputs

• High Temperature Stability. . . . . . . . . . . . . . 0.005%/

o

• Directly Interchangeable with SE555, NE555, MC1555,
and MC1455

Applications

• Precision Timing • Pulse Generation

• Sequential Timing • Pulse Detector

• Time Delay Generation • Pulse Width and Position

Modulation

Ordering Information

P ART NUMBER

(BRAND)

CA0555E -55 to 125 8 Ld PDIP E8.3
CA0555M (555) -55 to 125 8 Ld SOIC M8.15
CA0555M96 (555) -55 to 125 8 Ld SOIC
CA0555T -55 to 125 8 Pin Metal Can T8.C
CA0555CE 0 to 70 8 Ld PDIP E8.3
CA0555CM (555C) 0 to 70 8 Ld SOIC M8.15
CA0555CM96 (555C) 0 to 70 8 Ld SOIC
CA0555CT 0 to 70 8 Pin Metal Can T8.C
LM555N -55 to 125 8 Ld PDIP E8.3
LM555CN 0 to 70 8 Ld PDIP E8.3
NE555N 0 to 70 8 Ld PDIP E8.3

† Denotes Tape and Reel

NOTE:

TEMP.

RANGE (oC) PACKAGE

† M8.15

† M8.15

PKG.

NO.

Description

The CA555 and CA555C are highly stable timers for use in
precision timing and oscillator applications. As timers, these
monolithic integrated circuits are capable of producing accu­rate time delays for periods ranging from microseconds
through hours. These devices are also useful for astable
oscillator operation and can maintain an accurately con-

C

trolled free running frequency and duty cycle with only two
external resistors and one capacitor.

The circuits of the CA555 and CA555C may be triggered by
the falling edge of the waveform signal, and the output of
these circuits can source or sink up to a 200mA current or
drive TTL circuits.

These types are direct replacements for industry types in
packages with similar terminal arrangements e.g. SE555
and NE555, MC1555 and MC1455, respectively. The CA555
type circuits are intended for applications requiring premium
electrical performance. The CA555C type circuits are
intended for applications requiring less stringent electrical
characteristics.

Pinouts

CA555, CA555C (PDIP, SOIC)

LM555, LM555C, NE555 (PDIP)

TOP VIEW

1

GND

TRIGGER

OUTPUT

TRIGGER

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

2
3
4

RESET

CA555, CA555C (METAL CAN)

TOP VIEW

V+

GND

2

OUTPUT

8

1

3

4

RESET

8

V+

7

DISCHARGE

6

THRESHOLD

5

CONTROL
VOLTAGE

TAB

7

DISCHARGE

6

THRESHOLD

5

CONTROL
VOLTAGE

Functional Block Diagram

V+

CONTROL

8

VOLTAGE

6

THRESHOLD

THRESHOLD

COMPAR

4

RESET

1

GND

8-3

TRIGGER

5

2

TRIGGER
COMPAR

FLIP-FLOP

3

OUTPUT

OUTPUT

7

DISCHARGE

File Number 834.4

CA555, CA555C, LM555, LM555C, NE555

Absolute Maximum Ratings Thermal Information

DC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V

Operating Conditions

Temperature Range

CA555, LM555 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CA555C, LM555C, NE555 . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

Metal Can Package. . . . . . . . . . . . . . . 170 85

PDIP Package. . . . . . . . . . . . . . . . . . . 100 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . 160 N/A

Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Specifications T

= 25oC, V+ = 5V to 15V Unless Otherwise Specified

A

CA555, LM555 CA555C, LM555C, NE555

PARAMETER SYMBOL TEST CONDITIONS

UNITSMIN TYP MAX MIN TYP MAX

DC Supply Voltage V+ 4.5 - 18 4.5 - 16 V
DC Supply Current (Low State),

(Note 2)

Threshold Voltage V

I+ V+ = 5V, R

V+ = 15V, RL = ∞ - 10 12 - 10 15 mA

TH

= ∞ -35- 36mA

L

-(2/3)V+ - - (2/3)V+ - V

Trigger Voltage V+ = 5V 1.45 1.67 1.9 - 1.67 - V

V+ = 15V 4.8 5 5.2 - 5 - V
Trigger Current - 0.5 - - 0.5 - µA
Threshold Current (Note 3) I

TH

- 0.1 0.25 - 0.1 0.25 µA
Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V
Reset Current - 0.1 - - 0.1 - mA
Control Voltage Level V+ = 5V 2.9 3.33 3.8 2.6 3.33 4 V

V+ = 15V 9.6 10 10.4 9 10 11 V

Output Voltage V

Low State I

Output Voltage V

High State

Timing Error (Monostable) R1, R2 = 1kΩ to 100kΩ,

OL

OH

V+ = 5V, I

= 8mA - 0.1 0.25 - - - V

SINK

V+ = 15V, I
I

= 50mA - 0.4 0.5 - 0.4 0.75 V

SINK

I

= 100mA - 2.0 2.2 - 2.0 2.5 V

SINK

I

= 200mA - 2.5 - - 2.5 - V

SINK

V+ = 5V, I

V+ = 15V, I

I

SOURCE

= 5mA - - - - 0.25 0.35 V

SINK

= 10mA - 0.1 0.15 - 0.1 0.25 V

SINK

SOURCE

= 100mA 3.0 3.3 - 2.75 3.3 - V

SOURCE

= 100mA

13.0 13.3 - 12.75 13.3 - V

= 200mA - 12.5 - - 12.5 - V

- 0.5 2 - 1 - %

C = 0.1µF

Frequency Drift with Temperature - 30 100 - 50 - ppm/oC

Tested at V+ = 5V, V+ = 15V

Drift with Supply Voltage - 0.05 0.2 - 0.1 - %/V

8-4

CA555, CA555C, LM555, LM555C, NE555

Electrical Specifications T

= 25oC, V+ = 5V to 15V Unless Otherwise Specified (Continued)

A

CA555, LM555 CA555C, LM555C, NE555

PARAMETER SYMBOL TEST CONDITIONS

Output Rise Time t
Output Fall Time t

R

F

- 100 - - 100 - ns

- 100 - - 100 - ns

UNITSMIN TYP MAX MIN TYP MAX

NOTES:

2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.

3. The threshold current will determine the sum of the values of R1 and R2 to be used in Figure 4 (astable operation); the maximum total
R1 + R2 = 20MΩ.

Schematic Diagram

V+

8

THRESHOLD

6

CONTROL

VOLTAGE

5
2

TRIGGER

4

RESET

7

DISCHARGE

1

V-

THRESHOLD

COMPARATOR

4.7K 830 4.7K

Q3Q

Q

Q

2

6

DISCHARGE

D

4

5

10K

Q

Q

D

1

1

RESET

Q

2

Q

7

8

TRIGGER

COMPARATOR

1K

Q

Q

Q

9

100

10

11

100K

OUTPUTFLIP-FLOP

5K 6.8K

Q

16

Q

19

Q

20

OUTPUT

7K

D

4.7K

5K

Q

12

Q

13

Q

5K

15

Q

14

3

Q

17

3.9K

D

4

Q

18

220

Q

21

4.7K

3

NOTE: Resistance values are in ohms.

Typical Applications

Reset Timer (Monostable Operation)

Figure 1 shows the CA555 connected as a reset timer. In this
mode of operation capacitor C
a transistor on the integrated circuit. Upon closing the “start”
switch, or applying a negative trigger pulse to terminal 2, the
integral timer flip-flop is “set” and releases the short circuit
across C

which drives the output voltage “high” (relay ener-

T

is initially held discharged by

T

gized). The action allows the voltage across the capacitor to
increase exponentially with the constant t = R

. When the

1CT

voltage across the capacitor equals 2/3 V+, the comparator
resets the flip-flop which in turn discharges the capacitor rap­idly and drives the output to its low state.

8-5

CA555, CA555C, LM555, LM555C, NE555

RESET

R

1

C

T

7

6

4.7K

S

1

START

4

CA555

1

2

8

5

EO

0.01µF

680

3

10K

680

1N4001

RELAY
COIL

5V

V+

NOTE: All resistance values are in ohms.

FIGURE 1. RESET TIMER (MONOSTABLE OPERATION)

Since the charge rate and threshold level of the comparator
are both directly proportional to V+, the timing interval is rel­atively independent of supply voltage variations. Typically,
the timing varies only 0.05% for a 1V change in V+.

Applying a negative pulse simultaneously to the reset termi­nal (4) and the trigger terminal (2) during the timing cycle
discharges C

and causes the timing cycle to restart.

T

Momentarily closing only the reset switch during the timing
interval discharges C

, but the timing cycle does not restart.

T

Figure 2 shows the typical wavefor ms generated during this
mode of operation, and Figure 3 gives the family of time
delay curves with variations in R

SWITCH S

3V

VOLTAGE (TERMINAL 2)

VOLTAGE (TERMINALS 6, 7)

INPUT

SWITCH S

0

3.3V
CAPACITOR

0

5V
OUTPUT

VOLTAGE

(TERMINAL 3)

0

FIGURE 2. TYPICAL WAVEFORMS FOR RESET TIMER

“OPEN”

1

“CLOSED”

1

and CT.

1

t

D

100

TA = 25oC
V+ = 5V

10

10

R1 = 1kΩ

-4

10kΩ

-3

10

TIME DELAY(s)

100kΩ

10

1MΩ

10MΩ

-2

-1

10110

CAPACITANCE (µF)

0.01

0.001

0.1

1

-5

10

FIGURE 3. TIME DELAY vs RESISTANCE AND CAPACITANCE

Repeat Cycle Timer (Astable Operation)

Figure 4 shows the CA555 connected as a repeat cycle
timer. In this mode of operation, the total period is a function
of both R

FIGURE 4. REPEAT CYCLE TIMER (ASTABLE OPERATION)

where t1 = 0.693 (R1 + R2) C

and R

1

2.

R

1

R

2

C

T

4

CA555

1

2

8

5

7

6

T = 0.693 (R1 + 2R2) CT = t1 + t

and t2 = 0.693 (R2) C

T

EO

3

0.01µF

T

RELAY
COIL

2

5V

V+

the duty cycle is:

t

R

------------------------

=

R

1

+

1R2

2R2+

1

--------------- -

t1t2+

Typical waveforms generated during this mode of operation
are shown in Figure 5. Figure 6 gives the family of curves of
free running frequency with variations in the value of
(R

+2R2) and CT.

1

8-6

CA555, CA555C, LM555, LM555C, NE555

t

2

t

1

5V

0

3.3V

1.7V

0

Top Trace: Output voltage (2V/Div. and 0.5ms/Div.)

Bottom Trace: Capacitor voltage (1V/Div. and 0.5ms/Div.)

FIGURE 5. TYPICAL WAVEFORMS FOR REPEAT CYCLE TIMER

Typical Performance Curves

100

0.1

CAPACITANCE (µF)

0.01

0.001

10

1

10MΩ

-1

10

110

100kΩ

1MΩ

10

FREQUENCY (Hz)

10kΩ

2

TA = 25oC, V+ = 5V

R1 + 2R2 = 1kΩ

3

10

4

10

10

FIGURE 6. FREE RUNNING FREQUENCY OF REPEAT CYCLE

TIMER WITH VARIATION IN CAPACITANCE AND
RESISTANCE

5

150

100

50

MINIMUM PULSE WIDTH (ns)

MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)

TA = -55oC

0oC

25oC
70oC

125oC

0.40.30.20.10

NOTE: Where x is the decimal multiplier of the supply voltage.

FIGURE 7. MINIMUM PULSE WIDTH vs MINIMUM TRIGGER

VOLTAGE

2.0
TA = -55oC

1.6

1.2

0.8

25oC

125oC

10

9
8
7
6
5
4
3

SUPPLY CURRENT (mA)

2
1

SUPPLY VOLTAGE (V)

TA = 125oC

50oC

FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE

10.0
V+ = 5V

TA = -55oC

1.0

0.1

25oC

125oC

25oC

1512.5107.552.50

0.4

5V ≤ V+ ≤ 15V

SUPPLY VOLTAGE - OUTPUT VOLTAGE (V)

0

SOURCE CURRENT (mA)

FIGURE 9. OUTPUT VOLTAGE DROP (HIGH STATE) vs

SOURCE CURRENT

OUTPUT VOLTAGE - LOW ST ATE (V)

0.01

100101

SINK CURRENT (mA)

FIGURE 10. OUTPUT VOLTAGE LOW STATE vs SINK

CURRENT

8-7

100101

CA555, CA555C, LM555, LM555C, NE555

Typical Performance Curves

10.0
V+ = 10V

1.0

125oC

o

25

C

0.1

OUTPUT VOLTAGE - LOW ST ATE (V)

0.01

SINK CURRENT (mA)

(Continued)

TA = -55oC

25oC

FIGURE 11. OUTPUT VOLTAGE LOW STATE vs SINK

CURRENT

1.100

TA = 25oC

1.000

125oC

10.0
V+ = 15V

1.0

125oC

o

C

25

0.1

OUTPUT VOLTAGE - LOW ST ATE (V)

100101

0.01

SINK CURRENT (mA)

FIGURE 12. OUTPUT VOLTAGE LOW STATE vs SINK

CURRENT

1.005

-55oC

TA = -55oC

100101

0.990

NORMALIZED DELAY TIME

0.980

SUPPLY VOLTAGE (V)

1512.5107.552.50

17.5

0.995

0.985

NORMALIZED DELAY TIME

-50
TEMPERATURE (

FIGURE 13. DELAY TIME vs SUPPLY VOLTAGE FIGURE 14. DELAY TIME vs TEMPERATURE

300

250

200

150

100

50

PROPAGATION DELAY TIME (ns)

TA = -55oC

0oC

o

25

C

o

70

C

o

C

125

0.40.30.20.10

MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)

1007550250-25-75

125

o

C)

NOTE: Where x is the decimal multiplier of the supply voltage.

FIGURE 15. PROPAGATION DELAY TIME vs TRIGGER VOLTAGE

8-8