Datasheet NE555, LM555, SA555 Datasheet (Fairchild Semiconductor)

LM555/NE555/SA555

Single Timer

Features

FeaturesFeatures

• High Current Drive Capability (200mA)

• Adjustable Duty Cycle

• Tem perature Stability of 0.005%/°C

• Timing From µSec to Hours

• Turn off Time Less Than 2µSec

Applications

ApplicationsApplications

• Precision Timing

• Pulse Generation

• Time Delay Generation

• Sequential Timing

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Description

DescriptionDescription

The LM555/NE555/SA555 is a highly stable controller capable of producing accurate timing pulses. With a monostable operation, the time delay is controlled by one external resistor and one capacitor. With an astable operation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor.

8-DIP

8-DIP8-DIP

1

8-SOP

8-SOP8-SOP

Internal Block Diagram

Internal Block DiagramInternal Block Diagram

GND

GNDGND

Trigger

TriggerTrigger

Output

OutputOutput

Reset

ResetReset

1

RRRRR

1111

Comp.

Comp.Comp.

2222

OutPut

OutPutOutPut

3333

Stage

StageStage

4444

Vref

VrefVref

RR

Discharging Tr.

Discharging Tr.Discharging Tr.

F/F

F/FF/F

Comp.

Comp.Comp.

R

RR

8888

Vcc

VccVcc

7777

Discharge

DischargeDischarge

6666

Threshold

ThresholdThreshold

Control

ControlControl

5555

Voltage

VoltageVoltage

Rev. 1.0.3

LM555/NE555/SA555

Absolute Maximum Ratings (T

Absolute Maximum Ratings (TAbsolute Maximum Ratings (T

Parameter

Parameter Symbol

ParameterParameter Supply Voltage V Lead Temperature (Soldering 10sec) T Power Dissipation P Operating Temperature Range

LM555/NE555 SA555

Storage Temperature Range T

= 25

= 25°°°°C)

= 25 = 25

AAAA

C)

C)C)

Symbol Value

SymbolSymbol

LEAD

T

OPR

STG

CC

D

Value Unit

ValueValue

16 V 300 °C 600 mW

0 ~ +70

-40 ~ +85

-65 ~ +150 °C

Unit

UnitUnit

°C

2222

Electrical Characteristics

Electrical CharacteristicsElectrical Characteristics

(TA = 25°C, V

Parameter

Parameter Symbol

ParameterParameter

= 5 ~ 15V, unless otherwise specified)

CC

Symbol Conditions

SymbolSymbol

Supply Voltage V Supply Current (Low Stable) (Note1) I

CC

Timing Error (Monostable) Initial Accuracy (Note2) Drift with Temperature (Note4) Drift with Supply Voltage (Note4)

ACCUR

∆t/∆T

∆t/∆V

CC

LM555/NE555/SA555

Conditions Min.

ConditionsConditions

Min. Typ.

Min.Min.

Typ. Max.

Typ.Typ.

Max. Unit

Max.Max.

-4.5-16V

VCC = 5V, RL = ∞ -36mA

= 15V, RL = ∞ -7.515mA

V

CC

RA = 1kΩ to100kΩ C = 0.1µF

CC

-1.0 50

0.1

3.0

0.5

Unit

UnitUnit

%

ppm/°C

%/V

Timing Error (Astable) Intial Accuracy (Note2) Drift with Temperature (Note4) Drift with Supply Voltage (Note4)

ACCUR

∆t/∆T

∆t/∆V

Control Voltage V

Threshold Voltage V Threshold Current (Note3) I Trigger Voltage V Trigger Current I

Reset Voltage V Reset Current I

Low Output Voltage V

High Output Voltage V

Rise Time of Output (Note4) t Fall Time of Output (Note4) t Discharge Leakage Current I

C

TH

TR

RST

OL

OH

R F

LKG

RA = 1kΩ to 100kΩ C = 0.1µF

CC

-

2.25 150

0.3 VCC = 15V 9.0 10.0 11.0 V V

= 5V 2.6 3.33 4.0 V

CC

VCC = 15V - 10.0 - V

= 5V - 3.33 - V

V

CC

-----0.10.25 µA

V

= 5V 1.1 1.67 2.2 V

CC

= 15V 4.5 5 5.6 V

V

CC

V

= 0V 0.01 2.0 µA

TR

----0.40.71.0V

----0.10.4mA

VCC = 15V I

SINK

I

SINK

V

CC

I

SINK

= 10mA = 50mA

= 5V

= 5mA

-0.06

0.3

-0.050.35 V

VCC = 15V I

SOURCE

I

SOURCE

V

CC

I

SOURCE

= 200mA = 100mA 12.75

= 5V

= 100mA

12.5

13.3

2.75 3.3 - V

---- - 100 - ns

---- - 20 100 nA

-% ppm/°C

%/V

0.25

0.75

V V

-V

V

Notes:

Notes:Notes:

1. When the output is high, the supply current is typically 1mA less than at V

2. Tested at V

3. This will determine the maximum value of R total R = 6.7MΩ.

4. These parameters, although guaranteed, are not 100% tested in production.

= 5.0V and V

CC

= 15V.

+ RB for 15V operation, the max. total R = 20MΩ, and for 5V operation, the max.

A

CC

= 5V.

3333

LM555/NE555/SA555

Application Information

Application InformationApplication Information

Table 1 below is the basic operating table of 555 timer:

Table 1. Basic Operating Table

Table 1. Basic Operating TableTable 1. Basic Operating Table

Threshold Voltage

Threshold Voltage Threshold Voltage

(V

)(PIN 6)

(V(V

)(PIN 6))(PIN 6)

th

thth

Trigger Voltage

Trigger VoltageTrigger Voltage

(V

)(PIN 2)

(V(V

)(PIN 2))(PIN 2)

tr

trtr

Reset(PIN 4)

Reset(PIN 4) Output(PIN 3)

Reset(PIN 4)Reset(PIN 4)

Output(PIN 3)

Output(PIN 3)Output(PIN 3)

Discharging Tr.

Discharging Tr.Discharging Tr.

(PIN 7)

(PIN 7)(PIN 7)

Don't care Don't care Low Low ON

> 2Vcc / 3 Vth > 2Vcc / 3 High Low ON

V

th

Vcc / 3 < V

< 2 Vcc / 3 Vcc / 3 < Vth < 2 Vcc / 3 High - -

th

< Vcc / 3 Vth < Vcc / 3 High High OFF

V

th

When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to threshold voltage and trigger voltage. When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.

1. Monostable Operation

1. Monostable Operation1. Monostable Operation

Trigger

4

RESET

TRIG

2

OUT

3

GND

L

Figure 1. Monoatable Circuit

Figure 1. Monoatable CircuitFigure 1. Monoatable Circuit

1

8

Vcc DISCH

THRES

CONT

+Vcc

2222

10

R

A

7

6

5

C1

C2R

1010

1111

10

1010

R

0000

10

1010

-1

-1-1

10

1010

Capacitance(uF)

Capacitance(uF)Capacitance(uF)

Capacitance(uF)

-2

-2-2

10

1010

-3

-3-3

10

1010

-5

-5-5

10

1010

Figure 2. Resistance and Capacitance vs.

Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs.

RR

-4

-3

-4-4

-3-3

10

1010

Time delay( t

Time delay( tTime delay(t

Ω

ΩΩ

=1k

=1k=1k

A

AA

-2

-2-2

10

1010

Time Delay(s)

Time Delay(s)Time Delay (s)

Ω

ΩΩ

Ω

ΩΩ

10k

10k10k

10

1010

))))

dddd

1M

100k

1M

100k

1M1M

100k100 k

-1

0000

-1-1

10

1010

Ω

ΩΩ

Ω

ΩΩ

10M

10M10M

1111

2222

10

1010

Figure 3. Waveforms of Monostable Operation

Figure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable Operation

4444

LM555/NE555/SA555

Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1 and setting the flip-flop output at the same time. The voltage across the external capacitor C1, V at td=1.1R for the V

*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takes

A

to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width.

C1

increases exponentially with the time constant t=RA*C and reaches 2Vcc/3

C1

When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop, turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low. In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationship based on R

and C. Figure 3 shows the general waveforms during the monostable operation.

A

It must be noted that , for a norma l oper ati on, the trig ger pul se vo ltage needs to ma intai n a min imum of Vcc/ 3 befor e the time r output turns low. That is, alth ough the output remains unaf fected even if a dif f erent trigger pulse is applied while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse remains at below Vcc/3. Figure 4 shows such a timer output abnormality.

Figure 4. Waveforms of Monostable Operation (abnormal)

Figure 4. Waveforms of Monostable Operation (abnormal)Figure 4. Waveforms of Monostable Operation (abnormal)

2. Astable Operation

2. Astable Operation2. Astable Operation

+Vcc

R

4

RESET

TRIG

2

OUT

3

GND

L

Figure 5. Astable Circuit

Figure 5. Astable CircuitFigure 5. Astable Circuit

8

Vcc DISCH

THRES

1

CONT

7

R

6

5

C2R

A

B

C1

100k

100k100k

Ω

ΩΩ

1M

1M1M

Ω

ΩΩ

10 100

1010

Frequency(Hz)

Frequency(Hz)Frequency(Hz)

1k

1k1k

Ω

ΩΩ

10k

10k10k

Ω

ΩΩ

100 1k

100100

(R

+2R

))))

(R(R

+2R+2R

AAAA

BBBB

1k 10k

1k1k

10k 100k

100k

10k10k

100k100k

100

100100

10

1010

1111

0.1

0.10.1

Capacitance(uF)

Capacitance(uF)Capacitance(uF)

Capacitance(uF)

0.01

0.010.01

1E-3

1E-31E-3

100m

100m 111110

100m100m

Figure 6. Capacitance and Resistance vs. Frequency

Figure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. Frequency

10M

10M10M

10M

Ω

ΩΩ

5555

LM555/NE555/SA555

3

Figure 7. Waveforms of Astable Operation

Figure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable Operation

An astable timer operation is achieved by adding resistor RB to Figure 1 and con fi g ur ing as shown on Figur e 5. I n the astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi vibrator. When the timer output is high, its internal discharging Tr. turns off and the V function with the time constant (R When the V

, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high,

C1

A+RB

)*C.

increases by exponential

C1

resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges through the discharging channel formed by R

and the discharging Tr. When the VC1 falls below Vcc/3, the comparator

B

output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the V

rises again.

C1

In the above process, the section where the timer output is high is the time it takes for the V and the section where the timer output is low is the time it takes for the V

to drop from 2V cc/3 to V cc/3. Wh en time r o utpu t

C1

to rise from Vcc/3 to 2Vcc/3,

C1

is high, the equivalent circuit for charging capacitor C1 is as follows:

Vcc

dv

C

-------------

1

VC10+()VCC3⁄= 2()

VC1t() VCC1

= 3()

R

A

c1

dt

    

R

B

C1 Vc1(0-)=Vcc/

VccV0-()–

------------------------------ -= 1()

RARB+



t

-

------------------------------------–



RARB+()C1



2

-- -

–

e

3

Since the duration of the timer output high state(t

6666

) is the amount of time it takes for the VC1(t) to reach 2Vcc/3,

H

t



H

-

------------------------------------–



RARB+()C1



+()C

1

B

2

-- -

VC1t()

= 4()

V

CC

3

tHC1RAR

 

2

---

V=

+()In2 0.693 RAR

B

–

1

e



CC

3

 

== 5()

The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows:

R

B

LM555/NE555/SA555

C1

VC1(0-)=2Vcc/3

dv

C1

--------------

C

1

dt

VC1t()

2

-- -

=

3

1

---------------------- +

RAR

V

e

CC

V

C1

B

t

-------------------------------------

+()C1

RAR

D

0=+ 6()

7()

Since the duration of the timer output low state(

t

L

-------------------------------------

-

1

-- -

3

tLC1RBR

Since R

t

L

is normally RB>>RD although related to the size of discharging Tr.,

D

=0.693RBC

2

-- -

= 8()

V

CC

3

+()In2 0.693 RBR

D

1

V

RARD+()C1

e

CC

== 9()

+()C

R

D

t

) is the amount of time it takes for the VC1(t) to reach Vcc/3,

L

1

D

(10)

Consequently, if the timer operates in astable, the period is the same with 'T=t

=0.693(RA+RB)C1+0.693RBC1=0.693(RA+2RB)C1' because the period is the sum of the charge time and discharge

H+tL

time. And since frequency is the reciprocal of the period, the following applies.

frequency, f

3. Frequenc y divider

3. Frequenc y divider3. Frequency divider

1

---

T

1.44

--------------------------------------- -== 11() +()C

RA2R

1

B

By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure

8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.

7777

LM555/NE555/SA555

Figure 8. Waveforms of Frequency Divider Operation

Figure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider Operation

4. Pulse Width Modulat ion

4. Pulse Width Modulat ion4. Pulse Width Modulat ion

The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators. Figure 9 illustrates the pulse width modulation circuit. When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated according to the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control terminal. Figure 10 shows the example of pulse width modulation waveform.

+Vcc

+Vcc+Vcc

RRRR

84

GND

1

Vcc

DISCH

THRES

CONT

7

6

5

Input

InputInput

Trigger

TriggerTrigger

Output

OutputOutput

Figure 9. Circuit for Pulse Width Modulation

Figure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width Modulation

5. Pulse Position Modulation

5. Pulse Position Modulation5. Pulse Position Modulation

RESET

TRIG

2

OUT

3

AAAA

CCCC

Figure 10. Waveforms of Pulse Width Modulation

Figure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width Modulation

If the modulating signal is applied to the control terminal while the timer is connected for the astable operation as in Figure 11, the timer becomes a pulse position modulator. In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the timer output according to the modulation signal applied to the control terminal. Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave shape could be used.

8888

LM555/NE555/SA555

+Vcc

+Vcc+Vcc

RRRR

84

GND

Vcc

7

DISCH

6

THRES

Modulation

ModulationModulation

CONT

5

1

RESET

TRIG

2

Output

OutputOutput

Figure 11. Circuit for Pulse Position Modulation

Figure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position Modulation

6. Linear Ramp

6. Linear Ramp6. Linear Ramp

OUT

3

AAAA

RRRR

BBBB

CCCC

Figure 12. Waveforms of pulse position modulation

Figure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulation

When the pull-up resistor RA in the monostable circuit shown in Figure 1 is replaced with constant current source, the VC1 increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates the generated linear ramp waveforms.

+Vcc

R1

R

E

4

RESET

TRIG

2

Output

Figure 13. Circuit for Linear Ramp

Figure 13. Circuit for Linear RampFigure 13. Circuit for Linear Ramp

OUT

3

GND

8

Vcc DISCH

THRES

1

CONT

7

6

5

C2

C1

Q1

R2

Figure 14. Waveforms of Linear Ram p

Figure 14. Waveforms of Linear Ram pFigure 14. Waveforms of Linear Ram p

In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and R

V

–

CCVE

I

-------------------------- -= 12()

C

VEV

R

E

Here, V

+= 13()

BE

R

2

--------------------- -

R1R2+

E is

V

CC

.

E

For example, if Vcc=15V, R V

=0.7V+10V=10.7V

E

Ic=(15-10.7)/20k=0.215mA

=20kΩ, R1=5kW, R2=10kΩ, and VBE=0.7V,

E

9999

LM555/NE555/SA555

When the trigger starts in a timer configured as shown in Figure 13, the current flowing through capacitor C1 becomes a constant current generated by PNP transistor and resistors. Hence, the V

is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined as

C

follows:

V

pp–

S

----------------= 14() T

Here the Vp-p is the peak-to-peak voltage. If the electric charge amount accumulated in the capacitor is divided by the capacitance, the V

comes out as follows:

C

V=Q/C (15)

The above equation divided on both sides by T gives us

V

QT⁄

--- -

----------- -= 16()

T

C

and may be simplified into the following equation.

S=I/C (17)

In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant current flowi ng through th e capacitor. If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02µF, the gradient of the ramp function at both ends of the capacitor is S = 0.215m/0.022µ = 9.77V/ms.

10

1010

Mechanical Dimensions

Mechanical DimensionsMechanical Dimensions

Package

PackagePackage

6.40 ±0.20

±0.008

0.252

8-DIP

8-DIP8-DIP

Dimensions in millimeters

Dimensions in millimetersDimensions in millimeters

0.79

0.031

()

±0.10

LM555/NE555/SA555

#1

#4 #5

7.62

0.300

#8

MAX

9.60

9.20 ±0.20

0.378

5.08

MAX

0.200

3.40 ±0.20

0.134 ±0.008

0.362 ±0.008

0.33

0.013

3.30 ±0.30

0.130 ±0.012

MIN

0.46

2.54

0.018 ±0.004

0.100

1.524 ±0.10

0.060 ±0.004

0~15°

0.25

0.010

+0.10 –0.05

+0.004 –0.002

11

1111

LM555/NE555/SA555

Mechanical Dimensions

Mechanical Dimensions Mechanical Dimensions

Package

PackagePackage

#1

(Continued)

8-SOP

8-SOP8-SOP

1.55

0.061

#8

±0.20

±0.008

MAX

5.13

0.202

Dimensions in millimeters

Dimensions in millimetersDimensions in millimeters

0.1~0.25

MIN

0.004~0.001

0.56 ()

±0.008

±0.20

4.92

0.194

0.022

0.006

-0.002

0.50

0.020

+

0.004

±0.20

±0.008

0.15

-0.05

+

0.10

#4

6.00

0.236

3.95

0.156

5.72

0.225

±0.30

±0.012

±0.20

±0.008

#5

0.071

0~8°

1.80

MAX

MAX0.10

MAX0.004

1.27

0.050

±0.004

±0.10

0.41

0.016

12

1212

Ordering Information

Ordering InformationOrdering Information

Product Number

Product Number Package

Product NumberProduct Number

LM555CN 8-DIP

LM555CM 8-SOP

Product Number

Product Number Package

Product NumberProduct Number

NE555N 8-DIP NE555D 8-SOP

Product Number

Product Number Package

Product NumberProduct Number

SA555 8-DIP

SA555D 8-SOP

Package Operating Temperature

PackagePackage

Package Operating Temperature

PackagePackage

Package Operating Temperature

PackagePackage

Operating Temperature

Operating TemperatureOperating Temperature

0 ~ +70°C

Operating Temperature

Operating TemperatureOperating Temperature

0 ~ +70°C

Operating Temperature

Operating TemperatureOperating Temperature

-40 ~ +85°C

LM555/NE555/SA555

13

1313

LM555/NE555/SA555

LM555/NE555/SA555LM555/NE555/SA555

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PRODUCTS HEREI N TO IMPROVE RELIABILITY, FUNCTIO N OR DESIGN. FAIRCH IL D DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER IT S PATENT RIGHTS, NOR THE RIGHTS OF OTHE RS.

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11/29/02 0.0m 001

 2002 Fairchild Semiconductor Corporation

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