If the output current I
OUT
is known, by assuming that I
OUT
=
IL, the peak and valley of ILR can be determined. Beware that
the peak of ILR should not be larger than the saturation current
of the inductor and the current rating of the main and synchronous MOSFETs. Also, the valley of ILR must be positive
if CCM operation is required.
30029732
FIGURE 5. Inductor selection for V
OUT
= 3.3V
30029733
FIGURE 6. Inductor selection for V
OUT
= 0.6V
Figures 5 and 6 show curves on inductor selection for various
V
OUT
and RON. According to (8), VIN is limited for small RON.
Some curves are therefore limited as shown in the figures.
C
VCC
: The capacitor on the VCC output provides not only noise
filtering and stability, but also prevents false triggering of the
VCC UVLO at the main MOSFET on/off transitions. C
VCC
should be no smaller than 1 µF for stability, and should be a
good quality, low ESR, ceramic capacitor.
C
OUT
and C
OUT3
: C
OUT
should generally be no smaller than
10 µF. Experimentation is usually necessary to determine the
minimum value for C
OUT
, as the nature of the load may require
a larger value. A load which creates significant transients requires a larger C
OUT
than a fixed load.
C
OUT3
is a small value ceramic capacitor located close to the
LM3103 to further suppress high frequency noise at V
OUT
. A
47 nF capacitor is recommended.
CIN and C
IN3
: The function of CIN is to supply most of the main
MOSFET current during the on-time, and limit the voltage ripple at the VIN pin, assuming that the voltage source connecting to the VIN pin has finite output impedance. If the voltage
source’s dynamic impedance is high (effectively a current
source), CIN supplies the difference between the instantaneous input current and the average input current.
At the maximum load current, when the main MOSFET turns
on, the current to the VIN pin suddenly increases from zero
to the valley of the inductor’s ripple current and ramps up to
the peak value. It then drops to zero at turn-off. The average
current during the on-time is the load current. For a worst case
calculation, CIN must be capable of supplying this average
load current during the maximum on-time. CIN is calculated
from:
(10)
where I
OUT
is the load current, ton is the maximum on-time,
and ΔVIN is the allowable ripple voltage at VIN.
C
IN3
’s purpose is to help avoid transients and ringing due to
long lead inductance at the VIN pin. A low ESR 0.1 µF ceramic
chip capacitor located close to the LM3103 is recommended.
C
BST
: A 33 nF high quality ceramic capacitor with low ESR is
recommended for C
BST
since it supplies a surge current to
charge the main MOSFET gate driver at each turn-on. Low
ESR also helps ensure a complete recharge during each offtime.
CSS: The capacitor at the SS pin determines the soft-start
time, i.e. the time for the reference voltage at the regulation
comparator and therefore, the output voltage to reach their
final value. The time is determined from the following equation:
(11)
CFB: If the output voltage is higher than 1.6V, CFB is needed
in the Discontinuous Conduction Mode to reduce the output
ripple. The recommended value for CFB is 10 nF.
PC BOARD LAYOUT
The LM3103 regulation, over-voltage, and current limit comparators are very fast so they will respond to short duration
noise pulses. Layout is therefore critical for optimum performance. It must be as neat and compact as possible, and all
external components must be as close to their associated
pins of the LM3103 as possible. Refer to the functional block
diagram. The loop formed by CIN, the main and synchronous
MOSFET internal to the LM3103, and the PGND pin should
be as small as possible. The connection from the PGND pin
to CIN should be as short and direct as possible. Vias should
be added to connect the ground of CIN to a ground plane,
located as close to the capacitor as possible. The bootstrap
capacitor C
BST
should be connected as close to the SW and
BST pins as possible, and the connecting traces should be
thick. The feedback resistors and capacitor R
FB1
, R
FB2
, and
CFB should be close to the FB pin. A long trace running from
V
OUT
to R
FB1
is generally acceptable since this is a low
impedance node. Ground R
FB2
directly to the AGND pin (pin
7). The output capacitor C
OUT
should be connected close to
the load and tied directly to the ground plane. The inductor L
should be connected close to the SW pin with as short a trace
as possible to reduce the potential for EMI (electromagnetic
interference) generation. If it is expected that the internal dis-
13 www.national.com
LM3103