Datasheet LM2650MX-ADJ, LM2650M-ADJ Datasheet (NSC)

LM2650
Synchronous Step-Down DC/DC Converter

LM2650 Synchronous Step-Down DC/DC Converter

June 1999

General Description

The LM2650 is a step-down DC/DC converter featuring high
efficiency over a 3A to milliamperes load range. This feature
makes the LM2650 an ideal fit in battery-powered applica­tions that demand long battery life in both run and standby
modes.

The LM2650 alsofeatures a logic-controlled shutdown mode
in which it draws at most 25µA from the input power supply.

The LM2650 employs a fixed-frequency pulse-width modula­tion (PWM) and synchronous rectification to achieve very
high efficiencies. In many applications, efficiencies reach
95%+ for loads around 1A and exceed 90%for moderate to
heavy loads from 0.2A to 2A.

A low-power hysteretic or ″sleep″ mode keeps efficiencies
high at light loads. The LM2650 enters and exits sleep mode
automatically as the load crosses ″sleep in″ and ″sleep out″
thresholds. The LM2650 provides nodes for programming
both thresholds via external resistors. A logic input allows the
user to override the automatic sleep feature and keep the
LM2650 in PWM mode regardless of the load level.

An optional soft-start feature limits current surges from the
input power supply at start up and provides a simple means
of sequencing multiple power supplies.

Typical Application

Features

n Ultra high efficiencies (95%possible)
n High efficiency over a 3A to milliamperes load range
n Synchronous switching of internal NMOS power FETs
n Wide input voltage range (4.5V to 18V)
n Output voltage adjustable from 1.5V to 16V
n Automatic low-power sleep mode
n Logic-controlled micropower shutdown (I
n Frequency adjustable up to 300 kHz
n Frequency synchronization with external signal
n Programmable soft-start
n Short-circuit current limiting
n Thermal shutdown
n Available in 24-lead Small-Outline package

QSD

≤ 25 µA)

Applications

n Notebook and palmtop personal computers
n Portable data terminals
n Modems
n Portable Instruments
n Global positioning devices (GPSs)
n Battery-powered digital devices

LM2650-ADJ Efficiency

DS012848-1

Converting a Four-Cell Li Ion Battery to 5V

© 1999 National Semiconductor Corporation DS012848 www.national.com

DS012848-2

Connection Diagram

DS012848-14

24-Lead Small Outline Package (M)

Order Number LM2650M-ADJ

See Package Number M24B

Pin Descriptions

(Refer to the Block Diagrams)

Pins Description

1, 12 SUB: These pins make electrical contact with the substrate of the die. Ground them. For best thermal

performance, ground them to the same large, uninterrupted copper plane as the PGND pins.

2 SLEEP LOGIC: Use this logic input to select the conversion mode; low selects PWM, high selects sleep, and

high impedance (open) permits the LM2650 to move freely and automatically between the modes, using PWM
for moderate to heavy loads and sleep for light loads.

3, 4, 9, 10 PGND: The ground return of the power stage. The power stage consists of the two power switches Q1 and

Q2, the gate drivers DH and DL, and the linear voltage regulators VRegH and VRegL. For best electrical and
thermal performance, ground these pins to a large, uninterrupted copper plane.

5, 8 SW: The output node of the power stage. It swings from slightly below ground to slightly below the voltage to

. To minimize the effects of switching noise on nearby circuitry, keep all traces originating from SW short

PV

IN

and to the point. Route all traces carrying signals well away from the SW traces.

6, 7 PV

: The positive supply rail of the power stage. Bypass each PVINpin to PGND with a 0.1 µF capacitor. Use

IN

capacitors having low ESL and low ESR, and locate them close to the IC.

11 BOOT: The positive supply rail of the high-side gate driver DH. Connect a 0.1 µF capacitor from this node to

SW. Bootstrapping action creates a supply rail about 9V above that at PV

the gate of the NMOS power FET Q1. Overriding ensures low R
13 FB: The feedback input.
14 V

: An internal regulator steps the input voltage down to a 4V rail used by the signal-level circuitry. VDDis the

DD

output node of this regulator. Bypass V
15 COMP: The inverting input of the error amplifier EA.
16 EA OUT: The output node of the error amplifier EA.
17 SS: The soft start node. Connect a capacitor from SS to GND.
18 GND: The ground return of the signal-level circuitry.
19 V

: The positive supply rail of the internal 4V regulator. Bypass VINto GND close to the IC with a 0.1 µF

IN

capacitor.
20 FREQ ADJ: The LM2650 switches at a nominal 90 kHz. Connect a resistor between FREQ ADJ and GND to

adjust the frequency up from the nominal. Use the graph under Typical performance Characteristics to select

the resistor.
21 SYNC: The synchronization input. If the switching frequency is to be synchronized with an external clock

signal, apply the clock signal here.
22 SD: Use this logic input to control shutdown; pull low for operation, high for shutdown.
23 SLEEP OUT ADJ (SOA): The value of the resistor connected between SIA and ground programs the sleep-in

threshold. Higher values program lower thresholds.
24 SLEEP IN ADJ (SIA): The value of the resistor connected between SIA and ground programs the sleep-in

threshold. Higher values program lower thresholds.

Top View

, and DH uses this rail to override

IN

.

DS(on)

to GND close to the IC with a 0.2 µF capacitor.

DD

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

(All voltages are referenced to the PGND and GND pins.)
DC Voltage at PV
DC Voltage at SD, SLEEP LOGIC

and SYNC 15V
DC current into SW
Junction Temperature Limited by the IC
DC Power Dissipation (Note 2) 1.28W
Storage Temperature −65˚C to +150˚C

IN

and V

±

20V

7.5A

IN

Soldering Time, Temperature (Note

3)
Wave (4 seconds)
Infrared (10 seconds)
Vapor Phase (75 seconds)

260˚C
240˚C
219˚C

ESD Susceptibility (Note 4) 1.3 kV

Operating Ratings (Note 1)

Supply Voltage Range (PV

) 4.5V to 18V

V

IN

Junction Temperature Range −40˚C to +125˚C

and

IN

Electrical Characteristics

V

= 15V, V

PVIN

type apply for T
Operating Ratings.

SLEEP LOGIC

A=TJ

=

0V and V

= +25˚C. Limits appearing in boldface type apply over the full junction temperature range shown under

Symbol Parameter Conditions Typ (Note 5) Limit (Note 6) Units

V

OUT

Output Voltage R1=75 kΩ,1%,

η1 System Efficiency I

η2 System Efficiency I

V

I

I

I

R

REF

Q

QS

QSD

DS(on)

Reference Voltage V

Quiescent Current in PWM
mode

Quiescent Current in Sleep
mode

Quiescent Current in Shutdown
mode

HS DC On-Resistance

Drain-to-Source of the
High-Side Power Switch

LS DC On-Resistance

R

DS(on)

Drain-to-Source of the
Low-Side Power Switch

I

LHS

I

LLS

I

LIMIT

F

F

D

OSC

MAX

MAX

Leakage current of the
High-Side Power Switch

Leakage current of the
Low-Side Power Switch

Active Current Limit of the
High-Side Power Switch

Oscillator Frequency V

Maximum Oscillator Frequency I

Maximum Duty Cycle V

=

0V unless superseded under Conditions. Typicals and limits appearing in plain

SD

5.00

R2=25 kΩ,1%,

7.5V ≤ V

0.12A ≤ I

LOAD

F

OSC

LOAD

F

OSC
SLEEPLOGIC

V

FB

−20mV (Note 8)
IV

FB

V

SLEEPLOGIC

≤ 18V

PVIN

LOAD

=

1A, T

Not Adjusted

=

3A, T

Not Adjusted

=

=

V

REF

=

−20mV,

V

REF

=

≤ 3A

A

A

VSD=3V
(Note 8)

=

1A,

I

DS

V

SLEEPLOGIC

V

FB

V

BOOT

=

I

DS

V

FB

V

PVIN

V

SD

V

PVIN

V

SD

V

PVIN

V

BOOT

V

FB

V

SLEEPLOGIC
FB

=

=

3V,

=

24V

1A,

=

3V

=

18V, V

=

3V

=

18V, V

=

3V

=

15V,

=

24V,

=

3V,

=

=

−20 mV 90

V

REF

=

25˚C,

=

25˚C,

3V (Note 7)

3V (Note 8)

3V,

=

0V,

SW

=

18V,

SW

3V,

94

89

1.25

4.0

850

9

130

125

100

95

5.5

4.80/4.75

5.20/5.25

1.281/1.294

1.219/1.206

6.50/7.0

1.35/1.60

20/25

170/245

175/245

10

210

3.5

7.5

80/75

100/105

FREQ ADJ

=

V

FB

=

FB

F

OSC

=

100µA,(Note 9)

−20 mV

V

REF

−20 mV,

V

REF

Not Adjusted

315

270/260
360/370

97

94/93

V

V(min)

V(max)

%

%

V(min)

V(max)

mA

mA(max)

µA

mA(max)

µA

µA(max)

mΩ

mΩ(max)

mΩ

mΩ(max)

nA

µA(max)

µA

µA(max)

A

A(min)

A(max)

kHz

kHz(min)

kHz(max)

kHz

kHz(min)

kHz(max)

%

%

(min)

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Electrical Characteristics (Continued)

V

= 15V, V

PVIN

type apply for T
Operating Ratings.

SLEEP LOGIC

A=TJ

=

0V and V

= +25˚C. Limits appearing in boldface type apply over the full junction temperature range shown under

Symbol Parameter Conditions Typ (Note 5) Limit (Note 6) Units

D

MIN

V

DD

V

BOOT

I

SS

V

HYST

T

SD

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the device operates
correctly. Operating ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Char­acteristics.

Note 2: This rating is calculated using the formula P
junction temperature, and θ
78˚C/W for T
the safe dissipation of more power. See Application Notes on thermal management. The LM2650 actively limits its junction temperature to about 170˚C.

Note 3: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook published by National Semiconductor Corporation.
Note 4: ESD is applied using the human-body model, a 100pF capacitor discharged through a 1.5kΩ resistor.
Note 5: A typical is the center of characterization data taken at T
Note 6: All limits are guaranteed. The guarantee is backed with 100%testing at T
Note 7: V
Note 8: Quiescent current is the total current flowing into the P

nominal switching frequency. I
Note 9: Pulling 100µA out of FREQ ADJ simulates adjusting the oscillator frequency with a 12.5 kΩ resistor connected from FREQ ADJ to GND. The sleep mode

cannot be used at switching frequencies above 250 kHz.

Minimum Duty Cycle V

Internal Rail Voltage I

Bootstrap Regulator Voltage
(VRegH)

Soft Start Current 10

Hysteresis of the Sleep
Comparator (C2

of SD 0.95 V(max)

V

IL

V

of SD 2.10 V(min)

IH

V

of SLEEP LOGIC 0.9 V(max)

IL

V

of SLEEP LOGIC 2.0 V(min)

IH

V

of SYNC 0.50 V(max)

IL

V

of SYNC 1.45 V(min)

IH

Figure 2

TJfor Thermal Shutdown 170 ˚C

is the junction ot ambient thermal resistance of the package. The P

JA

and θJArespectively.A θJAof 78˚C represents the worst condition of no heat sinking of the M24B small-outline package. Heat sinking allows

Jmax,TA

is measured at SLEEP OUT ADJ.

REF

includes no such current.

QS

=

0V unless superseded under Conditions. Typicals and limits appearing in plain

SD

=

+50 mV,

V

FB

REF

Not Adjusted

F

OSC

=1mA 4.0

VDD

2.8

5

3.6/3.4

4.2/4.3

I

=1mA 7.5

BOOT

6.5/6.0

13.5/20.0

V

)

SLEEPLOGIC

=

3V 30

10
50

DCmax

=

)/θJA, where P

(T

Jmax−TA

= 25˚C.

A=TJ

and VINpins. IQincludes the current used to drive the gates of the two NMOS power FETsat the

VIN

A=TJ

is the absolute maximum power dissipation, T

DCmax

= 125˚C and statistical correlation for room temperature and cold limits.

rating of 1.28W results from substituting 170˚C, 70˚C and

DCmax

is the maximum

Jmax

%

V(min)

V(max)

V(min)

µA(max)

mV(min)

mV(max)

%

(min)

V

V

µA

mV

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Typical Performance Characteristics

I

vs Input Voltage

QSD

IQSvs Input Voltage

IQvs Input Voltage

IQvs Oscillator Frequency

R

Low-Side vs Junction

DS(on)

Temperature

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DS012848-6

DS012848-9

R

Low-Side vs Input Voltage

DS(on)

R

High-Side vs Junction

DS(on)

Temperature

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DS012848-7

DS012848-10

DS012848-5

R

High-Side vs Input Voltage

DS(on)

DS012848-8

Oscillator Frequency vs Junction
Temperature

DS012848-11

Oscillator Frequency vs Adjusting Resistor

DS012848-12

Current Limit vs Junction Temperature

DS012848-13

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Block Diagrams

FIGURE 1. The PWM Circuit with External Components in a Closed Control Loop

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DS012848-16

FIGURE 2. The Hysteretic or ″Sleep″ Circuit with External Components in a Closed Control Loop

DS012848-21

FIGURE 3. The Internal Voltage Regulator and Voltage Reference used by Both the PWM and Hysteretic Circuits

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Operation

OVERVIEW

The LM2650 uses two step-down conversion modes:
fixed-frquency pulse-width modulation (PWM) and hyster­etic. It moves freely and automatically between them, using
PWM for moderate to heavy loads and hysteretic for light
loads.

For clarity, separate block diagrams for each conversion
mode have been included. See
Blocks used in both modes appear in both diagrams with the
same label. For example, both modes use the input buffer B.
To keep the diagrams simple, most power supply rails have
been omitted. R3, C10, R
are outside the IC.

THE PWM CIRCUIT (

Figure 1

The PWM is a fixed-frequency, voltage-mode pulse-width
modulator. It consists of four functional blocks: an input
buffer, an error amplifier, a modulator, and a power stage.

1. The input buffer B: B is a voltage follower. A fraction of
the output voltage is fed back to its noninverting input
FB. Circumventing B by using the COMP input as the
feedback input will cause the IC to malfunction.

2. The error amplifier EA: EA is a voltage amplifier. It sub­tracts the feedback voltage from the 1.25V reference
and amplifies the difference to produce an error voltage
for the control loop. For the purpose of loop compensa­tion, EA is typically configured as an integrator. In this
configuration, a capacitor C
nected in series between the inverting input COMP and
the output terminal EA OUT.The capacitor and the inter­nal 6.5kΩ resistor create a pole, while the capacitor and
series resistor create a zero.

3. The modulator: The modulator is the heart of the PWM
circuit. It consists of the 90 kHz oscillator, the voltage
comparator C1, and output logic represented here as a
simple SR latch.

The modulator generates a continuous stream of rectan­gular, signal-level. It generates the pulses at a fixed fre­quency, and it modulates or varies their widths in re­sponse to variations in the error voltage. The pulses
appear at Q, the output of the SR latch. An increase in
the error voltage results in a proportional increase in the
pulse widths, and, conversely, a decrease in the error
voltage results in a proportional decrease in the pulse
widths.

The oscillator produces a 90 kHz sawtooth that ramps
between 1V and 2V. At the beginning of each ramp, the
oscillator sets the SR latch sending Q high. As the ramp
voltage surpasses the error voltage, C1 resets the SR
latch sending Q low. An increase in the error voltage in­creases the time between the setting and the resetting of
the SR latch which , in turn, results in an equal increase
in pulse widths: that is, an equal increase in the time Q
spends high in each cycle. A decrease in the error volt­age has the opposite effect on the pulse widths as it de­creases the time between the setting and resetting of the
SR latch.

4. The power stage: The power stage puts some punch be­tween the output of the modulator by translating the
stream of signal-level pulses generated by the modula­tor into a stream of power pulses that swing from ground
up to the input voltage while sinking and sourcing as
much as 3.5A. The power stage consists of two gate

Figure 1

C,CC,CB

, L1, R1, R2, and C

)

and a resistor RCare con-

C

and

Figure 2

OUT

drivers DH and DL, two linear voltage regulators VRegH
and VRegL, and two NMOS power FETs Q1 and Q2.

The power pulses appear at the SW mode. When Q
goes high, DL drives the gate of Q2 low turning Q23 off.
While Q2 turns off, the SW potential may remain at just
below ground as the body diode of Q2 conducts what
was previously reverse current (source-to-drain) in Q2,
or the SW potential may swing up to just above the input
voltage as the body diode of Q1 conducts what was pre-

.

viously forward current (drain-to-source) in Q2. About 50
ns after Q goes high, DH drives the gate of Q1 high turn­ing Q1 on. If the task remains, Q1 pulls the SW potential
up, if not, Q1 simply takes over the conduction responsi­bility from its own body diode. When Q goes low, the in­verse action occurs resulting in the SW potential swing­ing from the input voltage to the ground. The 50 ns delay
between one switch beginning to turn off and the other
switch beginning to turn on prevents the switches from
″shooting through″ directly from the input supply to the
ground.

The PWM circuit drives the pulse stream into the
low-pass filter made up of L1 and C
passed the DC component of the stream and attenuates
the AC components. The output of the filter is the DC
voltage V
Since the DC component of any periodic waveforms the
average value of the waveform, V
ing:

superimposed with a small ripple voltage.

OUT

OUT

Here T is the switching period in seconds V(t) is the pulse
stream. Under DC steady-state conditions, (1) yields

Here V

is the input voltage, and therefore the height of the

IN

pulses, in volts, is the width of the pulses in seconds, and D
is the ratio of t
The output voltage is programmed using the resistive divider

to T, the duty or the duty cycle.

ON

made up for R1 and R2,

As Q1 turns on, its source voltage swings up to just below
the input voltage. The LM2650 uses a simple technique
called ″bootstrapping″ to pull the positive supply rail of DH
(at BOOT) up along with the source voltage of Q1, but to a
voltage above the input voltage. Because the source of Q1
and the positive supply rail of DH make the same voltage
swing together, DH maintains the positive gate-to-source
voltage required to turn Q1 on. Q12 plays an active role in
pulling the supply rail of DH up and is therefore said to pull it­self up by its ″bootstraps″, thus the name of the technique
and of the BOOT pin.
In the typical application, a capacitor CB is connected out­side the IC between the BOOT and SW pins. When Q2 is on,
the input supply charges CB through VRegH and the internal
diode D.

THE HYSTERETIC CIRCUIT AND LOOP (

Except for C2, the hysteretic circuit borrows all its circuit
blocks from the PWM circuit.

The hysteretic comparator C2 is a voltage comparator with
built-in hysteresis V

1.25V.

of typically 30mV centered at

HYST

. The filter

OUT

can be found us-

(1)

(2)

(3)

Figure 2

)

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Operation (Continued)

The diode D2 is the body diode of Q2. The hysteretic circuit
uses D2 as a rectifier instead of switching Q2 as a synchro­nous rectifier.

When the load current drops below the prescribed sleep-in
threshold, the LM2650 shuts down the PWM loop and starts
up the hysteretic loop. The hysteretic loop supports light
loads more efficiently because it uses less power to support
its own operation; it uses less bias power because it’s a sim­pler loop having less circuit blocks to bias, and it switches
slower, so it incurs lower switching losses.

The hysteretic control loop does not switch at a constant fre­quency. Instead, it monitors V
V

reaches either side of a narrow window centered on

OUT

the desired output voltage. C2 directs the switching based
on its reading of the feedback voltage. Switching in this man­ner yields a regulated voltage consisting of the desired out­put voltage and an AC ripple voltage. The magnitude of the
AC component can be approximated using

and switches only when

OUT

back voltage just surpasses the lower hysteretic threshold of
C2, the output of C2 changes states from low to high, and
DH responds by pulling the gate of Q1 up turning Q1 on and
starting the hysteretic cycle over.

Note that as the load current decreases, it takes increasingly
longer periods for the load current to discharge C
through the hysteretic window, and as the load current in-

OUT

creases, the periods become even shorter. It can be seen
from the above observation that the switching frequency of
the hysteretic loop varies as the load varies. The switching
frequency can be approximated using

(6)

Here f is the switching frequency in hertz, I is the load current
in amperes, C
V

OUT_PP

Typical switching frequencies range anywhere from a few

is the value of the capacitor in farads, and

OUT

is the magnitude of the AC ripple voltage in volts.

hertz for very light loads to a few thousand hertz for light
loads bordering on the moderate level.

(4)

For example, with V
120mV,

OUT

set to 5V,V

OUT_PP

is approximately

(5)

When it starts up, the hysteretic loop turns Q1 on. While Q1
is on, the input power supply charges C
current to the load. Current from the supply reaches C and

and supplies

OUT

the load via the series path provided by Q1 and L1. As the
feedback voltage just surpasses the upper hysteretic thresh­old of C2, the output of C2 changes from high to low, and HD
responds by pulling the gate of Q1 down turning Q1 off. As
Q1 turns off, L1 generates a negative-going voltage transient
that D2 clamps at just below ground. D2 remains on only
briefly as the current in L1 runs out. While both Q1 and D2
are off, C

alone supplies current to the load. As the feed-

OUT

Application Circuits

Figure 4

is a schematic of the typical application circuit. use
the component values shown in the figure and those con­tained in

Table 1

DC/DC converter. As with the design of any DC/DC con­verter, the design of these circuits involved tradeoffs be­tween efficiency, size, and cost. Here more weight was given
to efficiency than to size as evidenced by the low switching
frequency which keeps switching losses low but pushes the
value and size of the inductor up.

From a smaller circuit, use the component values shown in

Figure 4

slightly higher switching losses for a much smaller inductor.
Note,

Figure 4

adjust the switching frequency from 90 kHz up to 200 kHz.
Connect R

to build a 5V, 3A, or 3.3V, 3A step-down

and those contained in

Table3

. These circuits trade

does not show RFA, the resistor required to

between the FREQ ADJ pin and ground.

FA

FIGURE 4. The Typical 90 kHz Application Circuit

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DS012848-19

Application Circuits (Continued)

TABLE 1. Components for the Typical 90 kHz Application Circuit

Input Voltage 7V to 18V IN

Applicable Cell Stacks 8 to 12 Cell NiCd or NiMh, 3 to 4 Cell Li Ion, 8 to 11 Cell Alkaline, 6 Cell

Output 5V, 3A Out 3.3V, 3A out

Input Capacitor C

IN

Inductor L1 40µH (See

Output Capacitor C

OUT

Feedback Resistors R1

and R2

Compensation

Components R

and C

Sleep Resistors R

and R

10

SOA

C,CC,R3

SIA

,

2 x 22 µF, 35V AVX TPS

Series or Sprague 593D Series

Table 2

3x220 µF, 10V AVX TPS

Series or Sprague 593D Series

R1=75kΩ,1%,

R2=24.9kΩ,1%,

=

R

37.4 kΩ,

C

=

4.7 nF,

C

C

=

3.57 kΩ,

R

3

=

5.6 nF

C

10

=

R

33 kΩ,

SIA

=

200 kΩ

R

SOA

TABLE 2. Toroidal Inductors Using Cores from MICROMETALS, INC.

Lead Acid

2 x 22 µF, 35V AVX TPS

Series or Sprague 593D Series

) 33µH (See

3x220 µF, 10V AVX TPS

Series or Sprague 593D Series

R1=41.2kΩ,1%,
R2=24.9kΩ,1%,

=

R

C

=

C

C

=

R

3

C

10

R

SIA

R

SOA

23.2 kΩ,

8.2 nF,

2.0 kΩ,

=
=

=

Table 2

10 nF
39 kΩ,

130 kΩ

)

Core

Number

15µH T38 −52 AWG
20µH T38 −52 AWG
33µH T50 −52 AWG
40µH T50 (B) −18 AWG

MICROMETALS
5615 E. La Palma Ave. Anaheim, CA 92807 USA [phone]

Core

Material

Wire

Gauge

#

23 1 21

#

23 1 25

#

21 1 41

#

21 1 41

Number of

Strands

TABLE 3. Components for Typical 200 kHz Applications

Input Voltage 7V to 18V IN

Applicable Cell Stacks 8 to 12 Cell NiCd or NiMh, 3 to 4 Cell Li Ion, 8 to 11 Cell Alkaline, 6 Cell

Lead Acid

Output 5V, 3A Out 3.3V, 3A out

Input Capacitor C

IN

Inductor L1 20µH (See

Output Capacitor C

OUT

Feedback Resistors R1

and R2

Compensation

Components R

and C

Sleep Resistors R

and R

10

SOA

C,CC,R3

SIA

,

Frequency Adjusting

Resistor R

FA

2 x 22 µF, 35V AVX TPS

Series or Sprague 593D Series

Table 2

) 15µH (See

3x220 µF, 10V AVX TPS

Series or Sprague 593D Series

R1=75kΩ,1%,

R2=24.9kΩ,1%,

=

R

53.6 kΩ,

C

=

2.7 nF,

C

C

=

4.02 kΩ,

R

3

=

4.7 nF

C

10

=

R

33 kΩ,

SIA

=

200 kΩ

R

SOA

=

R

24.9 kΩ R

FA

2 x 22 µF, 35V AVX TPS

Series or Sprague 593D Series

3x220 µF, 10V AVX TPS

Series or Sprague 593D Series

R1=41.2kΩ,1%,
R2=24.9kΩ,1%,

=

R

33.2 kΩ,

C

=

C

C

=

3.01 kΩ,

R

3

=

C

10

=

R

SIA

=

R

SOA

=

FA

Table 2

3.9 nF,

6.8 nF
47 kΩ,

91 kΩ

24.9 kΩ

Number of

Turns

)

www.national.com9

Application Circuits (Continued)

FIGURE 5. An Efficient, 2%Accurate 5V to 3.3V Converter

DS012848-20

www.national.com 10

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small-Outline Package (M)

Order Number LM2650M-ADJ

NS Package Number M24B

LM2650 Synchronous Step-Down DC/DC Converter

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