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November 1, 2007
LM20242
36V, 2A PowerWise® Adjustable Frequency Synchronous
Buck Regulator
General Description
The LM20242 is a full featured 1MHz capable synchronous
buck regulator capable of delivering up to 2A of load current.
The current mode control loop is externally compensated with
only two external components, offering both high performance and ease of use. The device is optimized to work over
the input voltage range of 4.5V to 36V making it well suited
for high voltage systems.
The device features internal Over Voltage Protection (OVP)
and Over Current Protection (OCP) circuits for increased system reliability. A precision Enable pin and integrated UVLO
allows the turn on of the device to be tightly controlled and
sequenced. Startup inrush currents are limited by both an internally fixed and externally adjustable soft-start circuit. Fault
detection and supply sequencing are possible with the integrated PGOOD circuit.
The LM20242 is designed to work well in multi-rail power
supply architectures. The output voltage of the device can be
configured to track a higher voltage rail using the SS/TRK pin.
If the output of the LM20242 is pre-biased at startup it will not
sink current to pull the output low until the internal soft-start
ramp exceeds the voltage at the feedback pin.
The LM20242 is offered in an exposed pad 20 pin TSSOP
package that can be soldered to the PCB, eliminating the
need for bulky heatsinks.
Features
■
2A Output Current, 3.7A peak current
■
130 mΩ/110 mΩ integrated power MOSFETs
■
1.5% output voltage accuracy
■
Current Mode Control, selectable compensation
■
Resistor programmed, 1MHz capable oscillator
■
Synchronous rectifier with diode emulation
■
Adjustable output voltage down to 0.8V
■
Compatible with pre-biased loads
■
Programmable soft-start with external capacitor
■
Precision enable pin with hysteresis
■
OVP, UVLO inputs and PGOOD output
■
Internally protected with peak current limit, thermal
shutdown and restart
■
Accurate current limit with frequency foldback
■
Non-linear current mode slope compensation
■
eTSSOP-20 exposed pad package
Applications
■
Simple to design, high efficiency point of load regulation
from a 4.5V to 36V bus
■
High Performance DSPs, FPGAs, ASICs and
Microprocessors
■
Communications Infrastructure, Automotive
Simplified Application Circuit
30031401
PowerWise® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation 300314 www.national.com
LM20242 36V, 2A PowerWise
®
Adjustable Frequency Synchronous Buck Regulator
Page 2
Connection Diagram
30031402
Top View
eTSSOP-20 Package
Ordering Information
Order Number Package Type NSC Package Drawing Package Marking Supplied As
LM20242MH eTSSOP-20 MXA20A 20242MH 73 Units per Rail
LM20242MHE 250 Units per Tape and Reel
LM20242MHX 2500 Units per Tape and Reel
Pin Descriptions
Pin(s) Name Description Application Information
1 SS/TRK Soft-Start or Tracking control input An internal 5 µA current source charges an external capacitor to set
the soft-start rate. The PWM can Track to an external voltage ramp
with a low impedance source. If left open, an internal 1 ms SS ramp
is activated.
2 FB Feedback input to the error amplifier
from the regulated output
This pin is connected to the inverting input of the internal
transconductance error amplifier. An 800 mV reference is internally
connected to the non-inverting input of the error amplifier.
3 PGOOD Power good output signal Open drain output indicating the output voltage is regulating within
tolerance. A pull-up resistor of 10 kΩ to 100 kΩ is recommended if this
function is used.
4 COMP Output of the internal error amplifier and
input to the Pulse Width Modulator
The loop compensation network should be connected between the
COMP pin and the AGND pin.
5,6,15,16 VIN Input supply voltage Nominal operating range: 4.5V to 36V.
7,8,13,14 SW Switch pin The drain terminal of the internal Synchronous Rectifier power
NMOSFET and the source terminal of the internal Control power
NMOSFET.
9,10,11 GND Ground Internal reference for the power MOSFETs.
12 AGND Analog ground Internal reference for the regulator control functions.
17 BOOT Boost input for bootstrap capacitor An internal diode from VCC to BOOT charges an external capacitor
required from SW to BOOT to power the Control MOSFET gate driver.
18 VCC Output of the high voltage linear
regulator. The VCC voltage is regulated
to approximately 5.5V.
VCC tracks VIN up to about 7.2V. Above VIN = 7.2V, VCC is regulated
to approximately 5.5 Volts. A 0.1 µF to 1 µF ceramic decoupling
capacitor is required. The VCC pin is an output only.
19 EN Enable or UVLO input An external voltage divider can be used to set the line undervoltage
lockout threshold. If the EN pin is left unconnected, a 2 µA pull-up
current source pulls the EN pin high to enable the regulator.
20 RT Internal oscillator frequency adjust input Normally biased at 550 mV. An external resistor connected between
RT and AGND sets the internal oscillator frequency.
EP Exposed
Pad
Exposed pad Exposed metal pad on the underside of the package with a weak
electrical connection to GND. Connect this pad to the PC board ground
plane in order to improve heat dissipation.
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LM20242
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN to GND -0.3V to +38V
BOOT to GND -0.3V to +43V
BOOT to SW -0.3V to +7V
SW to GND -0.5V to +38V
SW to GND (Transient) -1.5V (< 20 ns)
FB, EN, SS/TRK, PGOOD to
GND
-0.3V to +6V
VCC to GND -0.3V to +8V
Storage Temperature -65°C to 150°C
ESD Rating
Human Body Model (Note 2) 2kV
Operating Ratings
VIN to GND +4.5V to +36V
Junction Temperature −40°C to + 125°C
Electrical Characteristics Unless otherwise stated, the following conditions apply: V
VIN
= 12V. Limits in standard
type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum
and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only.
Symbol Parameter Conditions Min Typ Max Units
V
FB
Feedback pin voltage V
VIN
= 4.5V to 36V
V
COMP
= 500 mV to 700 mV
0.788 0.8 0.812 V
R
HSW-DS(ON)
High-Side MOSFET On-Resistance ISW = 200 mA 130 225
mΩ
R
LSW-DS(ON)
Low-Side MOSFET On-Resistance ISW = 200 mA 110 190
mΩ
I
Q
Operating Quiescent Current V
VIN
= 4.5V to 36V 2 3 mA
I
SD
Shutdown Quiescent current VEN = 0V 150 180 µA
V
UVLO
VIN Under Voltage Lockout Rising V
VIN
3.65 3.9 4.2 V
V
UVLO(HYS)
VIN Under Voltage Lockout Hysteresis 200 400 mV
V
VCC
VCC Voltage I
VCC
= -5 mA, VEN = 5V 5.5 V
I
SS
Soft-Start Pin Source Current VSS = 0V 3 5 7 µA
I
BOOT
BOOT Diode Leakage V
BOOT
= 4V 10 nA
V
F-BOOT
BOOT Diode Forward Voltage I
BOOT
= -100 mA 0.9 1.1 V
Powergood
V
FB(OVP)
Over Voltage Protection Rising Threshold V
FB(OVP)
/ V
FB
107 110 112 %
V
FB(OVP-HYS)
Over Voltage Protection Hysteresis
Δ
VFB(OVP)
/ V
FB
2 3 %
V
FB(PG)
PGOOD Rising Threshold V
FB(PG)
/ V
FB
93 95 97 %
V
FB(PG-HYS)
PGOOD Hysteresis
Δ
VFB(PG)
/ V
FB
2 3 %
T
PGOOD
PGOOD delay 20 µs
I
PGOOD(SNK)
PGOOD Low Sink Current V
PGOOD
= 0.5V 0.6 1 mA
I
PGOOD(SRC)
PGOOD High Leakage Current V
PGOOD
= 5V 5 200 nA
Oscillator
F
SW1
Switching Frequency 1
RRT = 49.9 kΩ
675 750 825 kHz
F
SW2
Switching Frequency 2
RRT = 249 kΩ
225 250 325 kHz
T
OFF-TIME
Minimum Off Time 50 ns
V
RT
RT pin voltage
RRT = 250 kΩ
550 mV
Error Amplifier
I
FB
Feedback pin bias current VFB = 1V 50 nA
I
COMP(SRC)
COMP Output Source Current VFB = 0V
V
COMP
= 0V
200 400 µA
I
COMP(SNK)
COMP Output Sink Current VFB = 1V
V
COMP
= 0.5V
200 350 µA
g
m
Error Amplifier DC Transconductance I
COMP
= -50 µA to +50 µA 400 515 600 µmho
A
VOL
Error Amplifier Voltage Gain COMP pin open 2000 V/V
GBW Error Amplifier Gain-Bandwidth Product COMP pin open 7 MHz
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LM20242
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Symbol Parameter Conditions Min Typ Max Units
Current Limit
I
LIM
Cycle By Cycle Current Limit 3.1 3.7 4.65 A
T
ILIM
Cycle By Cycle Current Limit Delay 150 ns
Enable
V
EN(RISING)
EN Pin Rising Threshold 1.2 1.25 1.3 V
V
EN(HYS)
EN Pin Hysteresis 50 mV
I
EN
EN Source Current VEN = 0V, V
VIN
= 12V 2 µA
Thermal Shutdown
T
SD
Thermal Shutdown 170 °C
T
SD(HYS)
Thermal Shutdown Hysteresis 20 °C
Thermal Resistance
θ
JC
Junction to Case 5.6 °C/W
θ
JA
Junction to Ambient 0 LFM airflow 30 °C/W
Note 1: Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin.
Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Typical Performance Characteristics Unless otherwise specified: T
J
= 25°C, V
VIN
= 12V
Efficiency vs. Load Current
fSW = 350 kHz
30031403
Efficiency vs. Load Current
fSW = 500 kHz
30031404
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LM20242
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Error Amplifier Gain
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Error Amplifier Phase
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Line Regulation
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VCC vs. V
IN
30031408
Non-Switching IQ vs. V
IN
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Shutdown IQ vs. V
IN
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LM20242
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PGOOD VOL vs. I
PGOOD
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EN Threshold and Hysteresis vs. Temperature
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EN Current vs. Temperature
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Oscillator Frequency vs. R
RT
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Oscillator Frequency vs. V
IN
30031454
High-Side FET Resistance vs. Temperature
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Load Transient Response
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Low-Side FET Resistance vs. Temperature
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Peak Current Limit vs. Temperature
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Startup with CSS = 0
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Startup with CSS = 200 nF
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LM20242
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Block Diagram
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LM20242
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Operation Description
GENERAL
The LM20242 switching regulator features all of the functions
necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This
easy to use regulator features two integrated switches and is
capable of supplying up to 2A of continuous output current.
The regulator utilizes peak current mode control with nonlinear slope compensation to optimize stability and transient
response over the entire output voltage range. Peak current
mode control also provides inherent line feed-forward, cycleby-cycle current limiting and easy loop compensation. The
switching frequency can be varied from 100 kHz to 1 MHz with
an external resistor to ground. The device can operate at high
switching frequency allowing use of a small inductor while still
achieving efficiencies as high as 93%. The precision internal
voltage reference allows the output to be set as low as 0.8V.
Fault protection features include: current limiting, thermal
shutdown, over voltage protection, and shutdown capability.
The device is available in the eTSSOP-20 package featuring
an exposed pad to aid thermal dissipation. The typical application circuit for the LM20242 is shown in Figure 2 in the
design guide.
PRECISION ENABLE
The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a
precision analog input that enables the device when the voltage exceeds 1.25V (typical). The EN pin has 50 mV of hysteresis and will disable the output when the enable voltage
falls below 1.2V (typical). If the EN pin is not used, it should
be disconnected so the internal 2 µA pull-up will default this
function to the enabled condition. Since the enable pin has a
precise turn-on threshold it can be used along with an external
resistor divider network from VIN to configure the device to
turn-on at a precise input voltage. The precision enable circuitry will remain active even when the device is disabled.
PEAK CURRENT MODE CONTROL
In most cases, the peak current mode control architecture
used in the LM20242 only requires two external components
to achieve a stable design. The compensation can be selected to accommodate any capacitor type or value. The external
compensation also allows the user to set the crossover frequency and optimize the transient performance of the device.
For duty cycles above 50% all current mode control buck
converters require the addition of an artificial ramp to avoid
sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation. What makes the
LM20242 unique is the amount of slope compensation will
change depending on the output voltage. When operating at
high output voltages the device will have more slope compensation than when operating at lower output voltages. This
is accomplished in the LM20242 by using a non-linear
parabolic ramp for the slope compensation. The parabolic
slope compensation of the LM20242 is much better than the
traditional linear slope compensation because it optimizes the
stability of the device over the entire output voltage range.
CURRENT LIMIT
The precise current limit enables the device to operate with
smaller inductors that have lower saturation currents. When
the peak inductor current reaches the current limit threshold,
an over current event is triggered and the internal high-side
FET turns off and the low-side FET turns on, allowing the inductor current to ramp down until the next switching cycle. For
each sequential over-current event, the reference voltage is
decremented and PWM pulses are skipped resulting in a current limit that does not aggressively fold back for brief overcurrent events, while at the same time providing frequency
and voltage foldback protection during hard short circuit conditions.
SOFT-START AND VOLTAGE TRACKING
The SS/TRK pin is a dual function pin that can be used to set
the startup time or track an external voltage source. The startup or soft-start time can be adjusted by connecting a capacitor
from the SS/TRK pin to ground. The soft-start feature allows
the regulator output to gradually reach the steady state operating point, thus reducing stresses on the input supply and
controlling startup current. If no soft-start capacitor is used the
device defaults to the internal soft-start circuitry resulting in a
startup time of approximately 1 ms. For applications that require a monotonic startup or utilize the PGOOD pin, an external soft-start capacitor is recommended. The SS/TRK pin
can also be set to track an external voltage source. The tracking behavior can be adjusted by two external resistors connected to the SS/TRK pin as shown in Figure 7. in the design
guide.
PRE-BIAS STARTUP CAPABILITY
The LM20242 is in a pre-biased state when it starts up with
an output voltage greater than zero. This often occurs in many
multi-rail applications such as when powering an FPGA,
ASIC, or DSP. In these applications the output can be prebiased through parasitic conduction paths from one supply
rail to another. Even though the LM20242 is a synchronous
converter, it will not pull the output low when a pre-bias condition exists. During start up the LM20242 will not sink current
until the soft-start voltage exceeds the voltage on the FB pin.
Since the device cannot sink current, it protects the load from
damage that might otherwise occur if current is conducted
through the parasitic paths of the load.
POWER GOOD AND OVER VOLTAGE FAULT HANDLING
The LM20242 has built in under and over voltage comparators that control the power switches. Whenever there is an
excursion in output voltage above the set OVP threshold, the
part will terminate the present on-pulse, turn-on the low-side
FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage falls back into regulation
or the zero cross detection is triggered which in turn tri-states
the FETs. If the output reaches the UVP threshold the part will
continue switching and the PGOOD pin will be deasserted
and go low. Typical values for the PGOOD resistor are on the
order of 100 kΩ or less. To avoid false tripping during transient
glitches the PGOOD pin has 20 µs of built in deglitch time to
both rising and falling edges.
UVLO
The LM20242 has an internal under-voltage lockout protection circuit that keeps the device from switching until the input
voltage reaches 3.9V (typical). The UVLO threshold has 200
mV of hysteresis that keeps the device from responding to
power-on glitches during start up. If desired the turn-on point
of the supply can be changed by using the precision enable
pin and a resistor divider network connected to VIN as shown
in Figure 6 in the design guide.
THERMAL PROTECTION
Internal thermal shutdown circuitry is provided to protect the
integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 170°C, the
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LM20242
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LM20242 tri-states the power FETs and resets soft-start. After
the junction cools to approximately 150°C, the part starts up
using the normal start up routine. This feature is provided to
prevent catastrophic failures from accidental device overheating.
LIGHT LOAD OPERATION
The LM20242 offers increased efficiency when operating at
light loads. Whenever the load current is reduced to a point
where the peak to peak inductor ripple current is greater than
two times the load current, the part will enter the diode emulation mode preventing significant negative inductor current.
The point at which this occurs is the critical conduction boundary and can be calculated by the following equation:
Several diagrams are shown in Figure 1 illustrating continuous conduction mode (CCM), discontinuous conduction
mode, and the boundary condition.
It can be seen that in diode emulation mode, whenever the
inductor current reaches zero the SW node will become high
impedance. Ringing will occur on this pin as a result of the LC
tank circuit formed by the inductor and the parasitic capacitance. If this ringing is of concern, an additional RC snubber
circuit can be added from the switch node to ground.
At very light loads, usually below 100 mA, several pulses may
be skipped in between switching cycles, effectively reducing
the switching frequency and further improving light-load efficiency.
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FIGURE 1. Modes of Operation for LM20242
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Design Guide
This section walks the designer through the steps necessary
to select the external components to build a fully functional
power supply. As with any DC-DC converter numerous tradeoffs are possible to optimize the design for efficiency, size, or
performance. These will be taken into account and highlighted throughout this discussion. To facilitate component selection discussions the circuit shown in Figure 2 below may be
used as a reference. Unless otherwise indicated all formulas
assume units of amps (A) for current, farads (F) for capacitance, henries (H) for inductance and volts (V) for voltages.
30031429
FIGURE 2. Typical Application Circuit
The first equation to calculate for any buck converter is dutycycle. Ignoring conduction losses associated with the FETs
and parasitic resistances it can be approximated by:
INDUCTOR SELECTION (L)
The inductor value is determined based on the operating frequency, load current, ripple current and duty cycle.
The inductor selected should have a saturation current rating
greater than the peak current limit of the device. Keep in mind
the specified current limit does not account for delay of the
current limit comparator, therefore the current limit in the application may be higher than the specified value. To optimize
the performance and prevent the device from entering current
limit at maximum load, the inductance is typically selected
such that the ripple current, ΔiL, is not greater than 30% of the
rated output current. Figure 3 illustrates the switch and inductor ripple current waveforms. Once the input voltage, output voltage, operating frequency and desired ripple current
are known, the minimum value for the inductor can be calculated by the formula shown below:
30031467
FIGURE 3. Switch and Inductor Current Waveforms
If needed, slightly smaller value inductors can be used, however, the peak inductor current, I
OUT
+ ΔiL/2, should be kept
below the peak current limit of the device. In general, the inductor ripple current, ΔiL, should be more than 10% of the
rated output current to provide adequate current sense information for the current mode control loop. If the ripple current
in the inductor is too low, the control loop will not have sufficient current sense information and can be prone to instability.
OUTPUT CAPACITOR SELECTION (C
OUT
)
The output capacitor, C
OUT
, filters the inductor ripple current
and provides a source of charge for transient load conditions.
A wide range of output capacitors may be used with the
LM20242 that provide excellent performance. The best performance is typically obtained using ceramic, SP or OSCON
type chemistries. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output
ripple voltage and noise spikes, while the SP and OSCON
capacitors provide a large bulk capacitance in a small volume
for transient loading conditions.
When selecting the value for the output capacitor, the two
performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple
can be approximated by using the following formula.
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LM20242
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Where, ΔV
OUT
(V) is the amount of peak to peak voltage ripple
at the power supply output, R
ESR
(Ω) is the series resistance
of the output capacitor, fSW(Hz) is the switching frequency,
and C
OUT
(F) is the output capacitance used in the design.
The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep
the output ripple less than 1% of the rated output voltage.
Keep in mind ceramic capacitors are sometimes preferred
because they have very low ESR; however, depending on
package and voltage rating of the capacitor the value of the
capacitance can drop significantly with applied voltage. The
output capacitor selection will also affect the output voltage
droop during a load transient. The peak droop on the output
voltage during a load transient is dependent on many factors;
however, an approximation of the transient droop ignoring
loop bandwidth can be obtained using the following equation.
Where, C
OUT
(F) is the minimum required output capacitance,
L (H) is the value of the inductor, V
DROOP
(V) is the output
voltage drop ignoring loop bandwidth considerations, ΔI
OUT-
STEP
(A) is the load step change, R
ESR
(Ω) is the output
capacitor ESR, VIN (V) is the input voltage, and V
OUT
(V) is
the set regulator output voltage. Both the tolerance and voltage coefficient of the capacitor should be examined when
designing for a specific output ripple or transient droop target.
INPUT CAPACITOR SELECTION
Good quality input capacitors are necessary to limit the ripple
voltage at the VIN pin while supplying most of the switch current during the on-time. In general it is recommended to use
a ceramic capacitor for the input as they provide both a low
impedance and small footprint. One important note is to use
a good dielectric for the ceramic capacitor such as X5R or
X7R. These provide better over temperature performance
and also minimize the DC voltage derating that occurs on Y5V
capacitors. The input capacitors should be placed as close as
possible to the VIN and GND pins on both sides of the device.
Non-ceramic input capacitors should be selected for RMS
current rating and minimum ripple voltage. A good approximation for the required ripple current rating is given by the
relationship:
As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle.
For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best
performance, low ESR ceramic capacitors should be placed
in parallel with higher capacitance capacitors to provide the
best input filtering for the device.
SETTING THE OUTPUT VOLTAGE (R
FB1
, R
FB2
)
The resistors R
FB1
and R
FB2
are selected to set the output
voltage for the device. Table 1 provides suggestions for
R
FB1
and R
FB2
for common output voltages.
TABLE 1. Suggested Values for R
FB1
and R
FB2
R
FB1
(kΩ) R
FB2
(kΩ)
V
OUT
short open 0.8
4.99 10 1.2
8.87 10.2 1.5
12.7 10.2 1.8
21.5 10.2 2.5
31.6 10.2 3.3
If different output voltages are required, R
FB2
should be se-
lected to be between 4.99 kΩ to 49.9 kΩ and R
FB1
can be
calculated using the equation below.
ADJUSTING THE OPERATING FREQUENCY (RRT)
The operating frequency of the LM20242 can be adjusted by
connecting a resistor from the RT pin to ground. The equation
shown below can be used to calculate the value of RRT for a
given operating frequency.
Where, fSW is the switching frequency in kHz, and RRT is the
frequency adjust resistor in kΩ. Please refer to the curve Oscillator Frequency versus RRT in the typical performance characteristics section. If the RRT resistor is omitted the device will
not operate.
LOOP COMPENSATION (RC1, CC1)
The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining adequate
stability. Optimal loop compensation depends on the output
capacitor, inductor, load and the device itself.
The overall loop transfer function is the product of the power
stage and the feedback network transfer functions. For stability purposes, the objective is to have a loop gain slope that
is -20db/decade from a very low frequency to beyond the
crossover frequency. Figure 4 shows the transfer functions
for power stage, feedback/compensation network, and the
resulting closed loop system for the LM20242.
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30031472
FIGURE 4. LM20242 Loop Compensation
The power stage transfer function is dictated by the modulator, output LC filter, and load; while the feedback transfer
function is set by the feedback resistor ratio, error amp gain
and external compensation network.
To achieve a -20dB/decade slope, the error amplifier zero,
located at f
Z(EA)
, should be positioned to cancel the output fil-
ter pole (f
P(FIL)
). An additional error amp pole, located at f
P2
(EA)
, can be added to cancel the output filter zero at f
Z(FIL)
.
Cancellation of the output filter zero is recommended if larger
value, non-ceramic output capacitors are used.
Compensation of the LM20242 is achieved by adding an RC
network as shown in Figure 5 below.
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FIGURE 5. Compensation Network for LM20242
A good starting value for CC1 for most applications is 4.7 nF.
Once the value of CC1 is chosen the value of RC should be
calculated using the equation below to cancel the output filter
pole (f
P(FIL)
) as shown in Figure 4.
A higher crossover frequency can be obtained, usually at the
expense of phase margin, by lowering the value of CC1 and
recalculating the value of RC1. Likewise, increasing CC1 and
recalculating RC1 will provide additional phase margin at a
lower crossover frequency. As with any attempt to compensate the LM20242 the stability of the system should be verified
for desired transient droop and settling time.
If the output filter zero, f
Z(FIL)
approaches the crossover frequency (FC), an additional capacitor (CC2) should be placed
at the COMP pin to ground. This capacitor adds a pole to
cancel the output filter zero assuring the crossover frequency
will occur before the double pole at fSW/2 degrades the phase
margin. The output filter zero is set by the output capacitor
value and ESR as shown in the equation below.
If needed, the value for CC2 should be calculated using the
equation shown below.
Where R
ESR
is the output capacitor series resistance and
RC1 is the calculated compensation resistance.
BOOT CAPACITOR (C
BOOT
)
The LM20242 integrates an N-Channel buck switch and associated floating high voltage level shift / gate driver. This gate
driver circuit works in conjunction with an internal diode and
an external bootstrap capacitor. A 0.1 µF ceramic capacitor,
connected with short traces between the BOOT pin and SW
pin, is recommended. During the off-time of the buck switch,
the SW pin voltage is approximately 0V and the bootstrap capacitor is charged from VCC through the internal bootstrap
diode.
SUB-REGULATOR BYPASS CAPACITOR (C
VCC
)
The capacitor at the VCC pin provides noise filtering for the
internal sub-regulator. The recommended value of C
VCC
should be no smaller than 0.1 µF and no greater than 1 µF.
The capacitor should be a good quality ceramic X5R or X7R
capacitor. In general, a 1 µF ceramic capacitor is recommended for most applications. The VCC regulator should not
be used for other functions since it isn't protected against
short circuit.
SETTING THE START UP TIME (CSS)
The addition of a capacitor connected from the SS pin to
ground sets the time at which the output voltage will reach the
final regulated value. Larger values for CSS will result in longer
start up times. Table 3, shown below provides a list of soft
start capacitors and the corresponding typical start up times.
TABLE 2. Start Up Times for Different Soft-Start
Capacitors
Start Up Time (ms) CSS (nF)
1 none
5 33
10 68
15 100
20 120
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Page 14
If different start up times are needed the equation shown below can be used to calculate the start up time.
As shown above, the start up time is influenced by the value
of the soft-start capacitor CSS(F) and the 5 µA soft-start pin
current ISS(A). that may be found in the electrical characteristics table.
While the soft-start capacitor can be sized to meet many start
up requirements, there are limitations to its size. The soft-start
time can never be faster than 1 ms due to the internal default
1 ms start up time. When the device is enabled there is an
approximate time interval of 50 µs when the soft-start capacitor will be discharged just prior to the soft-start ramp. If the
enable pin is rapidly pulsed or the soft-start capacitor is large
there may not be enough time for CSS to completely discharge
resulting in start up times less than predicted. To aid in discharging of soft-start capacitor during long disable periods an
external 1MΩ resistor from SS/TRK to ground can be used
without greatly affecting the start up time.
USING PRECISION ENABLE AND POWER GOOD
The precision enable (EN) and power good (PGOOD) pins of
the LM20242 can be used to address many sequencing requirements. The turn-on of the LM20242 can be controlled
with the precision enable pin by using two external resistors
as shown in Figure 6 .
30031462
FIGURE 6. Sequencing LM20242 with Precision Enable
The value for resistor RB can be selected by the user to control
the current through the divider. Typically this resistor will be
selected to be between 10 kΩ and 1 MΩ. Once the value for
RB is chosen the resistor RA can be solved using the equation
below to set the desired turn-on voltage.
When designing for a specific turn-on threshold (VTO) the tolerance on the input supply, enable threshold (V
IH_EN
), and
external resistors need to be considered to insure proper turnon of the device.
The LM20242 features an open drain power good (PGOOD)
pin to sequence external supplies or loads and to provide fault
detection. This pin requires an external resistor (RPG) to pull
PGOOD high when the output is within the PGOOD tolerance
window. Typical values for this resistor range from 10 kΩ to
100 kΩ.
TRACKING AN EXTERNAL SUPPLY
By using a properly chosen resistor divider network connected to the SS/TRK pin, as shown in Figure 7, the output of the
LM20242 can be configured to track an external voltage
source to obtain a simultaneous or ratiometric start up.
30031461
FIGURE 7. Tracking an External Supply
Since the soft-start charging current ISS is always present on
the SS/TRK pin, the size of R2 should be less than 10 kΩ to
minimize the errors in the tracking output. Once a value for
R2 is selected the value for R1 can be calculated using appropriate equation in Figure 8, to give the desired start up.
Figure 8 shows two common start up sequences; the top
waveform shows a simultaneous start up while the waveform
at the bottom illustrates a ratiometric start up.
30031478
FIGURE 8. Common Start Up Sequences
A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these systems the
higher voltage, V
OUT1
, usually powers the I/O, and the lower
voltage, V
OUT2
, powers the core. A simultaneous start up provides a more robust power up for these applications since it
avoids turning on any parasitic conduction paths that may exist between the core and the I/O pins of the processor.
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LM20242
Page 15
The second most common power on behavior is known as a
ratiometric start up. This start up is preferred in applications
where both supplies need to be at the final value at the same
time.
Similar to the soft-start function, the fastest start up possible
is 1ms regardless of the rise time of the tracking voltage.
When using the track feature the final voltage seen by the SS/
TRACK pin should exceed 1V to provide sufficient overdrive
and transient immunity.
BENEFIT OF AN EXTERNAL SCHOTTKY
During dead time, the body diode of the synchronous MOSFET acts as a free-wheeling diode and conducts the inductor
current. The MOSFET is optimized for high breakdown voltage, but this makes an inefficient body diode reverse recovery
charge. The power loss is proportional to load current and
switching frequency. The loss increases at higher input voltages and switching frequencies. One simple solution is to use
a small 1A external Schottky diode between SW and GND as
shown in Figure 10, diodes D1 and D2. The external Schottky
diode effectively conducts all inductor current during the dead
time, minimizing the current passing through the synchronous
MOSFET body diode and eliminating reverse recovery losses.
The external Schottky conducts currents for a very small portion of the switching cycle, therefore the average current is
low. An external Schottky rated for 1A will improve efficiency
by several percent in some applications. A Schottky rated at
a higher current will not significantly improve efficiency and
may be worse due to the increased reverse capacitance. The
forward voltage of the synchronous MOSFET body diode is
approximately 700 mV, therefore an external Schottky with a
forward voltage less than or equal to 700 mV should be selected to ensure the majority of the dead time current is carried
by the Schottky.
THERMAL CONSIDERATIONS
The thermal characteristics of the LM20242 are specified using the parameter θJA, which relates the junction temperature
to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be used to approximate
the operating junction temperature of the device.
To obtain an estimate of the device junction temperature, one
may use the following relationship:
TJ = PD x θJA + T
A
and
PD = PIN x (1 - Efficiency) - 1.1 x (I
OUT
)2 x DCR
Where:
TJ is the junction temperature in °C.
PIN is the input power in Watts (PIN = VIN x IIN).
θJA is the junction to ambient thermal resistance for the
LM20242.
TA is the ambient temperature in °C.
I
OUT
is the output load current.
DCR is the inductor series resistance.
It is important to always keep the operating junction temper-
ature (TJ) below 125°C for reliable operation. If the junction
temperature exceeds 160°C the device will cycle in and out
of thermal shutdown. If thermal shutdown occurs it is a sign
of inadequate heatsinking or excessive power dissipation in
the device.
PCB LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI,
ground bounce, and resistive voltage loss in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability.
Good layout can be implemented by following a few simple
design rules.
1. Minimize area of switched current loops. In a buck regulator
there are two loops where currents are switched very fast. The
first loop starts from the input capacitor, to the regulator VIN
pin, to the regulator SW pin, to the inductor then out to the
output capacitor and load. The second loop starts from the
output capacitor ground, to the regulator GND pins, to the inductor and then out to the load (see Figure 9). To minimize
both loop areas the input capacitor should be placed as close
as possible to the VIN pin. Grounding for both the input and
output capacitor should consist of a small localized top side
plane that connects to GND and the exposed pad (EP). The
inductor should be placed as close as possible to the SW pin
and output capacitor.
2. Minimize the copper area of the switch node. Since the
LM20242 has the SW pins on opposite sides of the package
it is recommended that the SW pins should be connected with
a trace that runs around the package. The inductor should be
placed at an equal distance from the SW pins using 100 mil
wide traces to minimize capacitive and conductive losses.
3. Have a single point ground for all device grounds located
under the EP. The ground connections for the compensation,
feedback, and soft-start components should be connected
together then routed to the EP pin of the device. The AGND
pin should connect to GND under the EP. If not properly handled poor grounding can result in degraded load regulation or
erratic switching behavior.
4. Minimize trace length to the FB pin. Since the feedback
node can be high impedance the trace from the output resistor
divider to FB pin should be as short as possible. This is most
important when high value resistors are used to set the output
voltage. The feedback trace should be routed away from the
SW pin and inductor to avoid contaminating the feedback signal with switch noise.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of
the converter and can improve efficiency. Voltage accuracy
at the load is important so make sure feedback voltage sense
is made at the load. Doing so will correct for voltage drops at
the load and provide the best output accuracy.
6. Provide adequate device heatsinking. Use as many vias as
is possible to connect the EP to the power plane heatsink. For
best results use a 5x3 via array with a minimum via diameter
of 12 mils. "Via tenting" with the solder mask may be necessary to prevent wicking of the solder paste applied to the EP.
See the Thermal Considerations section to insure enough
copper heatsinking area is used to keep the junction temperature below 125°C.
15 www.national.com
LM20242
Page 16
30031446
FIGURE 9. Schematic of LM20242 Highlighting Layout Sensitive Nodes
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LM20242
Page 17
30031444
FIGURE 10. Typical Application Schematic
Bill of Materials
ID Qty Part Number Size Description Vendor
U1 1 LM20242MH eTSSOP-20 IC, Switching Regulator NSC
L1 1 MSS1260-153MX MSS1260 15 µH, 4.6A ISAT Coilcraft
C1-3 3 GRM32ER71H475KA88L 1210 4.7 µF, 50V, X7R Murata
C4, 6, 9 3 VJ0805JY104KXX 0805 0.1 µF Vishay
C5, 11 2 VJ0805Y105JXACW1BC 0805 1 µF Vishay
C7 1 C1608COG1H121J 0603 120 pF TDK
C8 1 VJ0805Y222J 0805 2.2 nF Vishay
C10 1 C1210C107M9PAC 1210 100 µF Kemet
D1, D2 2 MBR0540 SOD123 0.5A, 40V, Schottky Fairchild
R1,9 2 CRCW06031002F 0603
10 kΩ
Vishay
R2 1 CRCW08052053F 0805
205 kΩ
Vishay
R3 1 CRCW08051212F 0805
12.1 kΩ
Vishay
R4, 7 2 CRCW060330000ZOEA 0603
0 kΩ
Vishay
R5 1 CRCW08053212F 0805
32.1 kΩ
Vishay
R6 1 CRCW08051022F 0805
10.2 kΩ
Vishay
R8 1 CRCW08054992F 0603
49.9 kΩ
Vishay
17 www.national.com
LM20242
Page 18
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead eTSSOP Package
NS Package Number MXA20A
www.national.com 18
LM20242
Page 19
Notes
19 www.national.com
LM20242
Page 20
Notes
LM20242 36V, 2A PowerWise
®
Adjustable Frequency Synchronous Buck Regulator
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