Datasheet LIS302DL Datasheet (ST)

Download

Page 1

3-axis - ± 2g/± 8g smart digital output “piccolo” accelerometer

Feature

■ 2.16 V to 3.6 V supply voltage

■ 1.8 V compatible IOs

■ <1 mW power consumption

■ ± 2g/± 8g dynamically selectable full-scale

■ I

C/SPI digital output interface

■ Programmable multiple interrupt generator

■ Click and double click recognition

■ Embedded high pass filter

■ Embedded self test

■ 10000g high shock survivability

■ ECOPACK® RoHS and “Green” compliant

(see Section 9)

Description

The LIS302DL is an ultra compact low-power three axes linear accelerometer. It includes a sensing element and an IC interface able to provide the measured acceleration to the external world through I

The sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by ST to produce inertial sensors and actuators in silicon.

The IC interface is manufactured using a CMOS process that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics.

C/SPI serial interface.

LIS302DL

MEMS motion sensor

LGA 14

The LIS302DL has dynamically user selectable full scales of ± 2g/± 8g and it is capable of measuring accelerations with an output data rate of 100 Hz or 400 Hz.

A self-test capability allows the user to check the functioning of the sensor in the final application.

The device may be configured to generate inertial wake-up/free-fall interrupt signals when a programmable acceleration threshold is crossed at least in one of the three axes. Thresholds and timing of interrupt generators are programmable by the end user on the fly.

The LIS302DL is available in plastic Thin Land Grid Array package (TLGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.

The LIS302DL belongs to a family of products suitable for a variety of applications:

– Free-fall detection – Motion activated functions – Gaming and virtual reality input devices – Vibration monitoring and compensation

(3x5x0.9mm)

Table 1. Device summary

Part number Temp range, ° CPackage Packing

LIS302DL -40 to +85 LGA Tray

LIS302DLTR -40 to +85 LGA Tape and reel ( 5000 pcs/reel )

LIS302DLTR8 -40 to +85 LGA Tape and reel ( 8000 pcs/reel )

October 2008 Rev 4 1/42

www.st.com

Page 2

Contents LIS302DL

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.2 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.3 Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.4 Click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2.1 SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2.2 SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2.3 SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/42

Page 3

LIS302DL Contents

6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.2 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.3 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.4 CTRL_REG3 [Interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 28

7.5 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.6 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.7 OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.8 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.9 OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.10 FF_WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.11 FF_WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.12 FF_WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.13 FF_WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.14 FF_WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.15 FF_WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.16 FF_WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.17 FF_WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.18 CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.19 CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.20 CLICK_THSY_X (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.21 CLICK_THSZ (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.22 CLICK_TimeLimit (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.23 CLICK_Latency (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.24 CLICK_Window (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1 Mechanical characteristics at 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.2 Mechanical characteristics derived from measurement in the -40°C to +85°C

temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.3 Electro-mechanical characteristics at 25°C . . . . . . . . . . . . . . . . . . . . . . . 39

3/42

Page 4

Contents LIS302DL

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4/42

Page 5

LIS302DL List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Mechanical characteristics

(All the parameters are specified @ Vdd=2.5V, T = 25°C unless otherwise noted) . . . . . . 10

Table 4. Electrical characteristics

(All the parameters are specified @ Vdd=2.5V, T= 25°C unless otherwise noted) . . . . . . 11

Table 5. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 12. Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 13. Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 20

Table 14. ransfer when master is receiving (reading). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 15. Multiple bytes of data from slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 16. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17. WHO_AM_I (0Fh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18. CTRL_REG1 (20h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 19. CTRL_REG1 (20h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 20. CTRL_REG2 (21h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 21. CTRL_REG2 (21h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 22. High pass filter cut-off frequency configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 23. CTRL_REG3 (22h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 24. CTRL_REG3 (22h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 25. CTRL_REG3 (22h) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 26. STATUS_REG (27h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 27. STATUS_REG (27h) register desription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 28. OUT_X (29h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 29. OUT_Y (2Bh) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 30. OUT_Z (2Dh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 31. FF_WW_CFG_1 (30h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 32. FF_WW_CFG_1(30h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 33. FF_WU_SRC_1 (31h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 34. FF_WU_SRC_1 (31h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 35. FF_WU_THS_1 (32h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 36. FF_WU_THS_1 (32h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 37. FF_WU_DURATION_1 (33h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 38. FF_WU_DURATION_1 (33h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 39. FF_WU_CFG_2 (34h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 40. FF_WU_CFG_2 (34h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 41. FF_WU_SRC_2 (35h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 42. FF_WU_SRC_2 (35h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 43. FF_WU_THS_2 (36h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 44. FF_WU_THS_2 (36h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 45. FF_WU_DURATION_2 (37h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 46. FF_WU_DURATION_2 (37h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5/42

Page 6

List of tables LIS302DL

Table 47. CLICK_CFG (38h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 48. CLICK_CFG (38h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 49. CLICK_CFG (38h) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 50. CLICK_SRC (39h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 51. CLICK_SRC (39h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 52. CLICK_THSY_X (3Bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 53. CLICK_THSY_X (3Bh) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 54. CLICK_THSZ (3Ch) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 55. CLICK_THSZ (3Ch) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 56. CLICK_TimeLimit (3Dh) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 57. CLICK_Latency (3Eh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 58. CLICK_Window (3Fh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 59. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6/42

Page 7

LIS302DL List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. I2C Slave timing diagram (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. LIS302DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. SPI Read protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8. Multiple bytes SPI Read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. SPI Write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 10. Multiple bytes SPI Write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11. SPI Read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. X axis zero-g level at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. X axis sensitivity at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 14. Y axis zero-g level at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 15. Y axis sensitivity at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 16. Z axis zero-g level at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 17. Z axis sensitivity at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 18. X axis zero-g level change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 19. X axis sensitivity change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 20. Y axis zero-g level change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 21. Y axis sensitivity change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 22. Z axis zero-g level change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 23. Z axis sensitivity change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 24. Current consumption in normal mode at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 25. Current consumption in power down mode at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 26. LGA 14: mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7/42

Page 8

Block diagram and pin description LIS302DL

1 Block diagram and pin description

1.1 Block diagram

Figure 1. Block diagram

X+

Y+

Z+

MUX

Z-

Y-

X-

CHARGE AMPLIFIER

A/D

CONVERTER

CONTROL LOGIC

I2C

SPI

SCL/SPC

SDA/SDO/SDI

SDO

REFERENCESELF TEST

1.2 Pin description

Figure 2. Pin connection

TOP VIEW

TRIMMING

CIRCUITS

CLOCK

CONTROL LOGIC

INTERRUPT GEN.

INT 1

INT 2

13 8

BOTTOM VIEW

8/42

Page 9

LIS302DL Block diagram and pin description

Table 2. Pin description

Pin# Name Function

1 Vdd_IO Power supply for I/O pins

2 GND 0V supply

3 Reserved Connect to Vdd

4 GND 0V supply

5 GND 0V supply

6 Vdd Power supply

7CS

SPI enable

C/SPI mode selection (1: I2C mode; 0: SPI enabled)

8 INT 1 Inertial interrupt 1

9 INT 2 Inertial interrupt 2

10 GND 0V supply

11 Reserved Connect to Gnd

12 SDO

SDA

SDI

SDO

SCL SPC

SPI Serial Data Output

C less significant bit of the device address

C Serial Data (SDA)

I SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO)

C Serial Clock (SCL)

I SPI Serial Port Clock (SPC)

9/42

Page 10

Mechanical and electrical specifications LIS302DL

2 Mechanical and electrical specifications

2.1 Mechanical characteristics

Table 3. Mechanical characteristics

(1)

(All the parameters are specified @ Vdd=2.5 V, T = 25°C unless otherwise noted)

Symbol Parameter Test conditions Min. Typ.

FS Measurement range

So Sensitivity

(3)

FS bit set to 0 ±2.0 ±2.3

FS bit set to 1 ±8.0 ±9.2

FS bit set to 0 16.2 18 19.8

FS bit set to 1 64.8 72 79.2

TCSO

Ty Of f

TCOff

Sensitivity change vs temperature

Typical zero-g level offset accuracy

(4),(5)

Zero-g level change vs temperature

FS bit set to 0 ±0.01 %/°C

FS bit set to 0 ±40 mg

FS bit set to 1 ±60 mg

Max delta from 25°C

FS bit set to 0 STP bit used

-32 -3 LSb

X axis

FS bit set to 0 STP bit used Y axis

332LSb

Vst

Self test output

(6),(7),(8),(9)

change

FS bit set to 0 STP bit used

332LSb

Z axis

BW System bandwidth

(10)

Top Operating temperature range -40 +85 °C

Wh Product weight 30 mgram

1. The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V

2. Typical specifications are not guaranteed

3. Verified by wafer level test and measurement of initial offset and sensitivity

4. Typical zero-g level offset value after MSL3 preconditioning

5. Offset can be eliminated by enabling the built-in high pass filter

6. If STM bit is used values change in sign for all axes

7. Self Test output changes with the power supply. Vst at 3.3V is typically in the range [-74; -7] LSb for X axis and [7;74] LSb for Y

and Z axes.

“Self Test Output Change” is defined as OUTPUT[LSb] 1LSb=4.6g/256 at 8bit representation, ±2.3g Full-Scale

9. Output data reach 99% of final value after 3/ODR when enabling Self-Test mode due to device filtering

10. ODR is output data rate. Refer to Table 4 for specifications

(Self-test bit on ctrl_reg1=1)

-OUTPUT[LSb]

(2)

Max. Unit

±0.5 mg/°C

ODR/2 Hz

(Self-test bit on ctrl_reg1=0)

mg/digit

10/42

Page 11

LIS302DL Mechanical and electrical specifications

2.2 Electrical characteristics

Table 4. Electrical characteristics

(1)

(All the parameters are specified @ Vdd=2.5 V, T= 25°C unless otherwise noted)

Symbol Parameter Test conditions Min. Typ.

Vdd Supply voltage 2.16 2.5 3.6 V

Vdd_IO I/O pins supply voltage

(3)

1.71 Vdd+0.1 V

Idd Supply current T = 25°C, ODR=100Hz 0.3 0.4 mA

IddPdn

VIH

Current consumption in power-down mode

Digital high level input voltage

T = 25°C 1 5 µA

0.8*Vdd _IO

VIL Digital low level input voltage

VOH High level output voltage

0.9*Vdd _IO

VOL Low level output voltage

DR=0 100

ODR Output data rate

DR=1 400

BW System bandwidth

Ton Turn-on time

(4)

(5)

Top Operating temperature range -40 +85

1. The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V

2. Typical specification are not guaranteed

3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off.

4. Filter cut-off frequency

5. Time to obtain valid data after exiting Power-Down mode

(2)

Max. Unit

0.2*Vdd _IO

0.1*Vdd _IO

ODR/2 Hz

3/ODR s

°C

11/42

Page 12

Mechanical and electrical specifications LIS302DL

2.3 Communication interface characteristics

2.3.1 SPI - Serial Peripheral Interface

Subject to general operating conditions for Vdd and Top.

Table 5. SPI slave timing values

(1)

Val ue

Symbol Parameter

Min. Max.

tc(SPC) SPI clock cycle 100 ns

fc(SPC) SPI clock frequency 10 MHz

tsu(CS) CS setup time 5

th(CS) CS hold time 8

tsu(SI) SDI input setup time 5

Unit

th(SI) SDI input hold time 15

tv(SO) SDO valid output time 50

th(SO) SDO output hold time 6

tdis(SO) SDO output disable time 50

(2)

c(SPC)

h(SO)

SPC

SDI

SDO

Figure 3. SPI slave timing diagram

(3)

su(CS)

(3)

h(SI)

MSB OUT

(3)

su(SI)

MSB IN

v(SO)

h(CS)

LSB IN

LSB OUT

(3)

dis(SO)

(3)

1. Values are guaranteed at 10MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production

2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port

3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors

12/42

Page 13

LIS302DL Mechanical and electrical specifications

2.3.2 I2C - inter IC control interface

Subject to general operating conditions for Vdd and Top.

Table 6. I

C slave timing values

Symbol Parameter

(SCL)

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA) tr(SCL)

f(SDA) tf(SCL)

h(ST)

su(SR)

su(SP)

w(SP:SR)

SCL clock frequency 0 100 0 400 KHz

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100 ns

SDA data hold time 0

SDA and SCL rise time 1000

SDA and SCL fall time 300

START condition hold time 4 0.6

Repeated START condition setup time

STOP condition setup time 4 0.6

Bus free time between STOP and START condition

I2C standard mode

(1)

I2C fast mode

Min Max Min Max

3.45

(2)

20 + 0.1C

(3)

4.7 0.6

4.7 1.3

(1)

0.9

300

(2)

Unit

µs

SDA

Figure 4. I

f(SDA)

START

C Slave timing diagram

r(SDA)

su(SDA)

(4)

h(SDA)

su(SR)

su(SP)

w(SP:SR)

REPEATED

START

STOP

SCL

h(ST)

1. Data based on standard I

2. A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL

3. Cb = total capacitance of one bus line, in pF

4. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port

w(SCLL)

C protocol requirement, not tested in production

w(SCLH)

r(SCL)

f(SCL)

13/42

Page 14

Mechanical and electrical specifications LIS302DL

2.4 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 7. Absolute maximum ratings

Symbol Ratings Maximum value Unit

Vdd Supply voltage -0.3 to 6 V

Vdd_IO I/O pins supply voltage -0.3 to 6 V

Vin

POW

UNP

STG

ESD Electrostatic discharge protection

Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO)

Acceleration (any axis, powered, Vdd=2.5V)

Acceleration (any axis, unpowered)

Operating temperature range -40 to +85 °C

Storage temperature range -40 to +125 °C

-0.3 to Vdd_IO +0.3 V

3000g for 0.5 ms

10000g for 0.1 ms

3000g for 0.5 ms

10000g for 0.1 ms

4 (HBM) kV

1.5 (CDM) kV

200 (MM) V

Note: Supply voltage on any pin should never exceed 6.0V

This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part

This is an ESD sensitive device, improper handling can cause permanent damages to the part

2.5 Terminology

2.5.1 Sensitivity

Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so, ±1g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. This value changes very little over temperature and also very little over time. The Sensitivity Tolerance describes the range of Sensitivities of a large population of sensor.

14/42

Page 15

LIS302DL Mechanical and electrical specifications

2.5.2 Zero-g level

Zero-g level Offset (Off) describes the deviation of an actual output signal from the ideal output signal if there is no acceleration present. A sensor in a steady state on a horizontal surface will measure 0g in X axis and 0g in Y axis whereas the Z axis will measure 1g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to a precise MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature”. The Zero-g level of an individual sensor is stable over lifetime. The Zero-g level tolerance describes the range of Zero-g levels of a population of sensors.

2.5.3 Self test

Self Test allows to check the sensor functionality without moving it. The Self Test function is off when the self-test bit of CTRL_REG1 (control register 1) is programmed to ‘0‘. When the self-test bit of ctrl_reg1 is programmed to ‘1‘ an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which is related to the selected full scale through the device sensitivity. When Self Test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3, than the sensor is working properly and the parameters of the interface chip are within the defined specification.

2.5.4 Click and double click recognition

The Click and Double Click recognition functions help to create man-machine interface with little software overload. The device can be configured to output an interrupt signal on dedicated pin when tapped in any direction.

If the sensor is exposed to a single input stimulus it generates an interrupt request on inertial interrupt pin (INT1 and/or INT2). A more advanced feature allows to generate and interrupt request when a “double click” with programmable time between the two events enabling a “mouse button like” use.

This function can be fully programmed by the user in terms of expected amplitude and timing of the stimuli.

15/42

Page 16

Functionality LIS302DL

3 Functionality

The LIS302DL is a ultracompact, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I

3.1 Sensing element

A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation.

When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor.

At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in fF range.

C/SPI serial interface.

3.2 IC interface

The complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by analog-to-digital converters.

The acceleration data may be accessed through an I device particularly suitable for direct interfacing with a microcontroller.

The LIS302DL features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device.

The LIS302DL may also be configured to generate an inertial Wake-Up and Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both Free-Fall and Wake-Up can be available simultaneously on two different pins.

3.3 Factory calibration

The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off).

The trimming values are stored inside the device by a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the normal operation. This allows the user to use the device without further calibration.

C/SPI interface thus making the

16/42

Page 17

LIS302DL Application hints

4 Application hints

Figure 5. LIS302DL electrical connection

Vdd

10uF

100nF

GND

Top VIEW

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

INT 1

INT 2

SDO

Vdd_IO

SDA/SDI/SDO

SCL/SPC

TOP VIEW

DIRECTIONS OF THE DETECTABLE ACCELERATIONS

The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be placed as near as possible to the pin 6 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off.

The functionality of the device and the measured acceleration data is selectable and accessible through the I

C/SPI interface.When using the I2C, CS must be tied high.

The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user though the I

4.1 Soldering information

The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C.

Leave “Pin 1 Indicator” unconnected during soldering.

Land pattern and soldering recommendation are available at www.st.com/mems

C/SPI interface.

17/42

Page 18

Digital interfaces LIS302DL

5 Digital interfaces

The registers embedded inside the LIS302DL may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.

The serial interfaces are mapped onto the same pads. To select/exploit the I line must be tied high (i.e connected to Vdd_IO).

Table 8. Serial interface pin description

PIN name PIN description

C interface, CS

SCL/SPC

SDA/SDI/SDO

SDO SPI Serial Data Output (SDO)

SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)

C Serial Clock (SCL)

I SPI Serial Port Clock (SPC)

C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO)

5.1 I2C Serial Interface

The LIS302DL I2C is a bus slave. The I2C is employed to write the data into the registers whose content can also be read back.

The relevant I

Table 9. Serial interface pin description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus

Master

C terminology is given in the table below.

Term Description

The device which initiates a transfer, generates clock signals and terminates a transfer

Slave The device addressed by the master

There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS302DL. When the bus is free both the lines are high.

The I

C interface is compliant with Fast Mode (400 kHz) I2C standards as well as the

Normal Mode.

18/42

Page 19

LIS302DL Digital interfaces

5.1.1 I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master.

The Slave ADdress (SAD) associated to the LIS302DL is 001110xb. SDO pad can be used to modify less significant bit of the device address. If SDO pad is connected to voltage supply LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’ (address 0011100b). This solution permits to connect and address two different accelerometer to the same I

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received.

The I

C embedded inside the LIS302DL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a salve address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write.

C lines.

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the Master will transmit to the slave with direction unchanged. Table 10 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Table 10. SAD+Read/Write patterns

Command SAD[6:1] SAD[0] = SDO R/W SAD+R/W

Read 001110 0 1 00111001 (39h)

Write 001110 0 0 00111000 (38h)

Read 001110 1 1 00111011 (3Bh)

Write 001110 1 0 00111010 (3Ah)

Table 11. Transfer when master is writing one byte to slave

Master ST SAD + W SUB DATA SP

Slave SAK SAK SAK

Table 12. Transfer when master is writing multiple bytes to slave

Master ST SAD + W SUB DATA DATA SP

Slave SAK SAK SAK SAK

19/42

Page 20

Digital interfaces LIS302DL

Table 13. Transfer when Master is receiving (reading) one byte of data from slave

Master ST SAD + W SUB SR SAD + R NMAK SP

Slave SAK SAK SAK DATA

Table 14. ransfer when master is receiving (reading)

Master ST SAD + W SUB SR SAD + R MAK

Slave SAK SAK SAK DATA

Table 15. Multiple bytes of data from slave

Master MAK NMAK SP

Slave DATA DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to read.

In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge.

5.2 SPI bus interface

The LIS302DL SPI is a bus slave. The SPI allows to write and read the registers of the device.

The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.

20/42

Page 21

LIS302DL Digital interfaces

Figure 6. Read & write protocol

SPC

SDI

DI7DI6DI5DI4DI3DI2DI1DI0

DO7DO6DO5DO4DO3DO2DO1DO0

SDO

AD5 AD4 AD3 AD2 AD1 AD0

CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC.

Both the Read Register and Write Register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS.

bit 0: RW

bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)

from the device is read. In latter case, the chip will drive SDO at the start of bit 8.

bit 1: MS

bit. When 0, the address will remain unchanged in multiple read/write commands.

When 1, the address will be auto incremented in multiple read/write commands.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb

first).

bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).

In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS

bit

is 1 the address used to read/write data is incremented at every block.

The function and the behavior of SDI and SDO remain unchanged.

21/42

Page 22

Digital interfaces LIS302DL

5.2.1 SPI Read

Figure 7. SPI Read protocol

SPC

SDI

AD5 AD4 AD3 AD2 AD1 AD0

SDO

DO7 DO6 DO5DO4 DO3 DO2 DO1DO0

The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one.

bit 0: READ bit. The value is 1.

bit 1: MS

bit. When 0 do not increment address, when 1 increment address in multiple

reading.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb

first).

bit 16-... : data DO(...-8). Further data in multiple byte reading.

Figure 8. Multiple bytes SPI Read protocol (2 bytes example)

SPC

SDI

SDO

5.2.2 SPI Write

Figure 9. SPI Write protocol

AD5 AD4 AD3 AD2 AD1 AD0

DO7DO6DO5DO4DO3DO2DO1DO0

DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8

SPC

SDI

AD5 AD4 AD3 AD2 AD1 AD0MS

22/42

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

Page 23

LIS302DL Digital interfaces

The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one.

bit 0: WRITE bit. The value is 0.

bit 1: MS

bit. When 0 do not increment address, when 1 increment address in multiple

writing.

bit 2 -7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device

(MSb first).

bit 16-... : data DI(...-8). Further data in multiple byte writing.

Figure 10. Multiple bytes SPI Write protocol (2 bytes example)

SPC

SDI

AD5 AD4 AD3 AD2 AD1 AD0

5.2.3 SPI Read in 3-wires mode

3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2.

DI7 DI6 DI5 DI4 DI3 DI2 D I1 DI0 D I15 DI14 DI13 DI12 DI11 DI10 DI9 DI8

Figure 11. SPI Read protocol in 3-wires mode

SPC

SDI/O

AD5 AD4 AD3 AD2 AD1 AD0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

The SPI Read command is performed with 16 clock pulses:

bit 0: READ bit. The value is 1.

bit 1: MS

bit. When 0 do not increment address, when 1 increment address in multiple

reading.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb

first).

Multiple read command is also available in 3-wires mode.

23/42

Page 24

6 Register mapping

The table given below provides a listing of the 8 bit registers embedded in the device and the related address:

Table 16. Register address map

Name Type

Hex Binary

Reserved (Do not modify) 00-0E Reserved

Who_Am_I r 0F 000 1111 00111011 Dummy register

Reserved (Do not modify) 10-1F Reserved

Ctrl_Reg1 rw 20 010 0000 00000111

Ctrl_Reg2 rw 21 010 0001 00000000

Ctrl_Reg3 rw 22 010 0010 00000000

HP_filter_reset r 23 010 0011 dummy Dummy register

Reserved (Do not modify) 24-26 Reserved

Status_Reg r 27 010 0111 00000000

Default Comment

-- r 28 010 1000 Not Used

OutX r 29 010 1001 output

-- r 2A 010 1010 Not Used

OutY r 2B 010 1011 output

-- r 2C 010 1100 Not Used

OutZ r 2D 010 1101 output

Reserved (Do not modify) 2E-2F Reserved

FF_WU_CFG_1 rw 30 011 0000 00000000

FF_WU_SRC_1(ack1) r 31 011 0001 00000000

FF_WU_THS_1 rw 32 011 0010 0000000x

FF_WU_DURATION_1 rw 33 011 0011 00000000

FF_WU_CFG_2 rw 34 011 0100 00000000

FF_WU_SRC_2 (ack2) r 35 011 0101 00000000

FF_WU_THS_2 rw 36 011 0110 00000000

FF_WU_DURATION_2 rw 37 011 0111 00000000

CLICK_CFG rw 38 011 1000 00000000

CLICK_SRC (ack) r 39 011 1001 00000000

-- 3A Not Used

CLICK_THSY_X rw 3B 011 1011 00000000

24/42

Page 25

LIS302DL Register mapping

Table 16. Register address map (continued)

Name Type

Hex Binary

CLICK_THSZ rw 3C 011 1100 00000000

CLICK_TimeLimit rw 3D 011 1101 00000000

CLICK_Latency rw 3E 011 1110 00000000

CLICK_Window rw 3F 011 1111 00000000

Default Comment

Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device.

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up.

25/42

Page 26

7 Register description

The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface.

7.1 WHO_AM_I (0Fh)

Table 17. WHO_AM_I (0Fh) register

00111011

Device identification register. This register contains the device identifier that for LIS302DL is set to 3Bh.

7.2 CTRL_REG1 (20h)

Table 18. CTRL_REG1 (20h) register

DR PD FS STP STM Zen Yen Xen

Table 19. CTRL_REG1 (20h) register description

DR Data rate selection. Default value: 0

(0: 100 Hz output data rate; 1: 400 Hz output data rate)

PD Power Down Control. Default value: 0

(0: power down mode; 1: active mode)

FS Full Scale selection. Default value: 0

(refer to Table 3 for typical full scale value)

STP, STM Self Test Enable. Default value: 0

(0: normal mode; 1: self test P, M enabled)

Zen Z axis enable. Default value: 1

(0: Z axis disabled; 1: Z axis enabled)

Yen Y axis enable. Default value: 1

(0: Y axis disabled; 1: Y axis enabled)

Xen X axis enable. Default value: 1

(0: X axis disabled; 1: X axis enabled)

DR bit allows to select the data rate at which acceleration samples are produced. The default value is 0 which corresponds to a data-rate of 100Hz. By changing the content of DR to “1” the selected data-rate will be set equal to 400Hz.

PD bit allows to turn on the turn the device out of power-down mode. The device is in powerdown mode when PD= “0” (default value after boot). The device is in normal mode when PD is set to 1.

STP, STM bit is used to activate the self test function. When the bit is set to one, an output change will occur to the device outputs (refer to Table 3 and 4 for specification) thus allowing to check the functionality of the whole measurement chain.

26/42

Page 27

LIS302DL Register description

Zen bit enables the generation of Data Ready signal for Z-axis measurement channel when

set to 1. The default value is 1.

Yen bit enables the generation of Data Ready signal for Y-axis measurement channel when set to 1. The default value is 1.

Xen bit enables the generation of Data Ready signal for X-axis measurement channel when set to 1. The default value is 1.

7.3 CTRL_REG2 (21h)

Table 20. CTRL_REG2 (21h) register

SIM BOOT -- FDS

Table 21. CTRL_REG2 (21h) register description

SIM SPI Serial Interface Mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface)

BOOT Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

HP_FF_WU2HP_FF_W

HP_coeff2 HP_coeff1

FDS Filtered Data Selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter sent to output register)

HP FF_WU2 High Pass filter enabled for FreeFall/WakeUp # 2. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPFF_WU1 High Pass filter enabled for Free-Fall/Wake-Up #1. Default value: 0

(0: filter bypassed; 1: filter enabled)

HP coeff2 HP coeff1

High pass filter cut-off frequency configuration. Default value: 00 (See table below)

SIM bit selects the SPI Serial Interface Mode. When SIM is ‘0’ (default value) the 4-wire interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire interface mode output data are sent to SDA_SDI pad.

BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to ‘0’.

FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the sensor

HP_coeff[2:1]. These bits are used to configure high-pass filter cut-off frequency ft.

27/42

Page 28

Table 22. High pass filter cut-off frequency configuration

HP_coeff2,1

00 2 8

01 1 4

10 0.5 2

11 0.25 1

ft (Hz)

(DR=100 Hz)

7.4 CTRL_REG3 [Interrupt CTRL register] (22h)

Table 23. CTRL_REG3 (22h) register

IHL PP_OD I2CFG2 I2CFG1 I2CFG0 I1CFG2 I1CFG1 I1CFG0

Table 24. CTRL_REG3 (22h) register description

IHL Interrupt active high, low. Default value 0.

(0: active high; 1: active low)

PP_OD Push-pull/Open Drain selection on interrupt pad. Default value 0.

(0: push-pull; 1: open drain)

I2CFG2 I2CFG1 I2CFG0

I1CFG2 I1CFG1 I1CFG0

Data Signal on Int2 pad control bits. Default value 000. (see table below)

Data Signal on Int1 pad control bits. Default value 000. (see table below)

ft (Hz)

(DR=400 Hz)

Table 25. CTRL_REG3 (22h) truth table

I1(2)_CFG2 I1(2)_CFG1 I1(2)_CFG0 Int1(2) Pad

0 0 0 GND

001 FF_WU_1

010 FF_WU_2

0 1 1 FF_WU_1 or FF_WU_2

100 Data ready

1 1 1 Click interrupt

7.5 HP_FILTER_RESET (23h)

Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0g. This allows to overcome the settling time of the high pass filter.

28/42

Page 29

LIS302DL Register description

7.6 STATUS_REG (27h)

Table 26. STATUS_REG (27h) register

ZXYOR ZOR YOR XOR ZYXDA ZDA YDA XDA

Table 27. STATUS_REG (27h) register desription

X, Y and Z axis data overrun. Default value: 0

ZYXOR

ZOR

YOR

XOR

(0: no overrun has occurred; 1: new data has over written the previous one before it was read)

Z axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one)

Y axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one)

X axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one)

ZYXDA X, Y and Z axis new data available. Default value: 0

(0: a new set of data is not yet available; 1: a new set of data is available)

ZDA Z axis new data available. Default value: 0

(0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available)

YDA Y axis new data available. Default value: 0

(0: a new data for the Y-axis is not yet available; 1: a new data for the Y-axis is available)

XDA X axis new data available. Default value: 0

(0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available)

7.7 OUT_X (29h)

Table 28. OUT_X (29h) register

XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

X axis output data.

7.8 OUT_Y (2Bh)

Table 29. OUT_Y (2Bh) register description

YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0

Y axis output data.

29/42

Page 30

7.9 OUT_Z (2Dh)

Table 30. OUT_Z (2Dh) register

ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0

Z axis output data.

7.10 FF_WU_CFG_1 (30h)

Table 31. FF_WW_CFG_1 (30h) register

AOI LIR ZHIE ZLIE YHIE YLIE XHIE XLIE

Table 32. FF_WW_CFG_1(30h) register description

AOI

LIR

ZHIE

And/or combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events; 1: AND combination of interrupt events)

Latch Interrupt request into FF_WU_SRC reg with the FF_WU_SRC reg cleared by reading FF_WU_SRC_1 reg. Default value: 0

(0: interrupt request not latched; 1: interrupt request latched)

Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

ZLIE

YHIE

YLIE

XHIE

XLIE

Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

30/42

Page 31

LIS302DL Register description

7.11 FF_WU_SRC_1 (31h)

Table 33. FF_WU_SRC_1 (31h) register

X IA ZHZLYHYLXHXL

Table 34. FF_WU_SRC_1 (31h) register description

Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one ore more interrupt has been generated)

Z high. Default value: 0 (0: no interrupt, 1: ZH event has occurred)

Z low. Default value: 0 (0: no interrupt; 1: ZL event has occurred)

Y high. Default value: 0 (0: no interrupt, 1: YH event has occurred)

Y low. Default value: 0 (0: no interrupt, 1: YL event has occurred)

X high. Default value: 0 (0: no interrupt, 1: XH event has occurred)

X low. Default value: 0 (0: no interrupt, 1: XL event has occurred)

Free-fall and wake-up source register. Read only register.

Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and allows the refreshment of data in the FF_WU_SRC_1 register if the latched option was chosen.

7.12 FF_WU_THS_1 (32h)

Table 35. FF_WU_THS_1 (32h) register

DCRM THS6 THS5 THS4 THS3 THS2 THS1 THS0

Table 36. FF_WU_THS_1 (32h) register description

DCRM

THS6, THS0 Free-fall / wake-up threshold: default value: 000 000x

Resetting mode selection. Default value: 0 (0: counter resetted; 1: counter decremented)

Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration counter is decremented.

31/42

Page 32

7.13 FF_WU_DURATION_1 (33h)

Table 37. FF_WU_DURATION_1 (33h) register

D7 D6 D5 D4 D3 D2 D1 D0

Table 38. FF_WU_DURATION_1 (33h) register description

D7-D0 Duration value. Default value: 0000 0000

Duration register for Free-Fall/Wake-Up interrupt 1. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified

7.14 FF_WU_CFG_2 (34h)

Table 39. FF_WU_CFG_2 (34h) register

AOI LIR ZHIE ZLIE YHIE YLIE XHIE XLIE

Table 40. FF_WU_CFG_2 (34h) register description

AOI And/or combination of Interrupt events. Default value: 0

(0: OR combination of interrupt events; 1: AND combination of interrupt events)

LIR Latch interrupt request into FF_WU_SRC reg with the FF_WU_SRC reg cleared by

reading FF_WU_SRC_2 reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched)

ZHIE Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

ZLIE Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)

YHIE Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

YLIE Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)

XHIE Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)

XLIE Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)

32/42

Page 33

LIS302DL Register description

7.15 FF_WU_SRC_2 (35h)

Table 41. FF_WU_SRC_2 (35h) register

X IA ZH ZLYHYLXHXL

Table 42. FF_WU_SRC_2 (35h) register description

IA Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupt event has been generated)

ZH Z high. Default value: 0

(0: no interrupt; 1: ZH event has occurred)

ZL Z low. Default value: 0

(0: no interrupt; 1: ZL event has occurred)

YH Y high. Default value: 0

(0: no interrupt; 1: YH event has occurred)

YL Y low. Default value: 0

(0: no interrupt; 1: YL event has occurred)

XH X high. Default value: 0

(0: no interrupt; 1: XH event has occurred)

XL X low. Default value: 0

(0: no interrupt; 1: XL event has occurred)

Free-fall and wake-up source register. Read only register.

Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt and allows the refreshment of data in the FF_WU_SRC_2 register if the latched option was chosen.

7.16 FF_WU_THS_2 (36h)

Table 43. FF_WU_THS_2 (36h) register

DCRM THS6 THS5 THS4 THS3 THS2 THS1 THS0

Table 44. FF_WU_THS_2 (36h) register description

DCRM Resetting mode selection. Default value: 0

(0: counter resetted; 1: counter decremented)

THS6, THS0 Free-fall / wake-up Threshold. Default value: 000 0000

7.17 FF_WU_DURATION_2 (37h)

Table 45. FF_WU_DURATION_2 (37h) register

D7 D6 D5 D4 D3 D2 D1 D0

33/42

Page 34

Table 46. FF_WU_DURATION_2 (37h) register description

D7-D0 Duration value. Default value: 0000 0000

Duration register for Free-Fall/Wake-Up interrupt 2. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified.

7.18 CLICK_CFG (38h)

Table 47. CLICK_CFG (38h) register

- LIR Double_Z Single_Z Double_Y Single_Y Double_X Single_X

Table 48. CLICK_CFG (38h) register description

LIR Latch interrupt request into CLICK_SRC reg with the CLICK_SRC reg

refreshed by reading CLICK_SRC reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched)

Double_Z Enable interrupt generation on double click event on Z axis. Default value: 0