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LH5P864
CMOS 512K (64K × 8) Pseudo-Static RAM
FEATURES
•• 65,536 × 8 bit organ ization
•• Access time: 80 ns (MAX.)
•• Cycle ti me: 140 ns (MIN.)
•• Single +5 V p owe r su ppl y
•• Powe r consu mption :
Operating : 44 0 mW (MAX.)
Standb y (TTL level): 22 mW (MAX.)
Standb y (CMOS level): 2.75 mW (MAX.)
•• Operatin g temperature: 0 to 70°C
•• TTL compatible I/O
•• 512 refresh cycles /8 ms (MAX.)
•• Available for auto-refresh and
self-refresh modes
•• Package: 32-pin, 525 -mil SOP
DESCRIPTION
The LH5P864 is a 512K-bit P seudo-Static RA M organized as 65,536 × 8 bits. It is fabricated using silicon-gate CMOS process technology. With its built-in
oscillator, it is easy to refresh memories without an
external clock.
PIN CONNECTIONS
5P864-1
TOP VIEW
5
6
7
8
11
12
A
0
A
3
26
25
24
23
22
21
18
A
5
A
4
9
10
A
1
A
2
20
19
A
6
A
9
A
11
A
10
13
14
15
28
27
I/O
0
A
13
16
17
I/O
2
OE/RFSH
CE
1
A
7
GND
I/O
4
I/O
3
I/O
5
A
8
32-PIN SOP
3
4
A
12
30
29
CE
2
A
14
R/W
1
2
NC
32
31
V
CC
TEST
NC
I/O
1
I/O
6
I/O
7
Figure 1. Pin Connections for SOP Package
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I/O
1
CLOCK
GENERATOR
CE
1
R/W
A
12
A
13
A
14
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
11
A
10
A
2
A
1
A
0
COLUMN
ADDRESS
BUFFER
ROW
ADDRESS
BUFFER
REFRESH
ADDRESS
COUNTER
DATA
IN
BUFFER
DATA
OUT
BUFFER
I/O
SELECTOR
COLUMN
DECODER
SENSE
AMPS
ROW
DECODER
EXT/INT
ADDRESS
MUX
REFRESH
CONTROLLER
REFRESH
TIMER
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
V
BB
GENERATOR
GND
V
CC
5P864-2
I/O
0
RFSH
OE/
12
11
10
9
8
7
6
5
27
26
23
25
4
28
3
22
24
29
16
32
13
14
15
17
18
19
20
21
30
CE
2
MEMORY
ARRAY
256K
MEMORY
ARRAY
256K
A8 - A
14
A0 - A
7
1
TEST
1
Figure 2. LH5P864 Block Diagram
PIN DESCRIPTION
SIGNA L PIN N AME
A0 - A
14
Addre ss input
R/W Read/ Write En ab le i npu t
OE/RFSH
Outpu t E nab le inp ut/R efr esh
input
CE1, CE
2
Chip Ena ble in put
I/O0 - I/O
7
Data inp ut/out put
SIGNAL PIN NAME
V
CC
Power Sup ply
GND Ground
Test Test In put
NC No Connec tion
LH5P864 CMOS 512K (64K × 8) Pseudo-Static RAM
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ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Appli ed v ol tage on an y p in V
T
-1.0 to +7.0 V 1
Output sh ort ci rcu it c urr ent I
O
50 mA
Power dis sipati on P
D
600 mW
Operating temperature Topr 0 to +70
°C
Storage temperature Tstg -65 to +150
°C
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CON DITIONS (TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Suppl y v olt age V
CC
4.5 5.0 5.5 V
Input vol tage
V
IH
2.4 VCC + 0.3 V
V
IL
-1.0 0.8 V
CAPACITANCE (TA = 0 to +70°C, f = 1MHz, VCC = 5.0 V ±10%)
PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT
Input cap acitan ce
A
0
- A
14
C
IN1
8pF
R/W,
OE/RF SH C
IN2
8pF
CE1, CE
2
C
IN3
8pF
TEST
1
C
IN4
10 pF
Input/ Out put ca pac ita nce I/O
0
- I/O
7
C
OUT1
10 pF
DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5.0 V ±10%)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Operat ing cu rre nt I
CC1
tRC = tRC (MIN.) 80 mA 1, 2
Standb y c urr ent I
CC2
TTL inpu t
4.0 mA 1, 3, 5
CMOS i npu t
0.5 mA 1, 3, 6
Self r efr esh av era ge c urr ent I
CC3
TTL inpu t
4.0 mA 1, 4, 5
CMOS input 0.5 mA 1, 4, 6
Input lea kag e c urr ent I
LI
0 V ≤ VIN ≤ 6 .5 V,
0 V ex cep t o n t est pin s
-10 10
µA
Output le aka ge cur ren t
I
LO
0 V ≤ V
OUT
≤ VCC + 0.3 V,
Output s i n H igh -Z s tat e
-10 10 µA
Output HI GH vol tag e V
OH
I
OUT
= -1 .0 m A 2.4 V
Output LO W v olt age V
OL
I
OUT
= 4. 0 mA 0.4 V
NOTES:
1. Specified values are w ith outputs open.
2. I
CC1
depends on the cycle time.
3.
CE1 = CE2 = VIH, OE/RFSH = V
IH
4. CE1 = CE2 = VIH, OE/RFSH = V
IL
5. CE1 = CE2 = VCC – 0. 2 V, OE/RFSH = V
CC
– 0.2 V
6.
CE1 = CE2 = VCC – 0. 2 V, OE/R FSH = 0.2 V
CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 864
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AC CHARACTERISTICS
1,2,3
(TA = 0 to +70°C, VCC = 5.0 V ±10%)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Random re ad, wri te cyc le tim e t
RC
140 ns
Read m odi fy wri te c yc le time t
RMW
205 ns
CE pul se wid th t
CE
80 10,000 ns
CE pre cha rge ti me t
P
50 ns
Addres s s etu p t ime t
AS
0ns4
Addres s h old ti me t
AH
20 ns 4
Read c omm and se tup ti me t
RCS
0ns
Read c omm and ho ld time t
RCH
0ns
CE acc es s t ime t
CE A
80 ns 5
OE acces s time t
OEA
30 ns 5
CE to out put in Low -Z t
CLZ
20 ns
OE to out put in Low -Z t
OLZ
0ns
R/W to ou tpu t in Lo w-Z t
WLZ
0ns
Chip d isa ble to ou tpu t i n Hi gh- Z t
CHZ
25 ns
Output disable to outp ut in High-Z t
OHZ
25 ns
Write enab le to output in Hig h-Z t
WHZ
25 ns
OE setup tim e t
OES
10 ns
OE hold time t
OEH
10 ns
OE lead time t
OE L
10 ns
Write c omma nd pul se wid th t
WCP
30 ns
Write c omma nd set up tim e t
WCS
30 ns
Write c omma nd hol d t ime
t
WCH
50 ns
Data s etu p t ime fro m w rite
t
DS W
30 ns 6
Data s etu p t ime fro m CE
t
DSC
30 ns 6
Data h old ti me f rom wri te
t
DHW
0ns6
Data h old ti me f rom CE
t
DHC
0ns6
Transiti on time (r ise an d fa ll) t
T
335ns
Refres h t ime in terv al t
REF
8ms
Auto r efr esh cy cle ti me t
FC
130 ns
Refres h d ela y t ime fro m
CE t
RFD
50 ns
Refres h p uls e w idt h ( Aut o re fre sh) t
FAP
30 8,000 ns
Refres h p rec har ge time (A uto re fres h) t
FP
30 ns
CE del ay tim e f rom ref res h pr ech arg e ( Aut o
refres h)
t
FCE
160 ns
Refres h p uls e w idt h ( Sel f re fre sh) t
FAS
8,000 ns
CE del ay tim e f rom ref res h pr ech arg e ( Sel f re fre sh) t
FRS
160 ns
NOTES:
1. I n order to initialize the circuit, CE1, CE2 and OE/RFSH should
be kept in VIH for 100 µs after power-up and followed by at least
8 dummy cycles.
2. AC characteristics are m easur ed at t
T
= 5 ns.
3. AC character istics are measured at the following condition (see
figure at right).
4. Address is latched at the negative edge of
CE1 or CE2.
5. M easured with a load equivalent to 2TTL + 100 pF.
6. Data is latched at the positive edge of R/W or at the positive edge
of
CE1 or CE2.
2.4 V
0.8 V
2.6 V
0.6 V
2.2 V
0.8 V
OUTPUT
INPUT
5P864-3
Figure 3. AC Characteristics
LH5P864 CMOS 512K (64K × 8) Pseudo-Static RAM
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t
AS
t
AH
ADDRESS INPUT
t
P
t
RC
t
CE
CE
2
(OR CE1)
V
IH
V
IL
t
RCS
R/W
V
IH
V
IL
t
OHZ
t
OEA
t
CEA
t
CHZ
t
RCH
I/O0 - I/O
7
V
OH
V
OL
A0 - A
14
V
IH
V
IL
OE/RFSH
V
IH
V
IL
5P864-4
VALID-DATA OUTPUT
V
IH
V
IL
t
P
t
OES
t
OEL
t
OEH
t
OLZ
t
CLZ
CE
1
(OR CE2)
Figure 4. Read Cycle
CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 864
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t
AS
t
AH
ADDRESS INPUT
t
P
t
RC
t
CE
CE
2
(OR CE1)
V
IH
V
IL
R/W
V
IH
V
IL
I/O0 - I/O
7
A0 - A
14
V
IH
V
IL
OE/RFSH
V
IH
V
IL
5P864-5
VALID-DATA INPUT
V
IH
V
IL
t
P
t
OEH
t
OES
CE
1
(OR CE2)
t
WCH
t
WCS
t
WCP
t
DSW
t
DSC
t
DHW
t
DHC
V
IH
V
IL
Figure 5. Write Cycle
LH5P864 CMOS 512K (64K × 8) Pseudo-Static RAM
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t
AS
t
AH
ADDRESS INPUT
t
P
t
RMW
CE
2
(OR CE1)
V
IH
V
IL
R/W
V
IH
V
IL
I/O0 - I/O
7
A0 - A
14
V
IH
V
IL
OE/RFSH
V
IH
V
IL
5P864-6
VALID-DATA INPUT
V
IH
V
IL
t
P
CE
1
(OR CE2)
t
DSW
t
DSC
t
DHW
t
DHC
t
OES
t
OEH
t
RCS
t
WCP
t
WCS
VALID-DATA
OUTPUT
t
CHZ
t
WLZ
t
OHZ
t
WHZ
t
CLZ
t
OLZ
t
CEA
t
OEA
V
OH
V
OL
V
IH
V
IL
Figure 6. Read-Modify-Wri te Cycle
CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 864
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t
AS
t
AH
ADDRESS INPUT
t
P
t
RC
t
CE
CE
2
(OR CE1)
V
IH
V
IL
R/W
A
0 - A7
V
IH
V
IL
OE/RFSH
V
IH
V
IL
5P864-7
V
IH
V
IL
t
P
CE
1
(OR CE2)
t
OES
t
OEH
t
RCS
t
RCH
I/O0 - I/O
7
NOTE: A8 - A14 Don't Care
HIGH-Z
V
IH
V
IL
V
OH
V
OL
Figure 7. C E Only Refresh Cycle
t
FC
CE
1
5P864-8
I/O0 - I/O
7
NOTE: A0 - A14, R/W Don't Care
HIGH-Z
V
IH
V
IL
V
OH
V
OL
t
RFD
t
FCE
t
FAP
t
FP
t
FAP
V
IH
V
IL
OE/RFSH
V
IH
V
IL
CE
2
Fig ure 8. Auto Refresh Cycl e
LH5P864 CMOS 512K (64K × 8) Pseudo-Static RAM
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t
FAS
CE
1
5P864-9
I/O0 - I/O
7
HIGH-Z
V
IH
V
IL
V
OH
V
OL
t
RFD
t
FRS
V
IH
V
IL
OE/RFSH
V
IH
V
IL
CE
2
NOTE: A0 - A14, R/W Don't Care
Figure 9. Self Refresh Cycle
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32SOP (SOP032-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
20.80 [0.819]
20.40 [0.803]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
32
17
161
1.40 [0.055]
1.40 [0.055]
32SOP
32-pin, 525-mil SOP
PACKAGE DIAGRAM
CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 864
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80 Access Time (ns)
LH5P864
Device Type
N
Package
- ##
Speed
5P864-10
CMOS 512K (64K x 8) Pseudo-Static RAM
Example: LH5P864N-80 (CMOS 512K (64K x 8) Pseudo-Static RAM, 80 ns, 32-pin, 525-mil SOP)
32-pin, 525-mil SOP (SOP032-P-0525)
ORDERING INFORMATION
LH5P864 CMOS 512K (64K × 8) Pseudo-Static RAM
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