Page 1
LH5P860
CMOS 512K (64K × 8) Pseudo-Static RAM
FEATURES
•• 65,536 × 8 bit organ ization
•• Access time: 80 ns (MAX.)
•• Cycle ti me: 140 ns (MIN.)
•• Single +5 V p owe r su ppl y
•• Pin co mpatib le wi th 1M standar d SRAM
•• Powe r consu mption (MAX.):
Operating : 44 0 mW
Se lf refre sh (T TL level ) : 5.5 mW
Self refresh (CMOS level): 2.75 mW
•• TTL compatible I/O
•• 512 refresh cycles /8 ms (MAX.)
•• Available for auto-refresh and self-refresh
mode s
•• Packa ges:
32-pi n , 600 -mil DIP
32-pi n , 525 -mil S OP
DESCRIPTION
The LH5P860 is a 512K-bit Pseudo-Static RAM o rganized a s 65,536 × 8 bits. It is fabrica ted using silicon-gate CMOS process technology. With its built-in
oscillator, it is easy to refresh memories without an
external clock.
PIN CONNECTIONS
V
CC
A
15
CE
R/W
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
I/O
I/O
I/O
I/O
TOP VIEW
2
1
7
6
5
4
3
32-PIN DIP
32-PIN SOP
RFSH
NC
A
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
GND
1
2
3
14
4
12
5
7
6
6
7
5
8
4
9
3
10
2
11
1
12
0
13
0
14
1
15
2
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Figure 1. Pin Connecti ons for DIP and
SOP Packages
5P860-1
1
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LH5P860 CMOS 512K (64K × 8) Pseudo-Static RAM
16
GND
32
V
CC
12
A
0
A
11
1
A
10
2
A
9
A
3
8
A
4
A
7
5
6
A
6
5
A
7
27
A
8
A
26
9
A
23
A0 - A
10
25
A
11
A
4
12
A
28
13
3
A
14
31
A
15
- A
9
COLUMN
15
ADDRESS
BUFFER
ROW
ADDRESS
8
BUFFER
REFRESH
ADDRESS
COUNTER
EXT/INT
ADDRESS
MUX
ROW
DECODER
COLUMN
DECODER
SENSE
AMPS
MEMORY
ARRAY
512 K
SELECTOR
I/O
V
GENERATOR
BB
DATA
IN
BUFFER
DATA
OUT
BUFFER
13
14
15
17
18
19
20
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
22
CE
CE
RFSH
OE
R/W
1
30
2
1
24
29
CLOCK
GENERATOR
PIN DESCRIPTION
SIGNA L PIN N AME
A0 - A
15
R/W Read/ Write in put
OE Outpu t E nab le inp ut
RFSH Refre sh input
CE1, CE
Addre ss input
Chip Ena ble in put
2
REFRESH
CONTROLLER
REFRESH
TIMER
Figure 2. LH5P860 Block Diagram
SIGNAL PIN NAME
I/O0 - I/O
7
V
CC
GND Groun d
NC No Conn ect ion
5P860-2
Data inp ut/ out put
Powe r S upp ly
2
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CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 860
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Appli ed v ol tage on al l p ins V
Output sh ort ci rcu it c urr ent I
Power dis sipati on P
T
O
D
Operating temperature Topr 0 to +70
Storage temperature Tstg –65 to +150
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
–1.0 to +7.0 V 1
50 mA
600 mW
°C
°C
RECOMMENDED OPERATING CON DITIONS (TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Suppl y v olt age
V
CC
4.5 5.0 5.5 V
GND 0 0 0 V
Input vol tage
V
IH
V
IL
2.4 VCC + 0.3 V
–1.0 0.8 V
CAPACITANCE (TA = 0 to +70°C, f = 1 MHz, VCC = 5.0 V ±10%)
PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT
A
Input cap acitan ce
R/W,
CE1, CE
Input/ Out put ca pac ita nce I/O
– A
0
OE, R FSH
– I/O
0
15
2
7
C
C
C
C
IN1
IN2
IN3
OUT1
8pF
5pF
5pF
10 pF
DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5.0 V ±10%)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Average su ppl y c urr ent in
normal op era tio n
Suppl y c urre nt in
standb y m ode
Average su ppl y c urr ent in
self r efr esh cy cle
Input lea kag e c urr ent I
I/O le aka ge cur ren t
Output HI GH vol tag e V
Output LO W v olt age V
NOTES:
1. Specified values are w ith outputs open.
depends on the cycle time.
2. I
CC1
CE1 = VIH, RFSH = VIH.
3.
4.
CE1 = VCC – 0.2 V, RFSH = V
5. CE1 = VIH, RFSH = VIL.
CE1 = VCC – 0.2 V, R FS H = 0.2 V.
6.
CC
I
CC1
I
CC2
I
CC3
LI
I
LO
OH
OL
– 0.2 V.
TTL inpu t 1.0
CMOS input 0.5 1, 4
TTL inpu t
CMOS input 0.5 1, 6
0 V ≤ VIN ≤ 6 .5 V,
0 V ex cep t o n t est pin s
0 V ≤ V
≤ VCC + 0.3 V,
OUT
Output s i n h igh -imp eda nc e
state
I
= –1 .0 m A 2.4 V
OUT
I
= 4. 0 mA 0.4 V
OUT
80 mA 1, 2
mA
1.0
–10 10
mA
µA
–10 10 µA
1, 3
1, 5
3
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LH5P860 CMOS 512K (64K × 8) Pseudo-Static RAM
AC CHARACTERISTICS
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
1, 2, 3
(TA = 0 to +70°C, VCC = 5.0 V ±10%)
Random re ad, wri te cyc le tim e t
Read m odi fy wri te c yc le time t
CE pul se wid th t
CE pre cha rge ti me t
Addres s s etu p t ime t
Addres s h old ti me t
Read c omm and se tup ti me t
Read c omm and ho ld time t
CE acc es s t ime t
OE acces s time t
Output en abl e t ime fro m
Output en abl e t ime fro m
CE t
OE t
Output en abl e t ime fro m R /W t
Output di sab le tim e fr om
Output di sab le tim e fr om
CE t
OE t
Output di abl e t ime fro m R /W t
OE setup tim e t
OE hold time t
Write c omma nd pul se wid th t
Write c omma nd set up tim e t
Write c omma nd hol d t ime t
Data s etu p t ime fro m R /W
Data s etu p t ime fro m CE
Data h old ti me f rom R/ W
Data h old ti me f rom CE
Transiti on time (r ise an d fa ll)
Refres h t ime in terv al t
Refres h c omm and ho ld time t
Auto r efr esh cy cle ti me t
Refres h d ela y t ime fro m
CE t
Refres h p uls e w idt h ( Aut o re fre sh) t
Refres h p rec har ge time (A uto re fres h) t
Refres h p uls e w idt h ( Sel f re fre sh) t
CE del ay tim e f rom ref res h pr ech arg e ( Sel f re fre sh) t
NOTES:
1.
In order to initialize the circuit, an initialize pause of 100 µs w ith
CE1 = VIH, RFSH = VIH (or CE2 = VIL, RFSH = VIH) is required
af ter power-up, followed by at least 8 dummy cycles.
2. AC characteristics are m easur ed at t
3. AC characteristics are m easur ed at the follow ing condition (see
figure at right):
4. Address is latched at the negative edge of
edge of CE2.
5. M easured with a load equivalent to 2TTL + 100 pF.
6. Data is latched at the positive edge of R/W, at the positive edge
CE1, or at the negative edge of CE2.
of
= 5 ns.
T
CE1 or at the positive
RC
RMW
CE
AS
AH
RCS
RCH
CE A
OEA
CLZ
OLZ
WLZ
CHZ
OHZ
WHZ
OES
OEH
WP
WCS
WCH
t
DS W
t
DSC
t
DHW
t
DHC
t
REF
RHC
FC
RFD
FAP
FP
FAS
FRS
P
T
140 ns
205 ns
80 10,000 ns
50 ns
0ns4
20 ns 4
0ns
0ns
80 ns 5
30 ns 5
20 ns
0ns
0ns
25 ns
25 ns
25 ns
10 ns
10 ns
30 ns
30 ns
50 ns
30 ns 6
30 ns 6
0ns6
0ns6
335ns
8ms
15 ns
130 ns
50 ns
30 8,000 ns
30 ns
8,000 ns
160 ns
INPUT
OUTPUT
2.4 V
0.8 V
2.2 V
0.8 V
Figure 3. AC Characteristics
2.6 V
0.6 V
5P860-12
4
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CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 860
t
RC
t
CE
CE
CE
t
P
V
IH
V
1
IL
V
IH
2
V
IL
A0 - A
I/O0 - I/O
OE
R/W
7
t
AS
V
IH
15
V
IL
V
IH
V
IL
t
RCS
V
IH
V
IL
V
OH
V
OL
t
FP
t
FRS
t
AH
ADDRESS
INPUT
t
RHC
t
CLZ
t
CEA
t
OLZ
t
OEA
VALID-DATA
OUTPUT
t
OHZ
t
RCH
t
CHZ
t
RFD
V
RFSH
IH
V
IL
NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 4. Read Cycle
5P860-3
5
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LH5P860 CMOS 512K (64K × 8) Pseudo-Static RAM
t
RC
CE
CE
t
P
V
IH
V
1
IL
V
IH
2
V
IL
t
CE
A0 - A
OE
R/W
I/O0 - I/O
t
AS
V
IH
15
V
IL
t
OES
V
IH
V
IL
V
IH
V
IL
V
OH
V
7
OL
t
FP
t
FRS
t
AH
ADDRESS
INPUT
t
RHC
t
WCH
t
OEH
t
WCS
t
WP
t
DSW
t
DSC
t
DHW
t
DHC
DATA INPUT
t
RFD
V
RFSH
IH
V
IL
NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 5. Write Cycle 1 (OE = Fix ‘H’)
6
5P860-4
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CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 860
t
RC
t
CE
CE
CE
t
P
V
IH
V
1
IL
V
IH
V
2
IL
I/O0 - I/O
A0 - A
7
OE
R/W
D
t
AS
V
IH
15
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
IN
V
IL
t
AH
ADDRESS
INPUT
t
CLZ
t
WCH
t
OHZ
t
WHZ
t
WCS
t
WP
t
DSW
t
DSC
t
DHW
t
DHC
DATA INPUT
t
OLZ
t
WLZ
t
CHZ
V
OH
D
OUT
V
OL
t
FP
t
RFSH
t
V
IH
V
IL
FRS
RHC
NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 6. Write Cycle 2 ( OE Clock)
t
RFD
5P860-5
7
Page 8
LH5P860 CMOS 512K (64K × 8) Pseudo-Static RAM
t
RC
CE
CE
t
P
V
IH
V
1
IL
V
IH
2
V
IL
t
CE
I/O0 - I/O
7
A0 - A
R/W
D
OE
D
OUT
t
AS
V
IH
15
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
IN
V
IL
V
OH
V
OL
t
FP
t
FRS
t
ADDRESS
INPUT
t
CLZ
t
RHC
AH
t
WCH
t
WHZ
t
WP
t
DSW
t
WCS
DATA INPUT
t
WLZ
t
DSC
t
DHW
t
t
FD
t
DHC
t
CHZ
RFD
V
RFSH
IH
V
IL
NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 7. Write Cycle 3 (OE = Fix ‘L’)
8
5P860-6
Page 9
CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 860
t
RMW
t
P
V
IH
CE
1
V
IL
V
IH
CE
2
V
IL
I/O0 - I/O
7
A0 - A
R/W
D
OE
D
OUT
t
AS
V
IH
15
V
IL
V
IH
V
IL
t
RCS
V
IH
V
IL
V
IH
IN
V
IL
V
OH
V
OL
t
AH
ADDRESS
INPUT
t
OLZ
t
CLZ
t
CEA
t
OEA
t
OHZ
DATA
OUTPUT
t
WHZ
t
WCS
t
WP
t
DSW
t
DSC
DATA
INPUT
t
WLZ
t
DHW
t
CHZ
t
DHC
t
FP
RFSH
t
V
IH
V
IL
FRS
t
RHC
NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 8. Read-Modify-Wri te Cycle
t
RFD
5P860-7
9
Page 10
LH5P860 CMOS 512K (64K × 8) Pseudo-Static RAM
t
RC
CE
CE
t
P
V
IH
V
1
IL
V
IH
2
V
IL
t
CE
V
OE
R/W
IH
V
8
IL
V
IH
V
IL
V
IH
V
IL
V
OH
7
V
OL
V
IH
V
IL
A0 - A
I/O0 - I/O
RFSH
NOTES:
1. Operation is possible using only CE
2. A
- A16 = Don't Care.
9
t
t
OES
RCS
t
AS
t
AH
ADDRESS
INPUT
OPEN
t
FP
t
t
(CE1) by fixing CE1 to LOW (CE2 to HIGH).
2
FRS
RHC
t
OEH
t
t
RCH
RFD
5P860-8
10
Figure 9. C E Only Refresh Cycle
Page 11
CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 860
V
IH
CE
1
V
IL
V
IH
CE
2
V
IL
OR
V
IH
CE
1
V
IL
CE
2
RFSH
I/O0 - I/O
7
NOTE: OE, R/W, A0 - A
CE
1
CE
2
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
= Don't care
16
V
IH
V
IL
V
IH
V
IL
t
FC
t
RFD
t
FP
t
FAP
t
FP
OPEN
Figure 11. Auto Refresh Cycle
t
FAP
t
FC
t
RHC
t
FP
5P860-9
OR
CE
1
CE
2
RFSH
I/O0 - I/O
7
NOTE: OE, R/W, A0 - A
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
= Don't care
16
t
RFD
t
FP
t
FAS
OPEN
Figure 10. Self Refresh Cycle
t
FRS
t
RHC
5P860-10
11
Page 12
LH5P860 CMOS 512K (64K × 8) Pseudo-Static RAM
PACKAGE DIAGRAMS
32DIP (DIP032-P-0600)
1732
DETAIL
13.45 [0.530]
12.95 [0.510]
116
41.30 [1.626]
40.70 [1.602]
4.50 [0.177]
4.00 [0.157]
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
DIMENSIONS IN MM [INCHES]
0.60 [0.024]
0.40 [0.016]
MAXIMUM LIMIT
MINIMUM LIMIT
0.51 [0.020] MIN.
0.30 [0.012]
0.20 [0.008]
32-pin, 600-mil DIP
32SOP (SOP032-P-0525)
1.27 [0.050]
0.50 [0.020]
0.30 [0.012]
32
TYP.
1.40 [0.055]
17
0° TO 15°
15.24 [0.600]
TYP.
32DIP
12
20.80 [0.819]
20.40 [0.803]
DIMENSIONS IN MM [INCHES]
161
0.15 [0.006]
MAXIMUM LIMIT
MINIMUM LIMIT
11.50 [0.453]
11.10 [0.437]
1.40 [0.055]
1.275 [0.050]
1.275 [0.050]
14.50 [0.571]
13.70 [0.539]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.00 [0.000]
32-pin, 525-mil SOP
12.50 [0.492]
0.20 [0.008]
0.10 [0.004]
32SOP
Page 13
CMOS 512K (64K × 8) Pseudo-Stat ic R AM LH5P 860
ORDERING INFORMATION
LH5P860
Device Type
X
Package
- ##
Speed
80 Access Time (ns)
D 32-pin, 600-mil DIP (DIP032-P-0600)
N 32-pin, 525-mil SOP (SOP032-P-0525)
CMOS 512K (64K x 8) Pseudo-Static RAM
Example: LH5P860N-80 (CMOS 512K (64K x 8) Pseudo-Static RAM, 80 ns, 32-pin, 525-mil SOP)
5P860-11
13
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